Abstract: A master-slice type semiconductor integrated circuit device of the invention has a master substrate and a plurality of basic cells provided on the master substrate. Each of the basic cells includes a plurality of resistors and a plurality of transistors. A plurality of wirings are provided in the master substrate to form a predetermined logic circuit. The wirings in each of the basic cells are changed such that the current to flow in each transistor may be selected in a number of ways without the logical amplitude being changed in the logical circuit.

Abstract: A polycrystalline silicon layer 9 for a base leading electrode is formed on an element forming region divided by an element isolating layer which is formed by burying a BPSG film 8 in a groove. A depression generated on the element isolating layer is filled with a PSG film 11 which is formed as a part of an interlayer insulating film on the surface of the device including the polycrystalline silicon layer 9 by the spin-coating method so that the upper surface of the device is flattened. A polycrystalline silicon layer 13 is provided on the element isolating layer as a resistor layer so that the resistor layer is disposed between the adjacent transistors. The area of a circuit block is reduced to achieve a high integration and reduction in parasitic capacitance. This enables the high speed operation.

Abstract: An integrated semiconductor circuit includes a substrate, an epitaxial layer having transistor base regions, a first and a second (11) insulating oxide layer, and a protective layer. The first oxide layer carries heavily doped polycrystalline layers, including an electric contact layer, a screening layer and a connecting layer. The connecting layer electrically connects the screening layer to the epitaxial layer, through the electric contact layer. The screening layer prevents the occurrence of inversion and parasite components in the epitaxial layer between the base regions. The polycrystalline layer arrangement is simple and can be produced in a common process step. The arrangement is able to withstand high temperatures and enables the second insulating layer to be readily applied.

Abstract: An input protection structure for integrated circuits to be connected between an input and a reference potential includes a resistor. At least one transistor has a collector connected to the input, a base connected through the resistor to the reference potential, and an emitter connected to the reference potential. A semiconductor substrate has a first conduction type. The collector is in the form of a buried collector of a second conduction type in the semiconductor substrate. The base is in the form of at least one doped zone of the first conduction type having a base connection. The emitter is in the form of a doped zone of the second conduction type having an emitter connection. The resistor is in the form of at least one further doped zone of the first conduction type being connected to the emitter exclusively through the emitter connection and being connected to the base exclusively through the base connection.