Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.

Abstract: An electrostatic discharge (EDS) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The EDS device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.

Abstract: An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.

Abstract: A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).

Abstract: A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

Abstract: According to one embodiment, a semiconductor device includes: a substrate in which, on a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type and a semiconductor layer of the second conductivity type are stacked; trench that define an element forming region in the substrate; element isolation insulation film formed in the trench; and a semiconductor element formed in the element forming region. The trench include first trench formed from the surface of the substrate to boundary depth and second trench formed from the boundary depth to the bottom and having a diameter smaller than that of the first trench. First diffusion layers connected to the buried layer are formed around the first or second trench according to inter-element breakdown voltage required of the semiconductor element.

Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.

Abstract: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.

Abstract: Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.

Abstract: An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that |Vt1TR?Vt1DC|˜0.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.

Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

Abstract: Provided are an optoelectronic (OE) transmitter integrated circuit (IC) and method of fabricating the same using a selective growth process. In the OE transmitter IC, a driving circuit, which includes a double heterojunction bipolar transistor (DHBT) and amplifies received electric signals to drive an electroabsorption (EA) modulator, and the EA modulator with a multi-quantum well (MQW) absorption layer are integrated as a single chip on a semi-insulating substrate. The MQW absorption layer of the EA modulator and an MQW insertion layer of the DHBT are formed to different thicknesses from each other using a selective MOCVD growth process.

Abstract: The invention is directed to a semiconductor device having a diode element which prevents a leakage current due to a vertical parasitic bipolar transistor and enhances current efficiency. An element isolation insulation film is provided on an N well layer, and a first P+ layer and a second P+ layer are formed on the N well layer surrounded by the element isolation insulation film, the second P+ layer being formed at a distance from the first P+ layer. An electrode layer is formed on the N well layer between the first P+ layer and the second P+ layer. An N+ layer for a contact is formed on the N well layer between the element isolation insulation film and other element isolation insulation film. The first P+ layer is connected with an anode wiring, and the electrode layer, the second P+ layer, and the N+ layer are connected with a cathode wiring. A diode element utilizing a lateral PNP bipolar transistor is thus formed on the semiconductor substrate.

Abstract: A transistor assembly having a transistor includes a plurality of transistor regions, each of which has a vertical transistor structure having a collector semiconductor region, a base semiconductor region and an emitter semiconductor region, emitter contacting regions arranged above the transistor regions and base contacting regions connected to the base semiconductor regions via a polycrystalline semiconductor layer, wherein the polycrystalline semiconductor layer is structured such that the base contacting regions of transistor regions which are not part of the transistor are electrically isolated from base contacting regions of transistor regions which are part of the transistor.

Abstract: Disclosed is a semiconductor device with a bipolar transistor and method of fabricating the same. The device may include a collector region in a semiconductor substrate. A base pattern may be disposed on the collector region. A hard mask pattern may be disposed on the base pattern. The hard mask pattern may include a buffering insulation pattern and a flatness stopping pattern stacked in sequence. An emitter electrode may be disposed in a hole that locally exposes the base pattern, penetrating the hard mask pattern. A base electrode may contact an outer sidewall of the hard mask pattern and may be disposed on the base pattern. The flatness stopping pattern may contain an insulative material with etching selectivity to the buffering insulation pattern, the emitter electrode, and the base electrode.

Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.

Abstract: A semiconductor integrated circuit device (IC1) comprises a semiconductor chip (CHIP1), a first frame lead (FR1), and a second frame lead (FR2). The semiconductor chip (CHIP1) includes common-base transistors (P1, P2), pads (T11, T12) connected to the respective emitters of the common-base transistors (P1, P2), pads (T21, T22) connected to the respective collectors of the common-base transistors (P1, P2), and a means (DRV, ERR, E1) for generating a base signal. The pads (T11, T12) are connected through the respective bonding wires (W11, W12) to the first frame lead (FR1). The pads (T21, T22) are connected through the respective bonding wires (W21, W22) to the second frame lead (FR2). This structure can easily detect breaking of the bonding wires connected in parallel.

Abstract: An integrated circuit including a semiconductor assembly in thin-film SOI technology is disclosed. One embodiment provides a semiconductor assembly in thin-film SOI technology including a first semiconductor substrate structure of a second conductivity type inverse to a first conductivity type in a semiconductor substrate below a first semiconductor layer, a second semiconductor substrate structure of a second conductivity type in a semiconductor substrate below a second semiconductor layer structure, and a third semiconductor substrate structure of the first conductivity type below the first semiconductor layer structure in the semiconductor substrate and otherwise surrounded by the first semiconductor substrate structure.

Abstract: A semiconductor device including a bipolar transistor in which the collector resistance. The bipolar transistor includes a first conduction type semiconductor substrate having a main surface. A second conduction type collector region is formed in the semiconductor substrate. A shallow trench isolation structure isolates the main surface of the semiconductor substrate into two insulated active regions. A collector leading portion is formed in one of the active regions. A first conduction type base region and a second conduction type emitter region are formed on the other one of the active regions. The collector region has a first depth from the main surface immediately below the shallow trench isolation structure, and the collector region has a second depth from the main surface immediately below the two active regions. The first depth is less than the second depth.

Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.

Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

Abstract: The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and undercuts a portion of the active base region with an undercut angle of not more than about 90°. For example, the second STI region may a substantially triangular cross-section with an undercut angle of less than about 90°, or a substantially rectangular cross-section with an undercut angle of about 90°. Such a second STI region can be fabricated using a porous surface section formed in an upper surface of the collector region.

Abstract: A device for electrostatic discharge (ESD) protection is disclosed. The device for electrostatic discharge protection includes a lateral bipolar transistor and a diode. The semiconductor transistor has an emitter, a base and a collector electrically connected to a first power line (such as Vdd), a second power line (such as Vss) and a bond pad of an integrated circuit respectively. The diode has an n electrode and a p electrode electrically connected to the first power line and the bond pad respectively.

Abstract: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract: A method of performing a seasoning process for a semiconductor device processing apparatus is provided by the present invention. The method includes: forming a material layer on a test wafer; coating a photoresist on the material layer; patterning the photoresist so as to expose a central region of the wafer and cover an edge region thereof; and etching the material layer exposed by the photoresist pattern.

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

Abstract: This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.

Abstract: The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

Abstract: Method and apparatus for forming a semiconductor device. The method includes defining a plurality of rows in a semiconductor layer. Thereafter, on one or more of the plurality of rows, one or more bipolar junction devices are formed. Each of the bipolar junction devices has a first end region and a second end region. A quantity of a pre-amorphization ion is then implanted into at least one of the first end region and the second end region of a bipolar junction device for example. A silicide is formed in the semiconductor layer at the first end region and the second end region having implanted therein the quantity of the pre-amorphization ion. Additionally, laterally extending upper edges of the plurality of rows forming corners may be rounded prior to the implantation of the pre-amorphization.

Abstract: A high-frequency switching transistor comprises a collector area, which has a first conductivity type, a first barrier area bordering on the collector area, which has a second conductivity type which differs from the first conductivity type, and a semiconductor area bordering on the first barrier area, which has a dopant concentration which is lower than a dopant concentration of the first barrier area. Further, the high-frequency switching transistor has a second barrier area bordering on the semiconductor area, which has a first conductivity type, as well as a base area bordering on the second barrier area, which has a second conductivity type. Additionally, the high-frequency switching transistor comprises a third barrier area bordering on the semiconductor area, which has the second conductivity type and a higher dopant concentration than the semiconductor area. Further, the high-frequency switching transistor has an emitter area bordering on the third barrier area, which has the first conductivity type.

Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.

Abstract: A lateral semiconductor device includes: a semiconductor substrate formed on a base region therein; a plurality of emitter regions with a triangle arrangement in an upper part of the base layer and collector regions surrounding the emitter regions, respectively, apart from the emitter regions with a predetermined space through the base layer; the base layer formed in a concentric circular pattern on the upper part; the emitter regions and collector regions provided with contacts respectively; and emitter and collector wiring layers connected to the contacts.

Abstract: A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasitic bipolar transistor having the effect of reducing substrate conduction caused by a forward biased drain to body junction.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

Abstract: Electrostatic discharge (ESD) devices for protection of integrated circuits are described. ESD devices may be configured to provide uniform breakdown of finger regions extending through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. Such an EDS device may include a collector region having a middle region highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the EDS device. The lightly doped region may be eliminated in the collector region and an interlayer insulating layer is formed in contact with the top side regions and the middle region.

Abstract: A semiconductor structure having a self-aligned base contact and an emitter, where the base contact is electrically isolated from the emitter by a dielectric layer. The separation between the base contact and the emitter is determined by the thickness of the dielectric layer and the width of the emitter is determined by the minimum resolution provided by the fabrication techniques and tools used to define features within the dielectric layer.