Abstract: A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.

Abstract: A bipolar transistor structure for use in integrated circuits where the active device is processed on the sidewall of an n-hill so that the surface footprint does not depend on the desired area of active device region (emitter area). This structure, which is referred to as a Horizontal Current Bipolar Transistor (HCBT), consumes a smaller area of chip surface than conventional devices, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size. The device is fabricated with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires fewer etching processes and thermal oxidations than in conventional devices.

Abstract: In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

Abstract: At a surface region of an N?-type base region, surrounded by a P-type isolation region, a P+-type collector region, a P+-type emitter region, an N+-type base contact region, and an N-type rectifying region are formed. The N-type rectifying region straddles over the emitter region and the base contact region. The rectifying region has an impurity concentration higher than that of the base region, and lower than that of the base contact region. The forward voltage at the interface of the rectifying region and the emitter region is higher than the forward voltage at the interface of the base region and the emitter region. Therefore, the current from the emitter region flows to the collector region, and does not flow that much to the isolation region. By this, leakage current is small. Also, because the collector region does not surround the emitter region, the element size is small.

Abstract: A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.

Abstract: A transistor includes a means for providing a non-silicon-based emitter with a flexible structure to relieve lattice mis-match between the emitter and the base.

Abstract: According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further includes a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also includes a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further includes a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may include, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).

Abstract: An improved BJT is described that maximizes both Bvceo and Ft/Fmax for optimum performance. Scattering centers are introduced in the collector region (80) of the BJT to improve Bvceo. The inclusion of the scattering centers allows the width of the collector region WCD (90) to be reduced leading to an improvement in Ft/Fmax.

Abstract: A method including a buried layer formed on a semiconductor substrate, an active region formed adjacent to at least a portion of the buried layer, an isolation structure formed adjacent to at least a portion of the active region, and a gate oxide formed adjacent to at least a portion of the active region. The method also includes a polysilicon layer formed adjacent to at least a portion of the gate oxide having a portion removed to form a polysilicon definition structure that substantially surrounds and defines an emitter contact region. The method also includes forming a self-aligned implant region of the emitter contact region.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor might be a lateral PNP bipolar transistor and the base may comprise, for example, N type single crystal silicon. The bipolar transistor further comprises an emitter having a top surface, where the emitter is situated on the top surface of the base. The emitter may comprise P+ type single crystal silicon-germanium, for example. The bipolar transistor further comprises an electron barrier layer situated directly on the top surface of the emitter. The electron barrier layer will cause an increase in the gain, or beta, of the bipolar transistor. The electron barrier layer may be a dielectric such as, for example, silicon oxide. In another embodiment, a floating N+ region, instead of the electron barrier layer, is utilized to increase the gain of the bipolar transistor.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: A semiconductor device includes a p−-silicon substrate, n−-epitaxial growth layers on the p−-silicon substrate, a field insulating film at the surface of the n−-epitaxial growth layer, an npn transistor formed at the n−-epitaxial growth layer, an pnp transistor formed at the n−-epitaxial growth layer, a DMOS transistor on the n−-epitaxial growth layer, and a resistance. The DMOS transistor includes an n+-diffusion layer forming a source, a p-type diffusion layer forming a back gate region, a lightly doped n-type diffusion layer forming a drain, and a heavily doped n+-diffusion layer forming the drain.

Abstract: A first layer is formed on an underlying substrate having a surface layer made of semiconductor of a first conductivity type. The first layer is made of semiconductor having a resistance higher than that of the surface layer. A first impurity diffusion region of a second conductivity type is formed in a partial surface region of the first layer. The first impurity diffusion region does not reach the surface of the underlying substrate. A second impurity diffusion region of the first conductivity type is disposed in the first layer and spaced apart from the first impurity diffusion region. The second impurity diffusion region reaches the surface of the underlying substrate. A separation region is disposed between the first and second impurity diffusion regions. The separation region comprises a trench formed in the first layer and dielectric material disposed at least in a partial internal region of the trench.

Abstract: An IGBT structure includes successive regions whose conductivities have alternating signs. The structure is dimensioned for punch-through and is provided with two buffer layers. As a result, the component becomes symmetrically blocking and is suitable as a semiconductor switch, e.g., for converters.

Abstract: A lateral-current-flow integrated transistor, formed in an epitaxial layer defining a base well with a first conductivity type, which accommodates emitter and collector regions of a second conductivity type. The collector region is formed by an internal conductive region and by an external conductive region, and the emitter region is formed by an intermediate conductive region. The external conductive region has an annular shape and surrounds the intermediate conductive region, which also has an annular shape and surrounds the internal conductive region.

Abstract: The operating temperature range for a vertical PNP transistor can be extended by applying cancellation techniques. The vertical PNP generates a first leakage current from the base-collector region. Another vertical PNP transistor is configured to generate a second leakage current, which is coupled to a current-mirror circuit. The output of the current-mirror circuit is configured to provide a cancellation effect on the first leakage current. The current-mirror circuit and vertical PNP may be configured such that the first leakage current is cancelled in a judicious amount, whereby the effects of leakage current and flare-out in the vertical PNP transistor are minimized or cancelled. The cancellation technique is applicable to temperature sensor circuits, thermal voltage generators, and bandgap circuits.

Abstract: A bipolar transistor is provided in which the product of base-collector capacitance and collector resistance can be reduced through a layout optimization, which leads to an improvement of the critical transistor parameters. The bipolar transistor has an emitter formed from a plurality of emitter elements, a plurality of base contacts and a plurality of collector contacts, these elements being provided in a specific arrangement with respect to one another for the formation of the transistor layout. The invention provides for the emitter to have at least one closed emitter configuration, the at least one emitter configuration bounding at least one emitter inner space, which can in turn be divided into a plurality of partial spaces. At least one of the base contacts is arranged in the emitter inner space, while at least one other base contact and the collector contacts are arranged outside the emitter configuration.

Abstract: P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter due to early punch-through. This problem has been overcome by preceding the epitaxial deposition of N− silicon onto the P− substrate with an additional process step in which a buried N+ layer is formed at the surface of the substrate by ion implantation. This N+ buried layer significantly reduces the width of the depletion layer that extends outwards from the P− well when voltage is applied to the drain thus substantially raising the punch-through voltage.

Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.

Abstract: A dual polysilicon emitter, complementary output is provided which utilizes a buried power buss. While providing these advantages, the process is not complicated. The process has the speed performance of the ASSET technology with an easier process to produce. In addition, the process described in the present invention provides additional advantages that the ASSET process does not have.

Abstract: In an element formation region, a surface of an N− epitaxial layer is inclined upward from an end of a field oxide film to a sidewall of an opening. An external base diffusion layer at the surface of the N− epitaxial layer is inclined upward from a side of the field oxide film to the sidewall of the opening, and is exposed at the sidewall of the opening. A portion of the sidewall of the opening exposing the external base diffusion layer is tapered. The depth of a lower end of the external base diffusion layer or the sidewall of the opening is substantially equal to or smaller than that of a bottom of the opening. A decrease in breakdown voltage between an emitter and a base is suppressed, and decrease and variation of current gain hFE is suppressed.

Abstract: An integrated circuit that includes a high breakdown voltage bipolar transistor. The bipolar transistor includes an emitter 36, a base 32, and a collector structure. The emitter 36 is adjacent to and overlies the base 32 and the base 32 is adjacent to and overlies a core portion 48 of the collector structure. The collector structure includes, in addition to the core portion 48, a collector contact region 31 and a lateral collector region 50 between the core portion 48 and the collector contact region 31. The lateral collector region 50 is thinner than said collector contact region at some point along its length.

Abstract: Transistor, is disclosed, including a base having a bundle of (n,n) nanotubes, and an emitter and a collector connected to opposite sides of the base each having (n,m, n−m≠3 l) nanotubes, whereby substantially reducing a device size and improving an operation speed as the carbon nanotube has a thermal conductivity much better than silicon.

Abstract: Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed dielectric material ultimately determines the depth of the trench and hence the degree of isolation provided by the surrounding dielectric material. The shape and facility of etching of the trench may be determined through the use of etch-stop layers and unmasked photoresist regions of differing widths. Once the trench in the dielectric material is formed, the trench is filled with selectively and/or nonselectively grown epitaxial silicon. The process avoids complex and defect-prone deep trench masking, deep trench silicon etching, deep trench liner formation, and dielectric reflow steps associated with conventional processes.

Abstract: A method for adjusting the gain or the sensitivity of a lateral component formed in the front surface of a semiconductor wafer, having a first conductivity type, includes not doping or overdoping, according to the first conductivity type, the back surface when it is desired to reduce the gain or sensitivity of the lateral component, and doping according to the second conductivity type, the back surface, when the gain or the sensitivity of the lateral component is to be increased.

Abstract: The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure. The device includes a semiconductor substrate doped with impurities of the P type; a first buried layer doped with impurities of the N type to form a base region; and a second layer, overlying the first and having conductivity of the N type, to form an active area with opposite collector and emitter regions being formed in said active area and separated by a base channel region. The width of the base channel region is defined essentially by a contact opening formed above an oxide layer deposited over the base channel region. Advantageously, the contact opening is formed by shifting an emitter mask.

Abstract: A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills th

Abstract: A lateral semiconductor device includes an n-type buffer layer (15) selectively formed in the surface of an n-type base layer (14), a p-type drain layer (16) selectively formed in the surface of the n-type buffer layer (15), a p-type base layer (17) formed in the surface of the n-type base layer (14) so as to surround the n-type buffer layer (15), an n+-type source layer (18) selectively formed in the surface of the p-type base layer (17), a source electrode (24) in contact with the p-type base layer (17) and the n+-type source layer (18), a drain electrode (22) in contact with the p-type drain layer (16), and a gate electrode (20) formed via a gate insulating film (19) on the surface of the p-type base layer (17) sandwiched between the n+-type source layer (18) and the n-type base layer (14). The p-type drain layer (16) has an annular structure or horseshoe-shaped structure, or is divided into a plurality of portions. This realizes a high breakdown voltage with a low ON voltage.

Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.

Abstract: An n+ type emitter region and a p-type base region are formed in contact with one main surface of an n-type collector region, a p-type cathode region is formed in a ring shape in contact with the main surface so as to enclose the emitter region and the base region, the potential at the cathode region is sustained at a level equal to the potential at the emitter region and a p-type guard ring region is formed in a ring shape so as to enclose the cathode region. This structure prevents the base drive circuit from becoming damaged by an avalanche breakdown current.

Abstract: An npn transistor allowing the potential of each terminal to be easily set and superior in characteristics such as withstand-voltage performance and current amplification factor can be obtained. An n-type buried layer on a p-type substrate, a p-type buried layer on the n-type buried layer, n-type epitaxial layers covering the above layers, terminal regions on the surfaces of the layers, p-type outer-periphery layers encircling the terminal regions, and an encirclement layer encircling the layers are included, and p-type base regions and the p-type outer-periphery layer are continued to the p-type buried layer to separate a collector region from a p-type substrate and the n-type buried layer and the n-type encirclement layer are continued to separate the p-type buried layer, the p-type base region, and the p-type outer-periphery layer from the p-type substrate.

Abstract: An insulated gate transistor comprising a first semiconductor region, a second semiconductor region includes plural portions, a third semiconductor region, a fourth semiconductor region, a first insulation layer, control electrodes, a first main electrode, and a second main electrode, wherein a metallic wiring layer is provided on the first main surface plane via an insulating layer, plural regions insulated from the first main electrode are provided through said first main electrode, and the metallic wiring layer is connected electrically to the control electrode through the insulating layer via the region insulated from the main electrode.

Abstract: In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film in an SOI substrate with an electrically conductive film is utilized for an emitter and/or a collector, whereby a bipolar transistor is formed through a simple process.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: Each of an emitter (E), a first collector (CH) and a second collector (CL) is formed from a first conductivity-type area. A breakdown voltage between the first collector (CH) and the base (B) is greater than a breakdown voltage between the second collector (CL) and the base (B). The base (B) is formed from a second conductivity-type area. A positive electrode of a direct-current power source is connected to the first collector (CH) through a load, a negative electrode thereof is connected to the emitter (E), and a control voltage is applied to the base (B). At this time, if the control voltage is equal to or greater than a value determined based on a current flowing between the second collector (CL) and the base (B), a current flows to the load.

Abstract: A lateral heterojunction bipolar transistor comprises a first semiconductor layer in a mesa configuration disposed on an insulating layer, a second semiconductor layer formed by epitaxial growth on the side surfaces of the first semiconductor layer and having a band gap different from that of the first semiconductor layer, and a third semiconductor layer formed by epitaxial growth on the side surfaces of the second semiconductor layer and having a band gap different from that of the second semiconductor layer. The first semiconductor layer serves as a collector of a first conductivity type. At least a part of the second semiconductor layer serves as an internal base layer of a second conductivity type. At least a part of the third semiconductor layer serves as an emitter operating region of the first conductivity type. The diffusion of an impurity is suppressed in the internal base formed by epitaxial growth.

Abstract: A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP also includes a base region of a second conductivity type formed by a graded channel implant and a well region of a second conductivity type, the well region contacting the base region, the buried region and a base contact. Additionally, there are collector contacts and emitter contacts of a first conductivity type. The lightly doped collector region results in a large Early voltage and the base region provides for a high current gain.

Abstract: A PNPN semiconductor switching device for igniter circuits comprises first and third diffusion layers of N-type conductivity semiconductor material, second and fourth diffusion layers of P-type conductivity type semiconductor material, and a first buried region of N-type conductivity in the third layer adjacent to the junction between the second and third layers. The buried region has a greater impurity concentration than the third layer and serves to control the switching voltage of the device The first to third diffusion layers form an NPN transistor and a resistance is formed as part of the transistor base diffusion between the base and emitter diffusion regions of the transistor for controlling the switching current of the device.

Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Abstract: A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection efficiency while the collector region (120) has a lightly doped region for reduced base depletion.

Abstract: Transistor, is disclosed, including a base having a bundle of (n,n) nanotubes, and an emitter and a collector connected to opposite sides of the base each having (n,m, n−m≠3l) nanotubes, whereby substantially reducing a device size and improving an operation speed as the carbon nanotube has a thermal conductivity much better than silicon.

Abstract: A lateral semiconductor device includes an n-type buffer layer (15) selectively formed in the surface of an n-type base layer (14), a p-type drain layer (16) selectively formed in the surface of the n-type buffer layer (15), a p-type base layer (17) formed in the surface of the n-type base layer (14) so as to surround the n-type buffer layer (15), an n+-type source layer (18) selectively formed in the surface of the p-type base layer (17), a source electrode (24) in contact with the p-type base layer (17) and the n+-type source layer (18), a drain electrode (22) in contact with the p-type drain layer (16), and a gate electrode (20) formed via a gate insulating film (19) on the surface of the p-type base layer (17) sandwiched between the n+-type source layer (18) and the n-type base layer (14). The p-type drain layer (16) has an annular structure or horseshoe-shaped structure, or is divided into a plurality of portions. This realizes a high breakdown voltage with a low ON voltage.

Abstract: The invention relates to a semiconductor device comprising a semiconductor body (10) including, for example, a p-type substrate (11) and a PNP bipolar transistor having a collector (1), a base (2) and an emitter (3), which are each provided with a connection conductor (7, 8, 9). One or more of the connection conductors (7, 8, 9) extend over a part of an insulating layer (20) which covers the body (10) which contains, below said insulating layer (20), a further semiconductor region (4) of a conductivity type opposite to that of the substrate (11). A disadvantage of the known device is that it is less suitable for certain applications, such as power amplification. In a device according to the invention, a sub-region (4b) of the further semiconductor region which borders on the substrate (11) is provided with a higher doping concentration than the remainder (4a) of the further semiconductor region (4).

Abstract: A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped with emitter metal forming the resistor contacts. The emitter mesas are layered on top of the current channel that is layered atop of a base layer. The voltage variable resistor's control contact is provided by a base contact located on the base layer and separated from the current channel.

Abstract: In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Abstract: An object of the present invention is to provide a lateral bipolar transistor having a high current driving capacity and a high current amplification factor as well as a high cut-off frequency. A device area 13 surrounded by an isolating insulation layer is formed on the surface of a semiconductor substrate 11. A base area 15 is formed in the device area 13 to a specified depth from the surface of the semiconductor substrate 11. A core insulation layer 25 is formed in the base area 15 with a depth shallower than the base area 15 from the surface of the semiconductor substrate 11. Around the core insulation layer 25, there are formed emitter areas 26. A collector area 17 is formed at a specified distance from the emitter area 26. Since the bottom area of the emitter area 26 is reduced by being provided with the core insulation layer 25 without reducing the side area of the emitter area 26, the current driving capacity and the current amplification factor of the transistor are thus improved.

Abstract: Formed on the surface of an n-type semiconductor layer (21) taken as a collector region is a base region (22) consisting of a p-type region, and formed in the p-type region is an emitter region (23) consisting of an n+-type region. Further, provided in the base region is a base electrode connecting portion (24) consisting of an n+-type region, and a base electrode (26) is connected to the surface of the base electrode connecting portion, and an emitter electrode (27) and a collector electrode (28) are provided and connected electrically to the emitter region and the collector region (21), respectively. As a result, a semiconductor device is obtained which has the transistor in which the reduction in power consumption with a high withstand voltage can be achieved, and the fast switching speed is possible and the large current is obtained. Further a voltage-drive type bipolar transistor such as a digital transistor is obtained which is small in load capacity while establishing a desired drive voltage.

Abstract: SEMICONDUCTOR DEVICE AND PROCESS OF PRODUCTION OF SAME A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

Abstract: A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.