Abstract: A high-frequency switch includes a semiconductor body made of a semiconductor material having a first surface and a second surface, and two direct current terminals and two high-frequency terminals.

Abstract: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: A semiconductor power device includes a semiconductor body with a plurality of gate trenches formed therein. Disposed within each gate trench is a spacer gate that extends along at least a portion of the sidewalls of the gate trench but not along at least a portion of the bottom surface of the trench. The spacer gate of each gate trench may also include a layer of silicide along outer surfaces thereof. The semiconductor body may include a channel region and each gate trench may extend through the channel region and into the semiconductor body. Formed at the bottom of each gate trench within the semiconductor body may be a tip implant of the same conductivity as the semiconductor body. In addition, a deep body implant of the same conductivity as the channel region may be formed at the base of the channel region.

Abstract: A semiconductor device according to an embodiment of the present invention includes a plurality of chip regions and a plurality of chip rings. The plurality of chip regions include semiconductor integrated circuits each having a multilayered wiring structure using a metal wiring, and are formed into independent chips. The plurality of chip rings has the multilayered wiring structure using the metal wiring, and surround the respective chip regions. The plurality of chip rings are electrically connected to one another.

Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type conductive layer formed at side surfaces of the second interconnection, and an intrinsic layer formed between the first and second conductive-type conductive layers thereby forming a P-I-N structure.

Abstract: A method and apparatus are provided for protecting a semiconductor device from damage. The method includes the steps of providing a active semiconductor device on a surface of the semiconductor substrate where the active device is surrounded by inactive semiconductor areas and providing a soft metallic guard ring only in the inactive semiconductor areas around the periphery of the active device wherein the metallic guard ring is connected to ground potential and not to the active device.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.

Abstract: A method of manufacturing a thin-film circuit substrate, containing: (a) gouging a surface of a circuit substrate in a depth at least approximately equal to a thickness of a final product of the substrate, to form a section to be formed a penetrating section; (b) providing a protecting adhesive tape to adhere to the gouged surface of the substrate, before a backing surface of the substrate is ground; (c) grinding the backing surface in such a thickness that the gouged section would not penetrate; (d) dry etching entirely the backing surface, while the tape adheres to the substrate, after completion of the grinding for the backing surface; and (e) making the gouged section of the substrate to penetrate, by the dry etching, thereby forming the penetrating structure section; and, a protecting adhesive tape usable in the method.

Abstract: A structure in a phase changeable memory cell can include a bottom electrode having an interlayer dielectric layer thereon, the bottom electrode can have a recess therein that extends beyond a boundary between the bottom electrode and the interlayer dielectric. A phase changeable layer can be formed in the recess and include a protruding potion of the phase changeable layer that protrudes into the bottom electrode beyond the boundary. Related methods are also disclosed.

Abstract: An apparatus and method providing flexibility to a silicon chip carrier which, in at least one embodiment, comprises multiple chips and a silicon chip carrier having thinned regions between some adjacent chips, thus, allowing for increased flexibility and reduced package warpage.

Abstract: An array-type modularized light-emitting diode structure and a method for packaging the structure. The array-type modularized light-emitting diode structure includes a lower substrate and an upper substrate fixed on the lower substrate. A material with high heat conductivity is selected as the material of the upper substrate. The upper substrate is formed with multiple arrayed dents and through holes on the bottom of each dent. A material with high heat conductivity is selected as the material of the lower substrate. The surface of the lower substrate is formed with a predetermined circuit layout card. The bottom face of the upper substrate is placed on the upper face of the lower substrate with the through holes of the dents respectively corresponding to the contact electrodes of the circuit layout card of the lower substrate. Multiple light-emitting diode crystallites are respectively fixed on the bottoms of the dents.

Abstract: A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to from word lines that intersect the active area lines at the angled segments.

Abstract: A semiconductor device includes a first transistor having a first gate oxide layer with a first thickness; a second transistor having a second gate oxide layer with a second thickness different from the first thickness; and at least one of a capacitor and a variable capacitance diode. One of the capacitor and the variable capacitance diode includes a first electrode having a first area and a second area; a second electrode formed in the first area with the first gate oxide layer in between; and a third electrode formed in the second area with the second gate oxide layer in between. The second electrode and third electrode have comb shapes nested inside one another.

Abstract: The subject invention provides systems and methodologies for fabrication of memory and/or selection (e.g., diodes) elements in a recession in a semiconductor layer. In particular, a trench of varying width is created in the semiconductor layer by employing various etching techniques. A metal film can be deposited in the trench according to a desired deposition thickness in order to seam close a narrow portion of the trench while form a dimple in a wide portion of the trench. The trench, after metal film deposition, exhibits a depression in wider trench portions relative to narrow trench portions. The depression can be utilized by placing one or more memory or selection layers in the depression, and a via can be formed over a portion of the trench to form an interconnect.

Abstract: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

Abstract: In accordance with an embodiment of the invention, a Schottky diode includes a metal layer in contact with a semiconductor region to form a Schottky barrier therebetween. A first trench extends in the semiconductor region. The first trench includes at least one electrode or diode therein.

Abstract: A trench schottky diode which includes a thin insulation layer on the sidewalls of its trenches and a relatively thicker insulation layer at the bottoms of its trenches.

Abstract: A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.

Abstract: A semiconductor diode structure is provided which includes a substrate; a fin formed of a semiconducting material positioned vertically on the substrate, the fin includes a first heavily-doped region of a first doping type on one side and a second heavily-doped region of a second doping type on an opposite side; and a first conductor contacting the first heavily-doped region and a second conductor contacting the second heavily-doped region.

Abstract: A light source suitable for surface mounting onto a printed circuit board. The light source includes a planar substrate with a centrally positioned recess. A light emitting diode is mounted in the recess and the substrate is encapsulated by a transparent encapsulant material forming an ellipsoidal dome over the light emitting diode.

Abstract: The present invention has an object to provide a photoreceptor array with an excellent device property and no short fault between adjacent photoreceptors and to provide a method of manufacturing such the photoreceptor array with a high yield. On a transparent substrate (31), a transparent electrode (32) and a p-type amorphous silicon layer (33) are formed. An insulating layer (41) is deposited thereon to form a trench (42). In the trench (42), an i-type amorphous silicon layer (34), an n-type amorphous silicon layer (35) and an n-side electrode (36) are buried in turn to form the photoreceptor array.

Abstract: The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region.

Abstract: A semiconductor device includes a plurality of barrier layers and a plurality of quantum well layers which are alternately interleaved with each other and disposed on a substrate of semiconductor material so as to form a multiple-heterojunction varactor diode. The barrier layers and quantum well layers are doped with impurities. The varactor diode includes an ohmic contact which is electrically connected to a heavily doped embedded region and a Schottky contact which is electrically connected to a depletion region of the diode. The ohmic contact and the Schottky contact enable an external voltage source to be applied to the contacts so as to provide a bias voltage to the varactor diode. A variable capacitance is produced as a result of the depletion region varying with a variation in the bias voltage. The varactor diode also provides a constant series resistance.

Abstract: The invention relates to an integrated chip diode manufactured by forming two different typed semiconductors on the top and bottom of a wafer respectively and forming a plurality of diodes thereon, each diode comprises glass insulator encapsulated on sides thereof, two conductive metal layers formed on the surfaces of the semiconductors respectively, an insulation material coated on a portion of the surface of one conductive metal layer and a third conductive metal layer sintered on the glass insulator, such that the other conductive metal layer can be electrically connected to the insulation material on the one conductive metal layer via the third conductive metal layer. Thus, two independent soldered conductive terminals are formed at the same sides of the diodes and electrically connected to each of different typed semiconductors.

Abstract: A semiconductor arrangement and a method for manufacturing the semiconductor arrangement are provided, which arrangement and method allow an improvement in the current-carrying capacity for given chip dimensions. The semiconductor arrangement includes trenches introduced in the interior of the chip, which trenches reduce power loss and improve the heat dissipation of the chip, as well as reduce the forward voltage of diode.

Abstract: A surface PIN (SPIN) device and a method of fabricating such a SPIN device. The SPIN device, when activated, confines carrier injection to a small volume near the surface of the device such that the device is sufficiently conductive to simulate a planar conductor. The SPIN device comprises a P+ region and an N+ region formed in an intrinsic (I) layer. The P+ and N+ regions are separated by a lateral length of intrinsic material of length L. The length L is approximately the carrier diffusion length. When DC bias is applied across the N+ and P+ regions carriers are injected into the intrinsic region at a density exceeding 1018 carriers per cubic cm. The intrinsic region is sufficiently thin to confine the carriers near the surface of the intrinsic region. As such, in the “on” state, the SPIN device simulates a conductive material. In the “off” state, the SPIN device is no longer conductive.

Abstract: A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plurality of first and second orthogonal electrodes with cross points. A plurality of semiconductor layers are disposed between the first and second electrodes to form a plurality of diodes between the cross points of the first and second electrodes. A passivation layer is disposed between the first electrodes and the diodes to form a plurality of anti-fuses adjacent to the diodes at the cross points of first and second electrodes. Portions of the diode layers are removed between the electrode cross points to form the plurality of memory cells with rows of trenches between adjacent memory cells to provide a barrier against crosstalk between adjacent memory cells. The trenches extend substantially to the depth of the n-doped layer in each diode.

Abstract: Semiconductor diodes are diode connected vertical cylindrical field effect devices having one diode terminal as the common connection between a gate and a source/drain of the vertical cylindrical field effect devices. Methods of forming the diode connected vertical cylindrical field effect devices are disclosed.

Abstract: Semiconductor diodes are diode connected cylindrical junction field effect devices having one diode terminal as the common connection between a top gate, a back gate and a first channel terminal of the cylindrical junction field effect devices. The second diode terminal of the semiconductor diodes being the second channel terminal of the diode connected cylindrical junction field effect devices. The method of processing the cylindrical junction field effect devices provide very short channels, shallow diffused regions and trench terminated junctions at the edges of the active device for low forward voltage turn-on and high reverse bias breakdown. The trench terminated junctions spread the breakdown energy over the entire active device region rather than just device edges.

Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

Abstract: Methods and apparatus of forming a semiconductor device using pedestals and sidewalls. The pedestals and sidewalls may provide an etch stop and/or a diffusion barrier during manufacture of a semiconductor device. Processes of forming diode connected vertical cylindrical field effect devices are disclosed to exemplify the use of the pedestals and/or sidewalls. A system for forming the pedestals and sidewalls is described.

Abstract: The invention relates to a semiconductor device with a diode. The semiconductor body (10) comprises a stack of a first semiconductor region provided with a first connection conductor (5) and a second semiconductor region (2) connected to a second connection conductor (6), wherein a rectifying junction is present between the two semiconductor regions (1, 2) having opposite conductivity types. Such a device is—after a rotation through 90 degrees—suitable for surface mounting. However, in particular at high voltage and/or high power levels, the diode may suffer from breakdown or a high leakage current.

Abstract: Component having a blocking pn junction having an edge termination structure which is formed by a further, more weakly doped region (5) and a trench (8) formed therein, said trench being filled with a dielectric. The dielectric material in the trench (8) diverts the equipotential areas from the horizontal in a very confined space in the vertical direction, with the result that the electric field can emerge from the component within a small region of the chip surface.

Abstract: A semiconductor device (102) having a plurality of diodes (100) with alterable electrical conductivity by a source of energy (30), e.g., a laser, external to the semiconductor device. The diodes are formed and energy is applied to alter the electrical conductivity at least 10%, and preferably by several orders of magnitude. Certain embodiments (20, 40 and 50) are formed so as to function as anti-fuses, while another embodiment (60) functions as a fuse. The diodes may be formed as planar diodes (20, 40, 50 and 60) or as lateral diodes (70).

Abstract: The present invention relates to a pinned photodiode used in a CMOS image sensor. The pinned photodiode according to the present invention has an uneven surface for increasing an area of a PN junction of the photodiode. So, the increased PN junction area improves a light sensitivity of the photodiode. That is, the epitaxial layer, in which the photodiode is formed, has a trench or a protrusion. Also, in the pinned photodiode, since the P0 diffusion layer is directly in contact with the P-epi layer, the two P-type layers have the same potential and then it may operate in a low voltage.

Abstract: A low noise, high frequency solid state diode is provided from a plurality of unit diode cells which are interconnected in parallel. Each of the unit diode cells forms an element of an array having rows and columns of unit diode cells. The diode cells include a base region of polysilicon, forming an anode, and an active cathode region which forms a diode junction with the anode. A plurality of overlapping subcollector regions interconnect the cathode regions, to provide a single, continuous collector for the diode arrays. The base region has a minimum perimeter to area ratio which reduces the resistance of each active diode region. A plurality of cathode contacts are connected to the subcollector through a respective reach region of highly doped semiconductor material. One or more metalization layers connect the cathode regions together, and the anodes of the base regions together. By controlling the size and shape of the base region of polysilicon, the series resistance of the resulting diode is minimized.

Abstract: A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.

Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

Abstract: The invention provides an organic EL display device comprising a plurality of organic EL elements each having at least a first electrode, one or more organic layers participating in light emission capability, and a second electrode, the elements being able to be independently electrically operated to emit light, and a groove structure at the boundary between adjacent organic EL elements for isolating at least one of the electrodes between the adjacent organic EL elements. The organic EL display device featuring a greater proportion of light emitting region, higher reliability, a large size of substrate, a more number of elements arrayed in one substrate, and a reduced cost of manufacture is obtained as well as a method for the manufacture thereof.

Abstract: A diode is formed by forming a PN junction region 6 with a p region 5 formed on a buried oxide film 19 side and an n region 7 formed on the surface side in a surface silicon layer 3 which is isolated by the buried oxide film 19 of an SOI substrate 1, providing a lightly doped p region 33 on one end side of the PN junction region 6 and a lightly doped n region 31 on an other end side, forming a heavily doped p region 13 and a heavily doped n region 9 at the respective surface portions of the lightly doped p region 33 and the lightly doped n region 31 in such a manner as not to contact the PN junction region 6, and providing two metal plates which respectively connect to the heavily doped p region 13 and the heavily doped n region 9.

Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.

Abstract: In an SOI substrate, an active zone is completely surrounded by a trench filled with insulating material. Disposed adjacent to the trench is a first doped zone which is formed, in particular, by out-diffusion from a doped layer disposed on the wall of the trench. The first doped zone and a second doped zone form a p-n junction of a photodiode.

Abstract: A wafer layout for a multi-channel device for improving the yield of operative devices comprises a semiconductor wafer and a plurality of semiconductor devices formed in the semiconductor wafer, each device comprising a consecutive series of impurity regions formed in the semiconductor wafer, the impurity regions being arranged consecutively without separation between the respective semiconductor devices, such that each of the semiconductor devices is indistinguishable from the others, without regard to defective devices, and a single semiconductor device comprising a plurality of consecutive impurity regions formed in the semiconductor wafer may be cut from the wafer by cutting therefrom any of the plurality of consecutive impurity regions formed therein. The invention is particularly useful for the fabrication of strip diodes and the like.

Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

Abstract: The present invention discloses two kinds of ESD protection devices, an MOS transistor and an diode, and their method of fabrication. The MOS transistor is fabricated in a semiconductor substrate having a plurality of trenches formed therein at one side of its gate. One of the source/drain regions of the MOS transistor is formed in the substrate and disposed along the periphery of those trenches. The diode is fabricated in a semiconductor substrate having a plurality of trenches formed therein. A dope region is thereafter formed in the substrate and disposed along the periphery of those trenches. Accordingly, either the MOS transistor or diode has a vertically enlarged area along the trenches to effectively prevent ESD damage, but without consuming a great amount of horizontal chip area.

Abstract: A power diode includes at least one semiconductor body having an inner zone f a first conductivity type and a given doping level, a cathode zone of the first conductivity type and a doping level higher than the given doping level, and an anode zone of a second conductivity type opposite the first conductivity type and a doping level higher than the given doping level. The inner zone has at least a first region with a first predetermined thickness being dimensioned for a required blocking voltage and a second region with a second thickness being greater than the first predetermined thickness by at least a factor of 1.4. The area and/or the minority carrier life of first and second partial diodes is dimensioned for causing a current flowing through the first partial diode in a conductive phase to be greater than a current flowing through the second partial diode by at least a factor of 2.

Abstract: An array of light-emitting diodes each having a junction between a region of a first conductivity type and a region of a second conductivity type. The array fabrication process offers the elimination of wafer breakage is eliminated and an array with stable optical output power.