Avalanche Diode (e.g., So-called "zener" Diode Having Breakdown Voltage Greater Than 6 Volts) Patents (Class 257/603)
  • Patent number: 6191466
    Abstract: A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: February 20, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasunori Yamashita, Tomohide Terashima, Fumitoshi Yamamoto
  • Patent number: 6107673
    Abstract: The present invention relates to a high voltage diode which has a fast turn-off, formed of a series connection of several diodes, the relative intrinsic dispersion of recovered charges between the diodes being smaller than 5%.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: August 22, 2000
    Assignee: STMicroelectronics S.A.
    Inventor: Bertrand Rivet
  • Patent number: 6075276
    Abstract: A semiconductor device is provided which includes a first conductivity type semiconductor substrate, a second conductivity type Zener region formed in a surface layer of the first conductivity type semiconductor substrate, a first conductivity type anode region formed within the second conductivity type Zener region, an anode electrode which is formed in contact with both of the semiconductor substrate and first conductivity type anode region and is grounded, and a cathode electrode formed on a surface of the second conductivity type Zener region and connected to input and output terminals. A diode that consists of the first conductivity type semiconductor substrate and the second conductivity type Zener region and a diode that consists of the first conductivity type anode region and the second conductivity type Zener region serve as protective elements for preventing electrostatic breakdown of the semiconductor device.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: June 13, 2000
    Assignee: Fuji Electric Company, Ltd.
    Inventor: Akio Kitamura
  • Patent number: 6060763
    Abstract: A semiconductor device has formed onto the surface of a collector region 12 of a semiconductor substrate 11 of one conductivity type with a base region 13 of a different conductivity type, an emitter region 16 of the one conductivity type formed on a surface within the base region 13, and a base electrode 18 and emitter electrode 17 which are formed by opening windows in the base and emitter regions 13, 16.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: May 9, 2000
    Assignee: NEC Corporation
    Inventors: Kazuo Yamagishi, Akihiro Shimomura, Hirohiko Uno
  • Patent number: 6054716
    Abstract: A semiconductor light emitting device incorporates therein with (a) a light emitting portion formed by semiconductor overlying layers including a first conductivity layer and a second conductivity layer in order to a light emitting layer, and (b) a protecting element portion provided in electrical connection between said first conductivity type layer and said second conductivity type layer so that said light emitting portion is protected against at least a reverse voltage applied to said light emitting portion. The light emitting portion and the protecting element portion can be formed by separate chips or in one chip having the both. They are formed into a lamp-type or chip-type light emitting device. The incorporation of the protecting element increase the reverse-voltage resistance for a compound semiconductor, such as galium-itride or the like, that is less resistive to reverse voltages applied.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: April 25, 2000
    Assignee: Rohm Co., Ltd.
    Inventors: Masayuki Sonobe, Tsuyoshi Tsutsui, Shunji Nakata, Norikazu Itoh, Shinji Isokawa, Hidekazu Toda
  • Patent number: 6049109
    Abstract: A power semiconductor device according to the present invention has an SOI substrate formed of a buried silicon oxide film having an uneven surface portion on the surface thereof and an n-type silicon active layer of low impurity concentration formed on the buried silicon oxide film. An n-type emitter layer and a p-type emitter layer are selectively formed in the surface area of the n-type silicon active layer. A cathode electrode and an anode electrode are respectively formed on the n-type emitter layer and p-type emitter layer. With the above structure, a power semiconductor device of high withstand voltage can be realized.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: April 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Akio Nakagawa
  • Patent number: 6002144
    Abstract: A semiconductor device having a zener diode, wherein an anode electrode and a cathode electrode of the zener diode have a barrier metal layer as an underlying layer, i.e., a barrier metal structure to simplify manufacturing steps of the semiconductor device, while ensuring that the zener diode is short-circuited with a low resistance without variations in resistance. The anode electrode (6) and the cathode electrode (8) are formed with an underlying metal layer made of a barrier metal. The anode electrode and the cathode electrode are shaped such that Xa<La and Xc<Lc are satisfied, where Xa and Xc are the widths of opposite sides of contact portions of the anode electrode and the cathode electrode, at which they are connected to an anode region and a cathode region, respectively, and La and Lc are the lengths of the respective contact portions.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: December 14, 1999
    Assignee: Sony Corporation
    Inventor: Tetsuya Oishi
  • Patent number: 5986327
    Abstract: A base region is formed at a shallow junction and an impurity region of higher impurity concentration is formed, by a separate step, as a buried layer at a predetermined distance from the surface of a semiconductor substrate. By so doing, a bipolar diode is implemented which does not involve an increase in a base resistance even if conduction is effected over a longer period of time.
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: November 16, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Mishio, Satoshi Takahashi, Shigeru Komatsu
  • Patent number: 5977611
    Abstract: A Read diode includes an inner zone, a cathode zone, an anode zone and a first coupling zone disposed between the inner zone and the anode zone. A second coupling zone is disposed between the first coupling zone and the inner zone. Both coupling zones are used in the reverse mode for dividing an electric field into a high-field zone and a low-field zone and, consequently, permit greatly localized charge carrier generation by impact ionization in the voltage breakdown. The use of the two coupling zones ensures "punch-through" coupling between the high-field and low-field zones which, in contrast to the space charge coupling of Read diodes, permits a largely temperature-independent "soft-recovery" behavior. Hybrid diodes having optimized forward and commutation behaviors can be produced from the FCI-PT diodes. FCI-PT diodes are preferably employed in conjunction with switching power semiconductor components as voltage limiters or freewheeling diodes.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: November 2, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Roland Sittig, Karim-Thomas Taghizadeh-Kaschani
  • Patent number: 5959345
    Abstract: A semiconductor power device (100) that includes a number of bipolar or FET power devices (116), an over-voltage clamp (118), and an edge termination structure (110) that separates the power devices (116) and the over-voltage clamp (118). The power devices (116) are formed in an interior region (100a) of a semiconductor substrate (128), while the over-voltage clamp (118) is formed in a peripheral region (100b) of the substrate. The over-voltage clamp (118) and the gate/base terminals of the power devices (116) are formed in a polysilicon layer (126) overlying the substrate (128), such that the over-voltage clamp (118) is connected between the anode and gate/base terminals of each power device (116) to provide over-voltage protection.
    Type: Grant
    Filed: November 28, 1997
    Date of Patent: September 28, 1999
    Assignee: Delco Electronics Corporation
    Inventors: John Rothgeb Fruth, Stephen Paul Barlow, Donald Ray Disney
  • Patent number: 5955766
    Abstract: A zapping diode concerned with a P-N junction diode provided in an integrated circuit, whose P-N junction is subjected to breakdown by an overvoltage to perform fine adjustment in the value of capacitance or resistance involved in the circuit. The diode has a first impurity region of a first conductivity type formed in a first conductivity type semiconductor region, a second impurity region, an interlayer insulation film formed over the semiconductor region, and a third conductor film formed on the semiconductor region between the first and second impurity region. The third conductor film, when applied by a reverse-bias voltage, controls the direction of breakdown in the P-N junction to thereby provide a consistent value of residual resistance.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: September 21, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Ibi, Katsu Honna
  • Patent number: 5945691
    Abstract: In order to inhibit destruction during a turn-off state, a cathode electrode (6) is not connected to the overall major surface of a semiconductor substrate (10), but selectively connected to a region which is substantially opposed to an anode electrode (5). When a forward voltage is applied, therefore, an electric field which is generated in the semiconductor substrate (10) is distributed substantially only in a region immediately under a P-type diffusion layer (2), to hardly spread into a peripheral region positioned outside the region. Consequently, carriers which are injected from the P-type diffusion layer (2) and an N.sup.+ layer (4) into an N.sup.- layer (1) hardly spread to the peripheral region, but are stored substantially only in the region immediately under the P-type diffusion layer (2). Thus, concentration of a reverse current is relieved during a turn-off state in a peripheral edge portion of the P-type diffusion layer (2).
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: August 31, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshifumi Tomomatsu, Mitsuyoshi Takeda, Noriyuki Soejima
  • Patent number: 5939767
    Abstract: According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: August 17, 1999
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey S. Brown, Steven J. Holmes, Robert K. Leidy, Steven H. Voldman
  • Patent number: 5917227
    Abstract: A light-emitting-diode array includes a non-doped compound semiconductor layer between a substrate and a first compound semiconductor layer. A plurality of isolation regions extend from the first compound semiconductor layer to the surface of the non-doped compound semiconductor layer, and provide separation into isolated block regions each containing an equal number of diffusion regions. A plurality of shared electrode lines are connected to the diffusion regions in a plurality of the block regions, in such a relationship that diffusion regions selected from each of the block regions are connected to a common shared electrode. At least a surface portion of the substrate is formed of silicon. The density of the diffusion regions can be increased without increasing the number of the electrode pads. Moreover, the substrate is free from breakage or cracks.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: June 29, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Mitsuhiko Ogihara, Yukio Nakamura, Masumi Taninaka, Hiroshi Hamano
  • Patent number: 5869882
    Abstract: A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity type having an opposite conductivity type first tank disposed therein. The first tank includes relatively lower and relatively higher resistivity portions, the relatively lower doped portion isolating the relatively higher doped portion from the substrate. A first region of first conductivity type is disposed in the higher doped portion and a second region of opposite conductivity type and more highly doped than the first tank is spaced from the first region.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: February 9, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Wayne T. Chen, Ross E. Teggatz, Taylor R. Efland
  • Patent number: 5859446
    Abstract: In a diode, the backward length L of an anode electrode in a region, where a semiconductor layer of a p.sup.+ conductivity type and an anode electrode do not contact each other, is made longer than the diffusion length of holes in a semiconductor layer of an n.sup.- conductivity type for obtaining a large critical di/dt.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: January 12, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Nagasu, Mutsuhiro Mori, Hideo Kobayashi, Junichi Sakano
  • Patent number: 5834823
    Abstract: A power transistor incorporating a constant-voltage diode maintains the breakdown voltage of the constant-voltage diode at a specified level and prevents local breakdown of an insulating film located between an A1 field plate electrode and a base region of the transistor by spacing the A1 field plate electrode located on a collector region by a distance "d" from the base region.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: November 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Ziro Honda
  • Patent number: 5751054
    Abstract: A semiconductor structure which includes zener diodes and various combinations of MOS transistors, bipolar transistors and DMOS transistors, all fabricated on the same integrated circuit chip
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: May 12, 1998
    Assignee: Siliconix incorporated
    Inventors: Hamza Yilmaz, Richard K. Williams, Michael E. Cornell, Jun Wei Chen
  • Patent number: 5751052
    Abstract: An inductive driver circuit (10) has a driver transistor (11) that is used for driving loads. An input protection device (13) and a voltage suppression device (12) assist in protecting the transistor (11). The circuit (10), including the driver transistor (11) and the input protection device (13), are formed in a common collector region.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: May 12, 1998
    Assignee: Motorola, Inc.
    Inventors: David M. Heminger, Vincent L. Mirtich, William H. Grant
  • Patent number: 5747834
    Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the PNP transistor.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: May 5, 1998
    Inventors: Julian Zhiliang Chen, Ajith Amerasekera, Thomas A. Vrotsos
  • Patent number: 5736779
    Abstract: A semiconductor device has a Zener diode disposed between a gate and a source of a MOS type semiconductor device. The Zener diode is structured as N.sup.+ /P/P.sup.+ /P/N.sup.+. The P.sup.+ region functions as a channel stopper, and suppresses the occurrence of leakage current caused by an inversion of a surface of the low concentration P region. The adjustment of the width of the P.sup.+ region enables the controlling of a Zener voltage. The Zener diode protects the gate, and the arrangement enables the prevention of the occurrence of leakage current between the gate and the source.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: April 7, 1998
    Assignee: NEC Corporation
    Inventor: Kenya Kobayashi
  • Patent number: 5729044
    Abstract: A high voltage avalanche diode formed in an integrated circuit includes vertical power components. The integrated circuit is formed in an N-type semiconductor substrate. The rear surface of the substrate corresponds to a first main electrode of the power components, whose second main electrodes correspond to regions formed in P-type wells which are formed in the front surface of the substrate. The diode includes a P-type region wound substantially as a spiral that is formed in the front surface of the substrate; non-overlapping N-type regions formed in equal number in each turn of the spiral and forming with the spiral elemental avalanche diodes; metallizations connecting in series the elemental diodes; and a connection between an end of the spiral and the first electrode.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: March 17, 1998
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jacques Mille, Philippe Meunier
  • Patent number: 5691558
    Abstract: An avalanche breakdown diode includes a p-doped trough in which a highly p-doped region is introduced. In addition to the trough, an n-doped region is introduced, which is underlaid by a p-doped layer. The trough and the p-doped layer define a precisely established interspace. The arrangement is introduced into a p-type substrate. An insulating layer and thereon, in turn, a conductive layer are applied over the region between the trough and the p-doped layer. The conductive layer and the n-doped region are connected to a positive voltage and the highly p-doped region is connected to a negative voltage. A drift of the breakdown voltage is thereby prevented. In addition, the resistance during the breakdown is small due to the defined interspace between the trough and the layer.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: November 25, 1997
    Assignee: Robert Bosch GmbH
    Inventor: Neil A. Davies
  • Patent number: 5675533
    Abstract: A latch-type SRAM memory cell having a number of MOS transistors arranged to maintain symmetry with each other circuitwise, in which the source regions of the MOS transistors are arranged so as to be adjacent semiconductor regions of opposite conductivity with respect thereto. Zener diodes are formed between the adjacent source and semiconductor regions with each of these Zener diodes being connected between their respective source regions and a power supply. Since current to each source region of paired MOS transistors flows effectively to the power supply or ground side via a Zener diode using a tunneling effect, a rise in the source region potential can be reduced, and an increase in the transistor threshold value can be controlled. In this way, symmetry of the paired transistors can be maintained, and the performance of the memory cell, e.g., memory cell data retention ability and drive current ability, can be increased.
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: October 7, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Takayuki Niuya, Yuji Iwasawa
  • Patent number: 5656835
    Abstract: A very high sensitive solid state imager is realized by employing a multiplication process which includes avalanche multiplication of charges as generated by an incident light at each of several optical to electrical converting components (hereafter referred to as a photosite). Thus, the functions of a high speed electron shutter are obtained. Notwithstanding a high sensitivity, a reduced supply voltage for avalanche multiplication can be realized by laminating a transparent electrode of poly-silicon or ITO on a photosite, applying an avalanche multiplication voltage thereupon through its capacity coupling, and simultaneously applying a negative voltage on a read-out gate during a readout time. Furthermore, a reduced readout voltage can also be realized by laminating a transparent electrode of poly-silicon or ITO, on a photosite, and applying a voltage of polarity opposite to that applied during an avalanche multiplication time.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: August 12, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyoshi Komobuchi
  • Patent number: 5646433
    Abstract: A diode structure for protecting a pad in an integrated circuit formed in a P-type substrate coupled between a first supply terminal connected to the substrate and a second supply terminal. The structure includes a P-type pocket whose edges and bottom contact an N-type region, an N-type area formed in the pocket, an N-type ring laterally surrounding the region of the second conductivity type and contacting the substrate, and a P-type well surrounding the ring. The ring and the pocket are connected to the pad, the N-type area formed in the pocket is connected to the second supply terminal and the well is connected to the first supply terminal.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 8, 1997
    Assignee: SGS Thomson Microelectronics S.A.
    Inventor: Jean Jimenez
  • Patent number: 5631493
    Abstract: A monolithic component incorporates a protection diode in parallel with a plurality of pairs of diodes having the same polarity. The monolithic component is formed from an N-type semiconductor substrate and includes P-type first regions that are formed at the upper surface of the substrate; second regions constituted by upper portions of the substrate, whose lateral surfaces are delineated by P-type insulating walls; a P-type third region at the bottom of the second regions; a fourth P.sup.+ -type region formed from the lower surface in the third region; a fifth N+-type region on the lower surface of the substrate; first metallizations connecting each of the first regions to each of the second regions; and a second metallization on at least one portion of the insulating wall.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: May 20, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Robert Pezzani
  • Patent number: 5612564
    Abstract: A semiconductor device with a metal-insulator-semiconductor transistor and a limiter or sacrifice diode has predetermined breakdown voltage and constant withstand voltage. The device includes a special well region underlying a drain portion or contacting an edge of a drain portion.
    Type: Grant
    Filed: January 6, 1995
    Date of Patent: March 18, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoto Fujishima, Gen Tada
  • Patent number: 5612568
    Abstract: A low-noise Zener diode that enables to improve the surge resistance performance without degeneration of its low-noise characteristic is provided. The diode contains a semiconductor substrate of a first conductivity type and a first impurity doped region of a second conductivity type formed in a surface area of the substrate. The first impurity doped region has spaces into which no impurity of the second conductivity type is doped. The diode further contains a second impurity doped region of the second conductivity type formed in the first impurity doped region. The second impurity doped region has a depth less than that of the first impurity doped region. The second impurity doped region is contacted with the substrate in the spaces, producing main p-n junctions of the diode at respective interfaces of the second impurity doped regions and the substrate. The second impurity doped region is contacted with the first impurity doped region other than in the spaces.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: March 18, 1997
    Assignee: NEC Corporation
    Inventor: Takao Arai
  • Patent number: 5594266
    Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: January 14, 1997
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, William A. Krieger, Susan L. Feindt
  • Patent number: 5578859
    Abstract: A semiconductor structure having one or a plurality of lateral, high-blocking semiconductor components in a semiconductor of a metalized substrate (2), a dielectric layer (3) contiguous to the substrate, a homogeneously doped drift zone (4) disposed above the dielectric layer, and having heavily-doped zones of the semiconductor components which are formed in or extend into the drift zone and are electrically contacted. At least the zones (5, 6) of the semiconductor components, which can have a high potential difference with respect to the substrate during operational functioning mode of the semiconductor components, extend up to the dielectric layer (3).
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: November 26, 1996
    Assignee: Daimler-Benz AG
    Inventors: Wolfgang Wondrak, Raban Held, Erhard Stein, Horst Neubrand
  • Patent number: 5572044
    Abstract: A semiconductor commutator which is constructed by joining a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type, wherein there is provided a grain boundary which is located near a junction surface of the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type so as not to cross said junction surface.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: November 5, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toru Koizumi, Hidemasa Mizutani
  • Patent number: 5541426
    Abstract: A semiconductor device is provided with a surface-inactivated semiconductor layer provided on the surface of a compound semiconductor on which surface a semiconductor layer forming the depletion layer is provided, the semiconductor layer forming the depletion layer being of a conduction type opposite that of the compound semiconductor, and having a carrier density and thickness being capable of forming a depletion layer on the compound semiconductor. When a depletion layer is formed on the surface of the compound semiconductor by the semiconductor layer forming the depletion layer, the depletion layer has no charge so that the concentration of electrical fields is relaxed, the surface of the semiconductor is stabilized, and excellent dielectric breakdown performance is obtained.
    Type: Grant
    Filed: March 2, 1995
    Date of Patent: July 30, 1996
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Masaaki Abe, Ken-ichi Nonaka
  • Patent number: 5541140
    Abstract: Semiconductor arrangements, in particular diodes, have a p-layer and two n-layers that are doped to varying degrees of thickness. The p-n junction between the p-layer and the heavily doped n-layer is arranged in the chip so as to allow it to lie completely inside the chip. The p-n junction between the p-layer and the n-layer is situated in the outside areas of the chip. This arrangement does not permit any high field strengths to occur on the outside of the chip and, at the same time, it makes it possible for easily reproducible properties to be achieved. The manufacturing method can also be carried-out outside of a clean room.
    Type: Grant
    Filed: June 23, 1994
    Date of Patent: July 30, 1996
    Assignee: Robert Bosch GmbH
    Inventors: Herbert Goebel, Vesna Biallas, Richard Spitz, Anton Mindl
  • Patent number: 5500541
    Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: March 19, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomohide Terashima, Masanori Fukunaga
  • Patent number: 5497345
    Abstract: To protect the thin tunnel oxide layer interposed between the floating gate region of memory cells and the substrate and which are subject to in-process damage, when the wafer is subjected to radiation, provision is made for a diode, connected between the control gate region of the cells and the substrate. The diode defines a conductive path that, when normal operating voltage is applied to the control gate regions, is turned off and has no effect on normal operation of the memory, and which is turned on to permit the passage of charges between the control gate region and the substrate, when the control gate potential exceeds normal operating potential but is less than the breakdown voltage of the tunnel oxide divided by the coupling factor of the control and floating gate regions of the cells. The diode is appropriately formed prior to patterning the control gate regions of the cells.
    Type: Grant
    Filed: February 15, 1994
    Date of Patent: March 5, 1996
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Paolo G. Cappelletti
  • Patent number: 5479031
    Abstract: An overvoltage protection device having multiple shorting dots in the emitter region and multiple buried regions substantially aligned with these shorting dots. The placement, number, and area of these buried regions reduce and more accurately set the overshoot voltage value of the device while maintaining the high surge capacities of the device. Further, doping types and concentrations have been modified from that known in the prior art to reduce overshoot providing a more accurate and sensitive overvoltage protection device than that known previously in the prior art.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: December 26, 1995
    Assignee: Teccor Electronics, Inc.
    Inventors: Monty F. Webb, Elmer L. Turner
  • Patent number: 5479046
    Abstract: The invention relates to a monolithically integrated semiconductor arrangement, where from the first main surface a first zone (p) and a second zone (n.sup.+) are diffused into a substrate (2), which is weakly doped (substrate region n.sup.-) under a first main surface (3) and is more strongly doped (substrate region n.sup.+) under a second main surface (4). An insulating passivation layer is attached to the first main surface (3), on top of which a metallic cover electrode (D) is located, which covers adjacent substrate regions (n.sup.-) and the edge areas of the first zone (p) and the second zone (n.sup.+). In accordance with the invention, at least one additional zone (.nu.) of the same type of conductivity as the associated zone (n.sup.+), but with weaker doping, is diffused in for increasing the break-through voltage, and is connected to the zone (n.sup.+), does not contact the other zone (p) and prevents the zone (n.sup.+) from directly bordering the substrate (n.sup.
    Type: Grant
    Filed: June 22, 1994
    Date of Patent: December 26, 1995
    Assignee: Robert Bosch GmbH
    Inventors: Peter Flohrs, Christian Pluntke
  • Patent number: 5477078
    Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: December 19, 1995
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, William A. Krieger, Susan L. Feindt
  • Patent number: 5475258
    Abstract: A semiconductor device has a protective Zener diode formed through an insulation film to a silicon substrate having a power MOSFET formed thereon. The breakdown strength of the insulation film is substantially improved and the withstand voltage of the Zener diode can be set to a high value. A gate plate 11 electrically connected to an outer circumferential part of a p-type diffusion region 104 is installed, and element parts 112a-112c and equipotential plates 113a-133c constituting a Zener diode group 115 are formed. The equipotential plates 113a-133c hold a prescribed potential by Zener diode pairs 114 of the element parts 112a-112c.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: December 12, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Naohito Kato, Etsuji Toyoda, Naoto Okabe
  • Patent number: 5475245
    Abstract: A voltage regulator diode according to the present invention comprises: a semiconductor substrate (W); a highly doped source region (3) formed in the substrate (W) to adjoin one surface thereof; a highly doped drain region (D) formed in tile substrate (W) to adjoin the above-mentioned surface; a source electrode (4) held in contact with the source region (3); a shorting electrode (9) held in contact with the drain region (D); a gate insulating portion (8a) formed between the source region (3) and the drain region (4) to partly cover the above-mentioned surface of the substrate (W); and a gate electrode (10) formed to cover the gate insulating portion (8a). The gate electrode (19) is shorted to the drain region (D) through the shorting electrode (9). As a result, a channel (12) is formed in the substrate (W) to establish conduction between the source region (3) and the drain region (4) when a gate voltage not less than a predetermined threshold value is applied.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: December 12, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Koichi Kudo, Hiroshi Kadonishi
  • Patent number: 5468673
    Abstract: A reference diode is formed in an N-type insulated well. An avalanche diode includes a P-type deep region having a high doping level, beneath which is formed an N-type overlapping buried layer, a P-type deep diffused region contacting a central portion of the deep region, a second, P-type, deep diffused region contacting the periphery of the deep region, an N-type highly doped surface region coating the surface of the first deep diffused region and forming therewith an avalanche junction. At least another structure identical to the avalanche diode structure, without the N-type surface region, forms a resistor between its electrodes.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: November 21, 1995
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Gerard Le Roux, Jacques Le Menn
  • Patent number: 5453629
    Abstract: A photoelectric conversion device includes a plurality of photoelectric conversion units and a signal output unit. The signal output unit has at least one storage device for storing electrical signals generated by the photoelectric conversion device. A scanning device scans the electrical signals generated by the electric conversion units, and a reading device reads out electrical signals generated by the photoelectric conversion units. Each of the photoelectric conversion units includes a light absorption layer and a multiplication layer. The multiplication layer includes at least one step-back structure which multiplies carriers produced by absorption of light, and in which a forbidden band width changes continuously from a minimum to a maximum width.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: September 26, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ihachiro Gofuku, Masato Yamanobe, Izumi Tabata, Hiraku Kozuka
  • Patent number: 5432368
    Abstract: A diode structure for protecting a pad in an integrated circuit formed in a P-type substrate coupled between a first supply terminal connected to the substrate and a second supply terminal. The structure includes a P-type pocket whose edges and bottom contact an N-type region, an N-type area formed in the pocket, an N-type ring laterally surrounding the region of the second conductivity type and contacting the substrate, and a P-type well surrounding the ring. The ring and the pocket are connected to the pad, the N-type area formed in the pocket is connected to the second supply terminal and the well is connected to the first supply terminal.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: July 11, 1995
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jean Jimenez
  • Patent number: 5430311
    Abstract: A constant-voltage diode has a first semiconductor region of a first conductivity type, an adjoining semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type adjoining the second semiconductor region, and a fourth semiconductor region of the first conductivity type partially surrounded by the second semiconductor region. At low reverse biases between a cathode electrode and an anode electrode, the behavior of the device is determined by the pn junction between the first and second semiconductor regions. As the reverse biasing increases, the depletion layers of that junction will reach the fourth semiconductor region, but the reverse bias at this time is insufficient to break down that junction. A further increase of reverse bias causes breakdown of the pn junction between the third and fourth semiconductor regions. This effect is achieved by suitable impurity concentrations in the semiconductor regions.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: July 4, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Murakami, Yukimasa Satou, Hiroshi Narita
  • Patent number: 5416351
    Abstract: An ESD protection diode for a CMOS or BiCMOS integrated circuit formed by imbedding a Zener diode in the drain of a MOS device used as a protection diode. The Zener diode may be formed with the preexisting process steps of a BiCMOS process, and it provides a low voltage trigger for avalanche breakdown in the MOS ESD protection diode.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: May 16, 1995
    Assignee: Harris Corporation
    Inventors: Akira Ito, Michael D. Church
  • Patent number: 5401985
    Abstract: A monolithic protection component is formed in a P-type low-doped semiconductor substrate. The protection diode comprises, in an upper surface of the substrate, a first and a second N-type well with a mean doping level; at the surface of the first well, a first highly doped P region; at the surface of the second well, a second very highly doped N region; a third very highly doped N region laterally contacting the first well; a fourth highly-doped P region beneath a portion of the lower surface of the third region; a first metallization contacting the surface of the first and second regions which constitute the first diode terminal; and a second metallization coupled to a P-type area extending up to the fourth region and second well, which forms the second terminal of the diode. The protection component provides a unidirectional protection diode. Two of the protection components may be combined in a single structure to provide a bidirectional protection diode.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: March 28, 1995
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Christine Anceau
  • Patent number: 5387807
    Abstract: Generally, and in one form of the invention, a p-n junction diffusion barrier is disclosed comprising a first semiconductor layer 28 of p-type conductivity, a second semiconductor layer 32 of n-type conductivity and a third semiconductor layer 30 of p-type conductivity disposed between the first and second layers, the third layer being doped with a relatively low diffusivity dopant in order to form a diffusion barrier between the first and the second semiconductor layers.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: February 7, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 5386138
    Abstract: A semiconductor device including first and second diodes which are provided on the same side of a semiconductor substrate of a first conductivity type and which are connected in series with each other through the substrate. A main surface of the substrate is covered with an insulator film having first and second windows. A first patterned conductive film of a second conductivity type is in contact with the main surface of the substrate through the first window. The first conductive film and the substrate forme a p-n junction of a first diode at their interface. A second patterned conductive film is formed on the first conductive film acting as one of electrodes of the semiconductor device. A first conductive region of the second conductivity type is formed in a surface area of the substrate adjacent to the main surface. The first conductive region and the substrate form a p-n junction of a second diode at their interface.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: January 31, 1995
    Assignee: NEC Corporation
    Inventor: Isao Yoshino
  • Patent number: 5371385
    Abstract: A vertical type surge protection device for absorbing surges of either polarity has a second region forming a first pn junction with a first region, a third region forming a first minority carrier injection junction with respect to the second region, a fourth region forming a second pn junction with the first region and a fifth region forming a second minority carrier injection junction with the fourth region. When the absolute value of a surge voltage applied across the device exceeds the breakdown voltage, either the one of the first and second pn junctions that is reverse biased owing to the surge polarity breaks down or punch-through occurs between the first and third regions or between the first and fifth regions, whereafter breakover ensues as a result of positive feedback.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: December 6, 1994
    Assignees: Agency of Industrial Science & Technology, Ministry of International Trade & Industry, Sankosha Corporation, Ome Cosmos Electric Co., Ltd.
    Inventors: Yutaka Hayashi, Masaaki Sato, Yoshiki Maeyashiki