Subsurface Breakdown Patents (Class 257/606)
  • Patent number: 10685955
    Abstract: A method for forming a trench diode for a power semiconductor device includes forming a first trench having a first opening and a second trench having a second opening in a substrate material, the second opening of the second trench being wider than the first opening of the first trench. An insulating layer is formed over surfaces of the first and second trenches. A first semiconductor material is provided within the first and second trenches, the first semiconductor material filling the first trench at least until the first opening is entirely plugged and partially filling the second trench so that a portion of the second opening remains open, the first semiconductor material having a first conductivity type. A second semiconductor material is provided within the second trench and over the first semiconductor material, the second semiconductor material having a second conductivity type that is different from the first conductivity type.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 16, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jongho Park, Sangsu Woo, SangYong Lee, SeWoon Kim
  • Patent number: 10424578
    Abstract: A semiconductor device of an embodiment includes a conductive semiconductor substrate, an insulating film formed on the semiconductor substrate, an overvoltage protection diode configured to be formed on the insulating film and to include an n-type semiconductor layer and a p-type semiconductor layer alternately arranged adjacent to each other, and an insulating film that covers the overvoltage protection diode. The concentration of the p-type impurities in the p-type semiconductor layer is lower than the concentration of the n-type impurities in the n-type semiconductor layer. The concentration peak of the p-type impurities is disposed in a non-boundary region between a boundary region and a boundary region.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 24, 2019
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
  • Patent number: 9842836
    Abstract: A diode according to the present invention includes a semiconductor layer of a first conductivity type having an impurity concentration of 1×1016 cm?3 to 2.4×1017 cm?3, a Zener diode region of a second conductivity type formed selectively in the semiconductor layer and forming a pn junction with the semiconductor layer, a Schottky metal disposed on the semiconductor layer, forming a Schottky junction with the semiconductor layer, and having a work function of 3 eV to 6 eV, and a JBS (junction barrier Schottky) structure including a plurality of second conductivity type regions formed selectively in the Schottky junction region of the semiconductor layer.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 12, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Kohei Makita, Teruhiro Koshiba
  • Patent number: 9281359
    Abstract: One embodiment of a semiconductor device includes a semiconductor body with a first side and a second side opposite to the first side. The semiconductor device further includes a first contact trench extending into the semiconductor body at the first side. The first contact trench includes a first conductive material electrically coupled to the semiconductor body adjoining the first contact trench. The semiconductor further includes a second contact trench extending into the semiconductor body at the second side. The second contact trench includes a second conductive material electrically coupled to the semiconductor body adjoining the second contact trench.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 8, 2016
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Andreas Meiser, Hans-Peter Lang, Thorsten Meyer, Peter Irsigler
  • Patent number: 9000538
    Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Murakawa
  • Patent number: 8941207
    Abstract: A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: January 27, 2015
    Assignee: University of Electronic Science and Technology
    Inventor: Xingbi Chen
  • Patent number: 8779543
    Abstract: A semiconductor device that may include an avalanche photodiode (APD), the APD may include: a first doped region of a first polarity; a buried guard ring of a second polarity, the second polarity is opposite to the first polarity, the buried guard ring is spaced apart from the first doped region and is positioned below the first doped region; a well of the second polarity, wherein the well interfaces the first doped region to form a p-n junction; and a second doped region of the second polarity, the second doped region is spaced apart from the first doped region.
    Type: Grant
    Filed: September 16, 2012
    Date of Patent: July 15, 2014
    Assignee: Technion Research and Development Foundation Ltd.
    Inventors: Yael Nemirovsky, Vitali Savuskan, Sharon Bar-Lev Shefi, Igor Brouk, Gil Visokolov, Amos Fenigstein, Tomer Leitner
  • Patent number: 8637875
    Abstract: Apparatuses and systems for photon detection can include a first optical sensing structure structured to absorb light at a first optical wavelength; and a second optical sensing structure engaged with the first optical sensing structure to allow optical communication between the first and the second optical sensing structures. The second optical sensing structure can be structured to absorb light at a second optical wavelength longer than the first optical wavelength and to emit light at the first optical wavelength which is absorbed by the first optical sensing structure. Apparatuses and systems can include a bandgap grading region.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: January 28, 2014
    Assignee: The Regents of the University of California
    Inventors: Hod Finkelstein, Sadik C. Esener, Yu-Hwa Lo, Kai Zhao, James Cheng, Sifang You
  • Patent number: 8492866
    Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
  • Patent number: 8217416
    Abstract: Provided are a light emitting device package and a method for fabricating the same. The light emitting device package comprises a substrate; a light emitting device on the substrate; a zener diode comprising a first conductive type impurity region and two second conductive type impurity regions, the first conductive type impurity region being disposed in the substrate, the two second conductive type impurity regions being separately disposed in two areas of the first conductive type impurity region; and a first electrode layer and a second electrode layer, each of them being electrically connected to the second conductive type impurity regions and the light emitting device.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: July 10, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Geun Ho Kim, Yong Seon Song, Yu Ho Won
  • Patent number: 8188507
    Abstract: Provided are a light emitting device package and a method for fabricating the same. The light emitting device package comprises a substrate; a light emitting device on the substrate; a zener diode comprising a first conductive type impurity region and two second conductive type impurity regions, the first conductive type impurity region being disposed in the substrate, the two second conductive type impurity regions being separately disposed in two areas of the first conductive type impurity region; and a first electrode layer and a second electrode layer, each of them being electrically connected to the second conductive type impurity regions and the light emitting device.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: May 29, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Geun Ho Kim, Yong Seon Song, Yu Ho Won
  • Patent number: 8138520
    Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Mark Duskin, Suem Ping Loo, Ali Salih
  • Patent number: 8084815
    Abstract: A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: December 27, 2011
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Jae-gil Lee, Jin-young Jung, Ho-cheol Jang, Chong-man Yun
  • Patent number: 8026576
    Abstract: There is provided a wiring board. The wiring board includes: a semiconductor substrate having a through hole and covered with an insulating film; a through electrode formed in the through hole; a first wiring connected to one end of the through electrode; and a second wiring connected to the other end of the through electrode. The semiconductor substrate includes: a semiconductor element and a first guard ring formed to surround the through hole. The semiconductor element includes a first conductivity-type impurity diffusion layer having a different conductivity-type from that of the semiconductor substrate and is electrically connected to the first wiring and the second wiring.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 27, 2011
    Assignees: Shinko Electric Industries Co., Ltd., Asahi Kasei Microdevices Corporation
    Inventors: Kei Murayama, Shinji Nakajima
  • Patent number: 7989923
    Abstract: A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type, an epitaxial layer, and five diffused regions. The buried layer and the semiconductor substrate form a first semiconductor junction. The first diffused region of the second conductivity type and the semiconductor substrate form a second semiconductor junction. The fourth diffused region of the first conductivity type and the third diffused region of the second conductivity type form a third semiconductor junction. The fifth diffused region of the first conductivity type and the second diffused region of the second conductivity type form a fourth semiconductor junction.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: August 2, 2011
    Assignee: Amazing Microelectronic Corp.
    Inventors: Tang-Kuei Tseng, Kun-Hsien Lin, Hsin-Chin Jiang
  • Patent number: 7781786
    Abstract: Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: August 24, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7638857
    Abstract: A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: December 29, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yen Hwang, Shu-Hsuan Su, Tien-Hao Tang
  • Patent number: 7538367
    Abstract: The present invention provides an avalanche photodiode capable of raising productivity. An n-type InP buffer layer, an n-type GaInAs light absorption layer, an n-type GaInAsP transition layer, an n-type InP electric field adjusting layer, an n-type InP avalanche intensifying layer, an n-type AlInAs window layer and a p-type GaInAs contact layer are grown in order on an n-type InP substrate. Next, Be is ion-injected into an annular area along the outer periphery of a light receiving area which is activated by heat treatment so as to form an inclined joint, to obtain a p-type peripheral area for preventing an edge break down. Further, Zn is selectively diffused thermally into the light receiving area until it reaches the n-type InP avalanche intensifying layer so as to form a p-type conductive area.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: May 26, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eiji Yagyu, Eitaro Ishimura, Masaharu Nakaji
  • Patent number: 7521774
    Abstract: In a semiconductor system 20 made up of multiple sublayers, a sublayer over the largest part of a cross-sectional area BC in the interior of the semiconductor system borders immediately on the first sublayer, while bordering on a second sublayer only in a comparatively narrow edge region of the cross-sectional area. The semiconductor system is characterized by a low bulk resistance and a high breakdown voltage in the edge region. In addition, a method for manufacturing this semiconductor system is specified.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: April 21, 2009
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Dana Keppeler
  • Patent number: 7511357
    Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: March 31, 2009
    Assignee: Force-MOS Technology Corporation
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7361942
    Abstract: A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: April 22, 2008
    Assignee: Protek Devices, LP
    Inventors: Fred Matteson, Venkatesh Panemangalore Pai, Donald K. Cartmell
  • Patent number: 6936907
    Abstract: This invention provides a method or an auxiliary method to implement optimum variation lateral flux on a semiconductor surface. The method is to cover one or more thin films of high permittivity dielectric material on the semiconductor surface. The one or more films are capable of transmitting flux into or extracting flux from the semiconductor surface, or even to extract some flux from a part of the semiconductor surface and then transmit the flux to another part of the semiconductor surface. By using optimum variation lateral flux, not only can high-voltage lateral devices be made, but also an edge-termination technique for high-voltage vertical devices is provided. While the thin films can be used to prevent the occurrence of strong electric fields produced at the edges of some doped regions, these regions are used to compensate other doped regions with opposite doping and different location.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: August 30, 2005
    Assignee: The University of Electronic Science and Technology of China
    Inventor: Xingbi Chen
  • Patent number: 6936868
    Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: August 30, 2005
    Assignee: Anritsu Corporation
    Inventors: Jun Hiraoka, Kazuo Mizuno, Yuichi Sasaki
  • Patent number: 6867436
    Abstract: A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: March 15, 2005
    Assignee: Protek Devices, LP
    Inventors: Fred Matteson, Venkatesh Panemangalore Pai, Donald K. Cartmell
  • Publication number: 20040222498
    Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.
    Type: Application
    Filed: May 6, 2003
    Publication date: November 11, 2004
    Applicants: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Shane Wrschka
  • Patent number: 6815799
    Abstract: A semiconductor integrated circuit device with built-in spark killer diodes suitable for output transistor protection has a problem such that a leakage current to the substrate is great and a desirable forward current cannot be obtained. In a semiconductor integrated circuit device of the present invention, P+-type first and second diffusion regions 34 and 32 are formed on the surface of a second epitaxial layer 23 in a partly overlapping manner. And, by a connection to an anode electrode 39 at a part immediately over the P+-type second diffusion region 32, a parasitic resistance R1 is made greater than a parasitic resistance R2. Thus, an operation of a parasitic transistor TR2 that causes a leakage current to a substrate 21 is suppressed, whereby leakage current can be greatly reduced.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: November 9, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeaki Okawa, Koichiro Ogino
  • Patent number: 6803644
    Abstract: A plurality of connection holes 24 for connecting n+ type semiconductor region 20 of zener diodes (D1, D2) and wires 21 and 22 to each other are not arranged in the center of the n+ type semiconductor region 20, that is, in a region in which a p+ type semiconductor region 6 and the n+ type semiconductor region 20 form a junction but is arranged in the periphery which is deeper than the center in junction depth. In addition, these connection holes 24 are spaced from each other so that a pitch between the adjacent connection holes 24 is greater than a minimum pitch between connection holes of the circuit, and thereby a substrate shaving quantity is reduced when the respective connection holes 24 are formed by means of dry etching.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: October 12, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Minami, Yoshiaki Kamigaki, Hideki Yasuoka, Fukuo Owada
  • Patent number: 6784520
    Abstract: A constant voltage device includes n-type and p-type doped layers. The n-type doped layer is formed by heavily doping with an n-type impurity an upper portion of a p-type silicon semiconductor substrate, in an active region defined by an isolating insulator film. The p-type doped layer is formed by doping the region under the n-type doped layer with a p-type impurity. The n-type and p-type doped layers are provided to form two layers in parallel with the substrate surface of the semiconductor substrate, whereby a pn junction formed between the n-type and p-type doped layers creates a diode structure. Impurity concentration in the p-type doped layer is established so that the impurity concentration of a portion adjacent the isolating insulator film is lower that that of the rest.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: August 31, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Doi
  • Patent number: 6734515
    Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: May 11, 2004
    Assignees: Mitsubishi Cable Industries, Ltd., Nikon Corporation
    Inventors: Kazuyuki Tadatomo, Hiroaki Okagawa, Youichiro Ohuchi, Masahiro Koto, Kazumasa Hiramatsu, Yutaka Hamamura, Sumito Shimizu
  • Patent number: 6730979
    Abstract: A recessed p-type region cap layer avalanche photodiode (12) is provided. The photodiode (12) includes a semiconductor substrate (30) and a semiconductor stack (32), which is electrically coupled to the substrate (30). A cap layer (34) is electrically coupled to the stack (32) and includes a recessed p-type region (36). The recessed p-type region (36) forms a p-n junction (38) with the stack (32). A method of forming the photodiode (12) is also provided. The method includes forming the substrate (30), the stack (32), and the cap layer (34). The cap layer (34) is selectively etched to expose the stack (32) and form a cap layer opening (42). Dopant is diffused through the cap layer opening (42) into the stack (32) to form the p-n junction (38).
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: May 4, 2004
    Assignee: The Boeing Company
    Inventor: Joseph C. Boisvert
  • Patent number: 6706606
    Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: March 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Jr., Darrel C. Oglesby, Jr.
  • Publication number: 20040041237
    Abstract: This invention provides a method or an auxiliary method to implement optimum variation lateral flux on a semiconductor surface. The method is to cover one or more thin films of high permittivity dielectric material on the semiconductor surface. The one or more films are capable of transmitting flux into or extracting flux from the semiconductor surface, or even to extract some flux from a part of the semiconductor surface and then transmit the flux to another part of the semiconductor surface. By using optimum variation lateral flux, not only can high-voltage lateral devices be made, but also an edge-termination technique for high-voltage vertical devices is provided. While the thin films can be used to prevent the occurrence of strong electric fields produced at the edges of some doped regions, these regions are used to compensate other doped regions with opposite doping and different location.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 4, 2004
    Applicant: The University of Electronic Science and Technology of China.
    Inventor: Xingbi Chen
  • Patent number: 6639301
    Abstract: A semiconductor device embraces an n-type first semiconductor region, defined by first and second end surfaces and a first outer surface connecting the first and second end surfaces; a p-type second semiconductor region, defined by third and fourth end surfaces and a second outer surface connecting the third and fourth end surfaces, the fourth end surface is in contact with the first end surface; an n-type third semiconductor region connected with the first semiconductor region at the second end surface; a p-type fourth semiconductor region connected with the second semiconductor region at the third end surface; and a fifth semiconductor region having inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region. The fifth semiconductor region surrounds the first and second semiconductor regions and is disposed between the third and fourth semiconductor regions.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: October 28, 2003
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Hideyuki Andoh
  • Publication number: 20030197247
    Abstract: A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity. Dopant concentrations range from 1×1017 to 3×1018 dopant atoms per cm3 for the anode emitter, especially on its surface 1019 dopant atoms per cm3or more for the cathode emitter and approximately 1016 dopant atoms per cm3 for the blocking function of an anode-side zone.
    Type: Application
    Filed: March 18, 2003
    Publication date: October 23, 2003
    Applicant: Infineon Technologies AG
    Inventors: Anton Mauder, Alfred Porst
  • Patent number: 6605859
    Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: August 12, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory G. Romas, Jr., Darrel C. Oglesby, Jr.
  • Patent number: 6590273
    Abstract: In the semiconductor integrated circuit device, a first P+ type buried layer formed as an anode region and an N+ type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: July 8, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeaki Okawa, Toshiyuki Ohkoda
  • Patent number: 6552413
    Abstract: Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: April 22, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noritoshi Hirano, Katsumi Satoh
  • Patent number: 6531744
    Abstract: The invention concerns an integrated circuit, including a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a Vcc power supply terminal, an input point (in) and an output point (out). At least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, and the overvoltage protection circuit includes means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point. The means include two or more diode elements of the Zener type connected in series. The substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: March 11, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Henricus Antonius Lambertus Van Lieverloo
  • Publication number: 20030015675
    Abstract: A semiconductor device which includes a capacitor wherein the capacitance of the capacitor can be prevented from being lowered even in the case that the capacitor is miniaturized. A core insulating film having the core of the capacitor formed above a semiconductor substrate, a capacitor lower electrode formed so as to cover side surfaces of this core insulating film, a capacitor dielectric film formed so as to cover the surface of this capacitor lower electrode and the upper surface of the core insulating film and a capacitor upper electrode formed so as to cover the surface of this core insulating film are provided so that the bottom surface of the core insulating film is positioned lower than the bottom surface of the capacitor lower electrode.
    Type: Application
    Filed: July 18, 2002
    Publication date: January 23, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akie Yutani
  • Patent number: 6495863
    Abstract: An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: December 17, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventor: Atsushi Narazaki
  • Publication number: 20020105055
    Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.
    Type: Application
    Filed: March 28, 2002
    Publication date: August 8, 2002
    Inventors: Walter R. Buchanan, Roman J. Hamerski
  • Patent number: 6410950
    Abstract: A pin diode includes an inner zone, a cathode zone and an anode zone. A boundary surface between the inner zone and the anode zone is at least partly curved and/or at least one floating region having the same conduction type and a higher dopant concentration than in the inner zone is provided in the inner zone. The turnoff performance in such geometrically coupled power diodes, in contrast to the turnoff performance of pin power diodes (in the Read-diode version) with spaced charge coupling, is largely temperature-independent. Hybrid diodes with optimized conducting-state and turnoff performance can be made from such FCI diodes. FCI diodes are preferably used in conjunction with switching power semiconductor elements, as voltage limiters or free running diodes.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: June 25, 2002
    Assignee: Infineon Technologies AG
    Inventors: Roland Sittig, Karim-Thomas Taghizadeh-Kaschani
  • Patent number: 6075276
    Abstract: A semiconductor device is provided which includes a first conductivity type semiconductor substrate, a second conductivity type Zener region formed in a surface layer of the first conductivity type semiconductor substrate, a first conductivity type anode region formed within the second conductivity type Zener region, an anode electrode which is formed in contact with both of the semiconductor substrate and first conductivity type anode region and is grounded, and a cathode electrode formed on a surface of the second conductivity type Zener region and connected to input and output terminals. A diode that consists of the first conductivity type semiconductor substrate and the second conductivity type Zener region and a diode that consists of the first conductivity type anode region and the second conductivity type Zener region serve as protective elements for preventing electrostatic breakdown of the semiconductor device.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: June 13, 2000
    Assignee: Fuji Electric Company, Ltd.
    Inventor: Akio Kitamura
  • Patent number: 6051457
    Abstract: An integrated circuit with a passive component and an ESD device in accordance with the present invention has: a P substrate; an N+ buried layer implanted in the P substrate; a cathode coupled to the N+ buried layer with an N area formed between the cathode and the N+ buried layer; an anode coupled to the N+ buried layer with a P area formed between the anode and the N+ buried layer; and a first P+ buried layer implanted in the N+ buried layer and below the P area to form a Zener diode. In an alternative embodiment, the ESD device may be incorporated in an integrated circuit with an active component.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: April 18, 2000
    Assignee: Intersil Corporation
    Inventor: Akira Ito
  • Patent number: 5986327
    Abstract: A base region is formed at a shallow junction and an impurity region of higher impurity concentration is formed, by a separate step, as a buried layer at a predetermined distance from the surface of a semiconductor substrate. By so doing, a bipolar diode is implemented which does not involve an increase in a base resistance even if conduction is effected over a longer period of time.
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: November 16, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Mishio, Satoshi Takahashi, Shigeru Komatsu
  • Patent number: 5883414
    Abstract: An integrated circuit with a passive component and an ESD device in accordance with the present invention has: a P substrate; an N+ buried layer implanted in the P substrate; a cathode coupled to the N+ buried layer with an N area formed between the cathode and the N+ buried layer; an anode coupled to the N+ buried layer with a P area formed between the anode and the N+ buried layer; and a first P+ buried layer implanted in the N+ buried layer and below the P area to form a Zener diode. In an alternative embodiment, the ESD device may be incorporated in an integrated circuit with an active component.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: March 16, 1999
    Assignee: Harris Corporation
    Inventor: Akira Ito
  • Patent number: 5869882
    Abstract: A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity type having an opposite conductivity type first tank disposed therein. The first tank includes relatively lower and relatively higher resistivity portions, the relatively lower doped portion isolating the relatively higher doped portion from the substrate. A first region of first conductivity type is disposed in the higher doped portion and a second region of opposite conductivity type and more highly doped than the first tank is spaced from the first region.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: February 9, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Wayne T. Chen, Ross E. Teggatz, Taylor R. Efland
  • Patent number: 5834823
    Abstract: A power transistor incorporating a constant-voltage diode maintains the breakdown voltage of the constant-voltage diode at a specified level and prevents local breakdown of an insulating film located between an A1 field plate electrode and a base region of the transistor by spacing the A1 field plate electrode located on a collector region by a distance "d" from the base region.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: November 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Ziro Honda
  • Patent number: 5757057
    Abstract: A large area avalanche photodiode device that has a plurality of contacts formed on a bottom side that are isolated from each other by various kinds of isolation structures. In one embodiment, a cavity is formed in one layer of the avalanche photodiode that extends to a depletion region that exists in the layer as a result of a voltage applied to the device. The plurality of contacts are formed in the cavity so that each of the contacts are positioned substantially adjacent the depletion region. In another embodiment, a plurality of contacts are formed in a cavity and an isolation structure comprised of a grid of semiconductor material is formed so as to be interposed between adjacent contacts. The isolation structure preferably forms a p-n junction with the surrounding semiconductor material and the p-n junction provides isolation between adjacent contacts.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: May 26, 1998
    Assignee: Advanced Photonix, Inc.
    Inventor: Andrzej J. Dabrowski
  • Patent number: 5691558
    Abstract: An avalanche breakdown diode includes a p-doped trough in which a highly p-doped region is introduced. In addition to the trough, an n-doped region is introduced, which is underlaid by a p-doped layer. The trough and the p-doped layer define a precisely established interspace. The arrangement is introduced into a p-type substrate. An insulating layer and thereon, in turn, a conductive layer are applied over the region between the trough and the p-doped layer. The conductive layer and the n-doped region are connected to a positive voltage and the highly p-doped region is connected to a negative voltage. A drift of the breakdown voltage is thereby prevented. In addition, the resistance during the breakdown is small due to the defined interspace between the trough and the layer.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: November 25, 1997
    Assignee: Robert Bosch GmbH
    Inventor: Neil A. Davies