Subsurface Breakdown Patents (Class 257/606)
  • Patent number: 5691558
    Abstract: An avalanche breakdown diode includes a p-doped trough in which a highly p-doped region is introduced. In addition to the trough, an n-doped region is introduced, which is underlaid by a p-doped layer. The trough and the p-doped layer define a precisely established interspace. The arrangement is introduced into a p-type substrate. An insulating layer and thereon, in turn, a conductive layer are applied over the region between the trough and the p-doped layer. The conductive layer and the n-doped region are connected to a positive voltage and the highly p-doped region is connected to a negative voltage. A drift of the breakdown voltage is thereby prevented. In addition, the resistance during the breakdown is small due to the defined interspace between the trough and the layer.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: November 25, 1997
    Assignee: Robert Bosch GmbH
    Inventor: Neil A. Davies
  • Patent number: 5612568
    Abstract: A low-noise Zener diode that enables to improve the surge resistance performance without degeneration of its low-noise characteristic is provided. The diode contains a semiconductor substrate of a first conductivity type and a first impurity doped region of a second conductivity type formed in a surface area of the substrate. The first impurity doped region has spaces into which no impurity of the second conductivity type is doped. The diode further contains a second impurity doped region of the second conductivity type formed in the first impurity doped region. The second impurity doped region has a depth less than that of the first impurity doped region. The second impurity doped region is contacted with the substrate in the spaces, producing main p-n junctions of the diode at respective interfaces of the second impurity doped regions and the substrate. The second impurity doped region is contacted with the first impurity doped region other than in the spaces.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: March 18, 1997
    Assignee: NEC Corporation
    Inventor: Takao Arai
  • Patent number: 5608244
    Abstract: A high speed soft recovery diode having a large breakdown voltage is disclosed. Anode P layers (3) are selectively formed in a top portion of an N.sup.- body (2). A P.sup.- layer (4a) is disposed in the top portion of the N.sup.- body (2) so as to be spacewise complementary to the anode P layers (3). In the N.sup.- body (2), P regions (5) are selectively formed below the P.sup.- layer (4a). On the N.sup.- body (2), an anode electrode (6) is disposed in contact with both the P.sup.- layer (4a) and the anode P layers (3). A cathode electrode (7) is disposed under the N.sup.- body (2) through a cathode layer (1). When the diode is reverse-biased, a depletion layer does not have a sharply curved configuration due to the P regions (5). Hence, concentration of electric field is avoided and a breakdown voltage would not deteriorate. During forward-bias state of the diode, injection of excessive holes from the anode P layers (3) into the N.sup.- body (2) is prevented, thereby reducing a recovery current.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: March 4, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Takahashi
  • Patent number: 5594266
    Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: January 14, 1997
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, William A. Krieger, Susan L. Feindt
  • Patent number: 5554882
    Abstract: An avalanche semiconductor switch device utilizes trigger input. The integrated trigger input is a charge carrier injector which injects charge carriers directly into the avalanche semiconductor switch device. The avalanche semiconductor switch device includes: an active, semi-insulating layer; an anode; a cathode; and an injector disposed on the anode contact. The injector serves to switch the device into a state of very high conductance when a positive bias is applied to the injector. The integrated trigger input allows low power optical sources to be used with the avalanche semiconductor switch device further back in the trigger chain. The injector may inject holes or electrons. The injector may be integrated on one side of the substrate.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: September 10, 1996
    Assignee: The Boeing Company
    Inventor: R. Aaron Falk
  • Patent number: 5477078
    Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: December 19, 1995
    Assignee: Analog Devices, Incorporated
    Inventors: David F. Beigel, William A. Krieger, Susan L. Feindt
  • Patent number: 5468673
    Abstract: A reference diode is formed in an N-type insulated well. An avalanche diode includes a P-type deep region having a high doping level, beneath which is formed an N-type overlapping buried layer, a P-type deep diffused region contacting a central portion of the deep region, a second, P-type, deep diffused region contacting the periphery of the deep region, an N-type highly doped surface region coating the surface of the first deep diffused region and forming therewith an avalanche junction. At least another structure identical to the avalanche diode structure, without the N-type surface region, forms a resistor between its electrodes.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: November 21, 1995
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Gerard Le Roux, Jacques Le Menn
  • Patent number: 5414295
    Abstract: A reference diode is formed in an N-type insulated well. An avalanche diode includes a P-type deep region having a high doping level, beneath which is formed an N-type overlapping buried layer, a P-type deep diffused region contacting a central portion of the deep region, a second, P-type, deep diffused region contacting the periphery of the deep region, an N-type highly doped surface region coating the surface of the first deep diffused region and forming therewith an avalanche junction. At least another structure identical to the avalanche diode structure, without the N-type surface region, forms a resistor between its electrodes.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: May 9, 1995
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Gerard Le Roux, Jacques Le Menn
  • Patent number: 5336924
    Abstract: A zener diode having a semiconductor body (1) with a surface zone (1') doped with more than 10.sup.18 atoms/cc, in which at least two regions (2, 3) are provided through diffusion, which regions have substantially the same concentration of doping atoms and adjoin a surface (4) of the surface zone (1') and form p-n junctions (5,6) with the surface zone (1'), a first region (2) having a smaller lateral cross-section and a smaller depth than a second region (3). Both regions (2, 3) are connected to a first connection electrode (7, 8) provided on the surface (4), and a second connection electrode (9), which is spaced apart from the regions (2, 3), is provided on the semiconductor body (1). The first region has a side edge (10) which is formed through lateral diffusion and which is at least partly spaced apart from the second region (3). A higher electric field is created locally in the junction (5) during operation of the zener diode owing to the side edge (10).
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: August 9, 1994
    Assignee: U.S. Philips Corporation
    Inventor: Johannes H. M. M. Quint
  • Patent number: 5298788
    Abstract: An avalanche diode is formed in an N layer (20) of a bipolar integrated circuit. The diode comprises a first (P) region (22) and N region (21) disposed inside the first region. The portion of the first region which resides under the N region and close to the interface with the latter has a first doping level. A second (P) region (23) extends under the N region with a second doping level higher than the first close to the junction. A third P region (30) is disposed under the N region and overlaps the second P region. The third region has, at its interface with the N region, a doping level intermediate the first and second doping levels.
    Type: Grant
    Filed: June 26, 1992
    Date of Patent: March 29, 1994
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jean-Michel Moreau
  • Patent number: 5241213
    Abstract: A buried Zener diode has an auxiliary Zener junction access path in parallel with the force anode/cathode path. Unlike the force anode/cathode path, the auxiliary path is effectively by-passed by the current flowing between the force anode and cathode during circuit operation, so that there is no accumulation of significant resistance-current products that would otherwise mask the Zener voltage. The Zener diode has an anode region disposed in a first surface portion of a substrate. A `force` anode is formed on a first surface portion of the anode region. A `sense` anode is disposed on a second surface portion of the anode region spaced apart from the force anode. A first cathode region is disposed in a second surface portion of the substrate spaced apart from the anode region, while a sense cathode region is disposed in a third surface portion of the substrate spaced apart from each of the anode region and the first cathode region.
    Type: Grant
    Filed: July 30, 1991
    Date of Patent: August 31, 1993
    Assignee: Harris Corporation
    Inventor: Richard Hull
  • Patent number: 5233214
    Abstract: The invention relates to a controllable, temperature-compensated voltage limiter with a p.sup.+ np.sup.+ (or n.sup.+ pn.sup.+) semiconductor structure in which the width and doping of the central zone is selected such that no avalanche or Zener effect appears when voltage is applied to the two outer layers (punch-through diode). In accordance with the invention, the voltage U.sub.B to be limited is applied between the blocking pn-juncture (B-C). In addition, an adjustable auxiliary voltage (U.sub.H) is applied between the other pn-junction (H-C). The punch-through can be set to a higher defined value via the auxiliary voltage U.sub.H, this value being independent of the temperature to a large extent.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: August 3, 1993
    Assignee: Robert Bosch GmbH
    Inventors: Alfred Gorlach, Horst Meinders