Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device comprising an insulated gate field effect transistor provided with a region having added thereto an element at least one selected from the group consisting of carbon, nitrogen, and oxygen, said region having established at either or both of the vicinity of the boundary between the drain and the semiconductor layer under the gate electrode and the vicinity of the boundary between the source and the semiconductor layer under the gate electrode for example by ion implantation using a mask. It is free from the problems of reverse leakage between the source and the drain, and of throw leakage which occurs even at a voltage below the threshold ascribed to the low voltage resistance between the source and the drain.

Abstract: A thin film transistor according to the present invention includes a gate electrode, a semiconductor layer having a channel forming region arranged on the gate electrode and an impurity region arranged on a part of the channel forming region, source and drain electrodes electrically connected to the impurity region, and a gate insulating film that electrically insulates the gate electrode and the semiconductor layer, wherein the distance between the upper end of the gate electrode and the upper end of the impurity region is larger than the distance between the upper end of the gate electrode and the upper end of the channel forming region.

Abstract: A thin-film transistor includes: a pair of n-type heavily doped regions that are horizontally spaced apart from each other; p-type channel regions that are located between the n-type heavily doped regions so as to face their associated gate electrodes, respectively; an n-type intermediate region provided between two adjacent ones of the channel regions; and two pairs of lightly doped regions. The lightly doped regions in one of the two pairs have mutually different carrier concentrations and are located between one of the heavily doped regions and one of the channel regions that is closer to the heavily doped region than any other channel region is. The lightly doped regions in the other pair also have mutually different carrier concentrations and are located between the other heavily doped region and another one of the channel regions that is closer to the heavily doped region than any other channel region is.

Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.

Abstract: In a semiconductor device including bottom-gate-type thin-film transistors, each of which includes a gate electrode provided on an insulating surface of a substrate, a semiconductor layer provided on the gate electrode via a gate insulating layer, a pair of doped semiconductor layers adjacent to the semiconductor layer, and source and drain electrodes consisting of a pair of conductors adjacent to corresponding ones of the pair of doped semiconductor layers, the thickness of portions of the semiconductor layer below the source and drain electrodes is smaller than the thickness of a portion of the semiconductor layer at a gap portion between the source and drain electrodes.

Abstract: An active-matrix substrate is provided, which suppresses the unevenness of its surface due to the height difference of the TFTs and gate and data lines from the remaining area. After TFTs, gate lines, and data lines are formed on a transparent base, a transparent dielectric layer is formed on the base to cover the TFTs, the gate lines, and the data lines. The dielectric layer is selectively etched to form transparent dielectric portions arranged in a matrix array in such a way as to form a first plurality of recesses extending along the respective gate lines and a second plurality of recesses extending along the respective data lines. Each of the portions has a thickness equal to or greater than the maximum height of the TFTs, the gate lines, or the data lines, and a distance equal to or greater than the thickness thereof from a corresponding one of the TFTs, the gate lines, or the data lines.

Abstract: To realize the reduction of a manufacturing cost and the enhancement of yield by reducing the number of steps of a TFT in an electro-optical device typified by an active matrix liquid crystal display device. A semiconductor device of the present invention is characterized by including a first wiring and a second wiring formed of a first conductive film on the same insulating surface, a first semiconductor film of one conductivity type formed on the first and second wirings so as to correspond thereto, a second semiconductor film formed on an upper layer of the first semiconductor film of one conductivity type across the first wiring and the second wiring, an insulating film formed on the second semiconductor film, and a third conductive film formed on the insulating film.

Abstract: A liquid crystal display device in the prior art has been high in its manufacturing cost for the reason that TFTs have been fabricated using, at least, five photo-masks. A liquid crystal display device which includes a pixel TFT portion having an n-channel TFT of inverse stagger type, and a retention capacitor, can be realized by three photolithographic steps in such a way that a pixel electrode 119, a source region 117 and a drain region 116 are formed by a third photo-mask.

Abstract: A display device of the present invention includes: a plurality of pixel electrodes defining a plurality of pixels that are arranged in a matrix pattern; optical switching elements electrically connected to the plurality of pixel electrodes, respectively; and scanning signal light emitting elements for emitting dotted light, as scanning signals, to the optical switching elements. The distance between the optical switching element and the scanning signal light emitting element is less than the pixel pitch at which the plurality of pixels are arranged.

Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.

Abstract: A thin film field effect transistors and manufacturing method for the same are described. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor is endowed with immunity to illumination incident thereupon which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors which are located in order not to receive light rays.

Abstract: There is provided a semiconductor device including a semiconductor circuit formed by semiconductor elements having an LDD structure which has high reproducibility, improves the stability of TFTs and provides high productivity and a method for manufacturing the same. In order to achieve the object, the design of a second mask is appropriately determined in accordance with requirements associated with the circuit configuration to make it possible to form a desired LDD region on both sides or one side of the channel formation region of a TFT.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: A functional device free from cracking and having excellent functional characteristics, and a method of manufacturing the same are disclosed. A low-temperature softening layer (12) and a heat-resistant layer (13) are formed in this order on a substrate (11) made of an organic material such as polyethylene terephthalate, and a functional layer (14) made of polysilicon is formed thereon. The functional layer (14) is formed by crystallizing an amorphous silicon layer, which is a precursor layer, with laser beam irradiation. When a laser beam is applied, heat is transmitted to the substrate (11) and the substrate (11) tends to expand. However, a stress caused by a difference in a thermal expansion coefficient between the substrate (11) and the functional layer (14) is absorbed by the low-temperature softening layer (12), so that no cracks and peeling occurs in the functional layer (14). The low-temperature softening layer (12) is preferably made of a polymeric material containing an acrylic resin.

Abstract: The present invention discloses a thin film transistor and a process for forming thereof by a high anisotropy etching process. A thin film transistor according to the present invention comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes; a passivation layer being deposited on the layers and having first openings for contact holes; and an interlayer insulator extending along with the passivation layer and having second openings for the contact holes, the first openings and the second openings being aligned each other over the substrate, wherein an electrical conductive layer is deposited on an inner wall of the contact hole and the inner wall is formed by the first and second openings tapered smoothly and continuously through an anisotropic etching process.

Abstract: A semiconductor integared circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabriacting such circuits will be provided. A gate insulating film of the TFT required to operate a high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).

Abstract: There is provided a patterning method which makes it possible to form a desired preferable pattern having no reduction in the pattern thickness in a boundary portion where a group of patterns are joined using a plurality of exposure masks. There is provided a patterning method for forming a group of patterns in which first patterns to serve as basic units are repetitively arranged using a plurality of exposure masks. When a third region sandwiched by a first region exposed with a first exposure mask and a second region exposed with a second exposure mask is exposed with the first and second exposure masks in a complementary manner, repetitive unit patterns for exposing the third region are different from the first patterns.

Abstract: The present invention provide an LDD type TFT having excellent properties, particularly for a liquid crystal display unit. For this purpose, a top gate type LDDTFT gate electrode is converted into a two-stage structure by use of a chemical reaction or plating, and furthermore, into a shape in which an upper portion or a lower portion slightly protrudes on the source electrode side, or the drain electrode side relative to the other portions. Impurities are injected by using this electrode having this structure and shape as a mask. Prior to injection of impurities, the gate insulating film is removed, and a Ti film is formed for preventing hydrogen for dilution from coming in. This is also the case with the LDD-TFT on the bottom gate side.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: A valve for use in microfluidic structures. The valve uses a spherical member, such as a ball bearing, to depress an elastomeric member to selectively open and close a microfluidic channel. The valve may be operated manually or by use of an internal force generated to shift the spherical member to its activated position.

Abstract: A thin-film semiconductor device which has a pixel array section and a peripheral circuit section arranged around it, said pixel array section containing pixel electrodes and thin-film transistors for pixels which switch the pixel electrodes, said peripheral circuit section containing driving circuits each having thin-film transistors for circuits which drive the thin-film transistors for pixels, said each thin-film transistor having the laminate structure having a semiconductor thin film, a gate electrode, and a gate insulating film interposed between them, and said semiconductor thin film having a channel region inside the end of the gate electrode, a lightly doped region outside said channel region, a heavily doped region outside said lightly doped region, and a concentration boundary which separates said lightly doped region and heavily doped region from each other, wherein said concentration boundary measured from the end of said gate electrode is positioned more inside in said thin-film transistor for c

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device, includes a transistor configured to control the emission of electrons from an emitter.

Abstract: Amorphous and polycrystalline silicon (hybrid) devices are formed close to one another employing laser crystallization and back side lithography processes. A mask (e.g., TiW) is used to protect the amorphous silicon device during laser crystallization. A patterned nitride layer is used to protect the amorphous silicon device during rehydrogenation of the polycrystalline silicon. An absorption film (e.g., amorphous silicon) is used to compensate for the different transparencies of amorphous and polycrystalline silicon during the back side lithography. Device spacing of between 2 and 50 micrometers may be obtained, while using materials and process steps otherwise compatible with existing hybrid device formation processes.

Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.

Abstract: The present invention discloses a thin film transistor (TFT) and fabrication method thereof for a liquid crystal display device.

Abstract: A semiconductor device with a SOI structure comprises; a SOI substrate having a buried insulating film and a first conductivity type surface semiconductor layer on the buried insulating film; second conductivity type source and drain regions formed in the surface semiconductor layer; and a gate electrode formed over a first conductivity type channel region between the source and drain regions via a gate insulating film, wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer has a first conductivity type high-concentration impurity diffusion region whose first conductivity type impurity concentration is higher than that in a surface of the channel region and which is adjacent to the buried insulating film.

Abstract: A high quality semiconductor device comprising at least a semiconductor film having a microcrystal structure is disclosed, wherein said semiconductor film has a lattice distortion therein and comprises crystal grains at an average diameter of 30 Å to 4 &mgr;m as viewed from the upper surface of said semiconductor film and contains oxygen impurity and concentration of said oxygen impurity is not higher than 7×1019 atoms.cm−3 at an inside position of said semiconductor film. Also is disclosed a method for fabricating semiconductor devices mentioned hereinbefore, which comprises depositing an amorphous semiconductor film containing oxygen impurity at a concentration not higher than 7×1019 atoms.cm−3 by sputtering from a semiconductor target containing oxygen impurity at a concentration not higher than 5×1018 atoms.

Abstract: The present invention discloses a thin film transistor (TFT) and fabrication method thereof for a liquid crystal display device.

Abstract: An Ta film for use in forming a source electrode and a drain electrode and an amorphous silicon film for use in forming an amorphous silicon semiconductor layer with impurity are continuously etched without setting an etching selectivity ratio. As a result, the source electrode, the drain electrode and the amorphous silicon semiconductor can be formed by a single etching process, and in the meantime, surface protrusions and recessions can be formed in a back channel region on the order of several hundreds of Å reflecting the crystal grain diameters of the Ta film for use in forming the source electrode and the drain electrode. The resulting protrusions and recessions offers an effect of suppressing an increase in OFF-state current value of the thin film transistor, and according to the foregoing method, the thin film transistor can be manufactured through a reduced number of steps at lower cost.

Abstract: There is provided a semiconductor device including a semiconductor circuit formed by semiconductor elements having an LDD structure which has high reproducibility, improves the stability of TFTs and provides high productivity and a method for manufacturing the same.

Abstract: A liquid crystal display device includes transparent pixel electrodes disposed at intersections of scanning signal lines and data lines, and a plurality of thin film transistors each of which is provided correspondingly to one of the pixel electrodes. Each of the transistors includes an output electrode connected to one of the pixel electrodes, a control electrode connected to one of the scanning signal lines, and an input electrode connected to one of the data lines. A first insulating film covers the scanning signal lines, and a semiconductor layer is interposed between the first insulating film and a portion of the data lines.

Abstract: An improved MOS-gated power device 300 with a substrate 101 having an upper layer 101a of doped monocrystalline silicon of a first conduction type that includes a doped well region 107 of a second conduction type. The substrate further includes at least one heavily doped source region 111 of the first conduction type disposed in a well region 107 at an upper surface of the upper layer, a gate region 106 having a conductive material 105 electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer 112 on the upper surface overlying the gate and source regions 114, and a heavily doped drain region of the first conduction type 115. The improvement includes body regions 301 containing heavily doped polysilicon of the second conduction type disposed in a well region 107 at the upper surface of the monocrystalline substrate.

Abstract: There is provided a semiconductor device including a semiconductor circuit formed by semiconductor elements having an LDD structure which has high reproducibility, improves the stability of TFTs and provides high productivity and a method for manufacturing the same. In order to achieve the object, the design of a second mask is appropriately determined in accordance with requirements associated with the circuit configuration to make it possible to form a desired LDD region on both sides or one side of the channel formation region of a TFT.

Abstract: A method and apparatus for reducing vertical leakage current in a high fill factor sensor array is described. Reduction of vertical leakage current is achieved by eliminating Schottky junction interfaces that occur between metal back contacts and intrinsic amorphous silicon layers. One method of eliminating the Schottky junction uses an extra wide region of N doped amorphous silicon to serve as a buffer between the metal back contact and the intrinsic amorphous silicon layer. Another method of eliminating the Schottky junction completely replaces the metal back contact and the N doped amorphous silicon layer with a substitute material such as N doped poly-silicon.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A method of manufacturing a polycrystalline silicon film having a particular field effect mobility is disclosed. A first polycrystalline silicon film is formed on a transparent insulation substrate. The surface of the silicon film is oxidized, and an amorphous silicon film is formed on the first polycrystalline silicon film and oxide layer. The amorphous silicon film is subjected to a solid phase growth process to be converted to a second polycrystalline silicon film. The field effect mobility of the second polycrystalline silicon film can be adjusted to a desired value by controlling the relative thicknesses of the first and second polycrystalline silicon films.

Abstract: In a method of etching an Al or Al alloy layer, an Al or Al alloy layer is formed on an underlying surface, the surface of the Al or Al alloy layer is processed with TMAH, a resist pattern is formed on the surface of the Al or Al alloy layer processed with TMAH, and by using the resist pattern as an etching mask, the Al or Al alloy layer is wet-etched.

Abstract: A thin-film transistor is provided, which has a simple configuration and improved off-characteristic, operational reliability, and fabrication yield. This transistor includes a substrate and a layered structure formed on the substrate. The layered structure includes a semiconductor film, a gate insulating film located on a first side of the semiconductor film to be overlapped with the semiconductor film, a gate electrode located on the gate insulating film on the first side of the semiconductor film to be selectively overlapped with the semiconductor film, a source electrode located on a second side of the semiconductor film to be electrically connected to the semiconductor film, and a drain electrode located on the second side of the semiconductor film to be electrically connected to the semiconductor film and to be apart from the source electrode. The semiconductor film has a back channel section between opposite ends of the source and drain regions.

Abstract: An additional high quality insulating layer is grown over the substrate after the formation of the gate electrode of a thin film transistor (TFT). The growth temperature of the insulating layer can be higher than conventional method and the insulating layer is more free of pin-holes. After the insulating layer in the thin oxide region of the TFT is etched away, conventional fabrication processes are followed. The dielectric of the thin film oxide region is the same as that of the conventional TFT; but the dielectric in the vicinity of the thin oxide region, the crossovers of the data lines and the scan lines, and the gate dielectric layer of the TFT are now composed of the high quality insulating layer. The TFT structure can improve the yield of fabrication by confining the channel region in the shadow of the gate electrode to reduce the leakage photo-current, and by reducing the steps at crossovers steps and interconnections to avoid open-circuit.

Abstract: Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: A thin film transistor of the present invention is composed of a transparent insulating substrate, a gate electrode formed on the transparent insulating substrate, a gate insulating film formed on the transparent insulating substrate including the gate electrode, a semiconductor active layer formed corresponding to the gate electrode through the gate insulating film, a source region and a drain region formed adjacent to the semiconductor active layer, a protective layer formed on the semiconductor active layer and having the side face inclined with respect to the transparent insulating substrate surface, a source electrode and a drain electrode formed respectively on the source region and the drain region, a part of which is extended onto the protective layer.

Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Abstract: A TFT of the present invention includes an insulating substrate, a first conductive film layer which is to be a gate electrode provided on the insulating substrate, a first insulating film layer which is to be a gate insulating film layer provided on the first conductive film layer, a non-doped semiconductor layer formed on the first insulating film layer, and a second conductive film layer which is to be a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor, wherein a junction is formed by implanting an n-type impurity in the source region of the semiconductor layer and the drain region of the semiconductor.

Abstract: A thin film semiconductor device comprising a substrate having an insulating surface, gate electrodes disposed on the insulating surface, gate insulating films disposed on upper portions of the gate electrodes, and thin film semiconductors disposed on the gate insulating films and including channel forming regions, source regions and drain regions. Two kinds of thin film semiconductor unit are disposed on the substrate. A first thin film semiconductor unit includes the thin film semiconductor of polycrystal, an insulating film covering an upper portion of the channel forming region, impurity semiconductor films doped with trivalent or pentavalent impurities and covering the source region and the drain region, and conductive films disposed on the impurity semiconductor films. A second thin film semiconductor unit includes the thin film semiconductor of amorphous, and other components similar to the first thin film semiconductor unit.

Abstract: On the polycrystal semiconductor film 3 formed on the insulating substrate 1, the source 6 and drain 7 in LDD structure having a low concentration region 4 and a high concentration region 5 are formed. The region 4 has a low impurity concentration, and the region 5 has a high impurity concentration. The length of the low concentration region 4 measured from the edge of gate insulating film 9 is not smaller than the average grain size of the polycrystal semiconductor film 3. The LCD device employing the TFT thus constructed is free from white spots (micro brighter spots) in a high temperature atmosphere.

Abstract: A high-performance thin-film semiconductor device and a simple fabrication method is provided. After a silicon film is deposited at approximately or less 580° C. and at a deposition rate of at least approximately 6 Å/minute, thermal oxidation is performed. This ensures an easy and simple fabrication of a high-performance thin-film semiconductor device. A thin-film semiconductor device capable of low-voltage and high-speed drive is provided. The short-channel type of a TFT circuit with an LDD structure reduces a threshold voltage, increases speed, restrains the power consumption and increases a breakdown voltage. The operational speeds of the thin-film semiconductor device is further increased by optimizing the maximum impurity concentration of an LDD portion, a source portion a drain portion, as well as optimizing the LDD length and the channel length. A display system is provided using these TFTs having drive signals at or below approximately the TTL level.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.degree. C.