Abstract: A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.

Abstract: According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.

Abstract: A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.

Abstract: A solid-state light source (SSLS) with an integrated short-circuit protection approach is described. A device can include a SSLS having an n-type semiconductor layer, a p-type semiconductor layer and a light generating structure formed there between. A field-effect transistor (FET) can be monolithically connected in series with the SSLS. The FET can have a saturation current that is greater than the normal operating current of the SSLS and less than a predetermined protection current threshold specified to protect the SSLS and the FET.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.

Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.

Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.

Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary semiconductor structure includes an insulation material layer having a top semiconductor layer having transistor regions formed on a top surface of the insulation material layer; isolation structures formed in the top semiconductor layer between adjacent transistor regions; a first dielectric layer formed over the top semiconductor layer; a first heat-conducting layer having a thermal conductivity higher than a thermal conductivity of the isolation structure and passing through the insulation material layer, the top semiconductor layer and the first dielectric layer; a second dielectric layer formed over the first dielectric layer; an interconnect structure formed in the second dielectric layer; and a bottom layer conductive via passing through the heat-conducting layer and a partial thickness of the second dielectric layer, and electrically connected with the interconnect structure.

Abstract: This is directed to systems and methods for coupling sections of an electronic device together. Sections of an electronic device can be coupled together via “knuckles.” The particular shape and structure of the knuckles can be based on various design considerations. For example, in some embodiments each section can function as an individual antenna. In this case, the knuckles can be designed in order to provide electrical isolation between the sections, thus allowing proper operation of the antennas. For example, the knuckles can be formed from a dielectric material, etc. As another design example, the knuckles can be designed in order to provide increased strength in areas of high strain, and/or to counteract torsional twisting in areas of high impact. As yet another design example, the knuckle can be designed in a manner that is aesthetically pleasing or which otherwise meets cosmetic requirements.

Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.

Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate including a semiconductor layer having a first main surface and a second main surface located opposite to the first main surface and an epitaxial layer formed on the first main surface, forming a trench having a sidewall passing through the epitaxial layer and reaching the semiconductor layer and a bottom portion continuing to the sidewall and located in the semiconductor layer, decreasing a thickness of the semiconductor layer by grinding the second main surface, forming an electrode layer on the ground second main surface, achieving ohmic contact between the second main surface and the electrode layer by laser annealing, and obtaining individual substrates by forming a cutting portion along the trench and dividing the semiconductor substrate along the cutting portion.

Abstract: A resistor structure composed of a metal liner is embedded within a MOL dielectric material and is located, at least in part, on a surface of a doped semiconductor material structure. The resistor structure is located on a same interconnect level of the semiconductor structure as a lower contact structure and both structures are embedded within the same MOL dielectric material. The metal liner that provides the resistor structure is composed of a metal or metal alloy having a higher resistivity than a metal or metal alloy that provides the contact metal of the lower contact structure.

Abstract: A nitride compound semiconductor has a substrate and a nitride compound semiconductor stack on the substrate. The nitride compound semiconductor stack includes a multilayer buffer layer, a channel layer on this multilayer buffer layer, and an electron supply layer on this channel layer. A recess extends from the surface of the electron supply layer through the channel layer and the multilayer buffer layer. A heat dissipation layer in this recess is contiguous to the multilayer buffer layer and the channel layer and has a higher thermal conductivity than the multilayer buffer layer.

Abstract: In a method of manufacturing a semiconductor device, sacrificial layer patterns extending in a first direction are formed on an etch target layer. Preliminary mask patterns are formed on opposite sidewall surfaces of each of the sacrificial layer patterns. A filling layer is formed to fill a space between the preliminary mask patterns. Upper portions of the preliminary mask patterns are etched to form a plurality of mask patterns. Each of the mask patterns is symmetric with respect to a plane passing a center point of each of the mask patterns in a second direction substantially perpendicular to the first direction and extending in the first direction. The sacrificial layer patterns and the filling layer are removed. The etch target layer is etched using the mask patterns as an etching mask to form a plurality of target layer patterns.

Abstract: A method for forming a stair-step structure in a substrate is provided, wherein the substrate has an organic mask, comprising at least one cycle, wherein each cycle comprises a) depositing a hardmask over the organic mask, b) trimming the organic mask, c) etching the substrate, d) trimming the organic mask, wherein there is no depositing a hardmask between etching the substrate and trimming the organic mask, e) etching the substrate, and f) repeating steps a-e a plurality of times forming the stair-step structure.

Abstract: A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided.

Abstract: A structured substrate configured for epitaxial growth of a semiconductor layer thereon is provided. Structures can be formed on a side of the structured substrate opposite that of the growth surface for the semiconductor layer. The structures can include cavities and/or pillars, which can be patterned, randomly distributed, and/or the like. The structures can be configured to modify one or more properties of the substrate material such that growth of a higher quality semiconductor layer can be obtained.

Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

Abstract: Embodiments relate to structures, systems and methods for more efficiently and effectively etching sacrificial and other layers in substrates and other structures. In embodiments, a substrate in which a sacrificial layer is to be removed to, e.g., form a cavity comprises an etch dispersion system comprising a trench, channel or other structure in which etch gas or another suitable gas, fluid or substance can flow to penetrate the substrate and remove the sacrificial layer. The trench, channel or other structure can be implemented along with openings or other apertures formed in the substrate, such as proximate one or more edges of the substrate, to even more quickly disperse etch gas or some other substance within the substrate.

Abstract: Causing a self-assemblable block copolymer (BCP) having first and second blocks to migrate from a region surrounding a lithography recess of the substrate and a dummy recess on the substrate to within the lithography recess and the dummy recess, causing the BCP to self-assemble into an ordered layer within the lithography recess, the layer having a first block domain and a second block domain, and selectively removing the first domain to form a lithography feature having the second domain within the lithography recess, wherein a width of the dummy recess is smaller than the minimum width required by the BCP to self-assemble, the dummy recess is within the region of the substrate surrounding the lithography recess from which the BCP is caused to migrate, and the width between portions of a side-wall of the lithography recess is greater than the width between portions of a side-wall of the dummy recess.

Abstract: An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer or printed circuit board forming a portion of the test circuit.

Abstract: Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si1-xGex SRB layer in the trenches, and growing a germanium based channel layer on the Si1-xGex SRB layer. In this example, the Si1-xGex SRB layer comprises a germanium content x that is within the range of 20% to 99%, and the SRB layer has a thickness less than 400 nm. The present disclosure also relates to an associated transistor device.

Abstract: A housing includes a main portion and at least one insulating portion. The main portion includes two portions, an inner surface and an outer surface opposite to the inner surface. The inner surface defines at least one groove. The outer surface defines at least one gap that is coupled to the at least one groove. The at least one insulating portion is corresponding to the at least one groove and each insulating portion is filled in one groove. The two portions of the main portion are positioned at two sides of the at least one gap and the two portions are insulated by the at least one gap and the at least one insulating portion.

Abstract: A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape.

Abstract: A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A MOS gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode. The p well regions are formed immediately below the gate pad electrode. The p channel regions are linked to the p well regions via extension portions. By making the width of the p well regions wider than the width of the p channel regions, it is possible to reduce a voltage drop caused by a reverse recovery current generated in a reverse recovery process of a body diode.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a trench in the dielectric layer, forming a first barrier layer in the trench, applying a thermal treatment to convert a first portion of the barrier layer to a second barrier layer, exposing the first conductive feature in the trench while a portion of the second barrier layer is disposed over the dielectric layer and forming a second conductive feature in the trench.

Abstract: A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.

Abstract: A method and structure for forming an array of LED devices is disclosed. The LED devices in accordance with embodiments of the invention may include a confined current injection area in which a current spreading layer protrudes away from a cladding layer in a pillar configuration so that the cladding layer is wider than the current spreading layer pillar.

Abstract: A marker pattern for enhancing resolution of a defect location along an axis in semiconductor defect analysis, and in particular, a marker pattern providing greater resolution in locating bit line defects using thermal laser stimulation methods such as OBIRCH. In an example, the marker pattern may consist of large markers, each having a set of associated small markers. Each of the small markers may be offset along an axis from each other. By identifying the small marker and its associated large marker which align with the defect, the bit line containing the defect may be more easily identified.

Abstract: A method for manufacturing an organic electroluminescent (EL) display panel through a printing process of applying a raw material liquid between banks disposed on a board, the raw material liquid containing an organic EL material. The method includes, before the printing process: a detection process of detecting a contaminant A present on the board; an information generation process of generating, when the contaminant A is detected, position information indicating a position of the contaminant A; and a resin application process of applying an inhibitory resin to at least one of the contaminant A and a region in the vicinity of the contaminant A based on the position information.

Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a circuit pattern at one surface, an insulation film formed over a back surface of the semiconductor substrate, a through silicon via (TSV) configured to pass through the semiconductor substrate and the insulation film, and an oxide film formed at a sidewall of the TSV and protruded from the back surface of the semiconductor substrate in a manner that the oxide film partially contacts the insulation film.

Abstract: A method of fabricating MEMS device includes forming a plurality of rounded edge trenches on a sacrificial layer over a carrier substrate. Then, formation of a polycrystalline silicon layer over the sacrificial layer to fill the trenches. A plurality of stoppers is defined by the trenches and protrudes from the polycrystalline silicon layer toward the carrier substrate Subsequently, a portion of the sacrificial layer is removed to define a recess between the polycrystalline silicon layer and a carrier substrate and expose the stoppers.

Abstract: A semiconductor chip includes a body having a frontside, a backside opposite the frontside, and sidewalls extending between the backside and frontside, at least a portion of each sidewall having a defined surface structure with hydrophobic characteristics to inhibit travel of a bonding material along the sidewalls during attachment of the semiconductor chip to a carrier with the bonding material.

Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.

Abstract: Described herein are methods, systems, and apparatuses to utilize a semiconductor optical amplifier (SOA) comprising a silicon layer including a silicon waveguide, a non-silicon layer disposed on the silicon layer and including a non-silicon waveguide, first and second mode transition region comprising tapers in the silicon waveguide and/or the non-silicon waveguide for exchanging light between the waveguide, and a plurality of regions disposed between the first and second mode transition regions comprising different cross-sectional areas of the silicon waveguide and the non-silicon waveguide such that confinement factors for the non-silicon waveguide in each of the plurality of regions differ.

Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.

Abstract: A method of dicing semiconductor devices includes depositing a continuous first layer over the substrate, such that the first layer imparts a compressive stress to the substrate, and etching grooves in the first layer to increase local stress at the grooves compared to stress at the remainder of the first layer located over the substrate. The method also includes generating a pattern of defects in the substrate with a laser beam, such that a location of the defects in the pattern of defects substantially corresponds to a location of at least some of the grooves in the in the first layer, and applying pressure to the substrate to dice the substrate along the grooves.

Abstract: A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect dielectric material containing a plurality of first conductive metal structures utilizing a titanium nitride hard mask portion located over a second region of the interconnect dielectric material as an etch mask. The titanium nitride hard mask portion located over the second region of the interconnect dielectric material is thereafter removed, again prior to air gap opening formation, utilizing another wet etch process. The wet etching processes are used instead of reactive ion etching.

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Abstract: A semiconductor device according to the present invention includes: a combination object; and a chip having a front surface opposed to a front surface of the combination object. The chip includes: a multi-level wiring structure provided in the front surface of the chip; a connection electrode provided in the multi-level wiring structure and electrically connected to the combination object; an alignment mark set provided in the multi-level wiring structure and electrically isolated from the connection electrode; and an electrically conductive film provided at a higher level than the alignment mark set in association with the multi-level wiring structure to cover the alignment mark set and electrically isolated from the connection electrode.

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Abstract: A method of fabricating a nitride substrate including preparing a growth substrate and disposing a sacrificial layer on the growth substrate. The sacrificial layer includes a nitride horizontal etching layer including an indium-based nitride and an upper nitride sacrificial layer formed on the nitride horizontal etching layer. The method of fabricating the nitride substrate also includes horizontally etching the nitride horizontal etching layer, forming at least one etching hole at least partially through the upper nitride sacrificial layer such that the at least one etching hole expands in the nitride horizontal etching layer in a horizontal direction during horizontal etching of the nitride horizontal etching layer, forming a nitride epitaxial layer on the upper nitride sacrificial layer by hydride vapor phase epitaxy (HVPE) and separating the nitride epitaxial layer from the growth substrate at the nitride horizontal etching layer.

Abstract: Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure.

Abstract: Methods and apparatus for forming structures to reduce wafer warpage. A method includes providing a semiconductor wafer having a plurality of integrated circuits; providing a photomask defining a plurality of cavities to be formed by an etch on a backside surface of the semiconductor wafer; defining structural support areas for the backside surface, the structural support areas being contiguous areas; providing areas on the photomask that correspond to the structural support areas, the structural support areas being areas that are not to be etched; using the photomask, performing an etch on the backside surface of the semiconductor wafer to form the cavities by removing semiconductor material from the backside surface of the semiconductor wafer; and the structural supports on the backside of the semiconductor wafer formed as areas that are not subjected to the etch. Additional methods and apparatus are also disclosed.

Abstract: Embodiments are directed to a polymeric print head useful for inkjet printing. The inkjet print head has an injection molded, polymeric ink-carrying portion that includes conductive particles. The print head also includes a plurality of inductor coils embedded in a inductive heating portion. The plurality of inductor coils are configured to generate a magnetic field that induces heat in the conductive particles. The print head includes a source of high frequency, low amperage alternating current that is configured to supply current to at least one of the plurality of inductor coils.

Abstract: Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

Abstract: The present invention provides a dicing die bond film in which peeling electrification hardly occurs and which has good tackiness and workability. The dicing die bond film of the present invention is a dicing die bond film including a dicing film and a thermosetting type die bond film provided thereon, wherein the thermosetting type die bond film contains conductive particles, the volume resistivity of the thermosetting type die bond film is 1×10?6 ?·cm or more and 1×10?3 ?·cm or less, and the tensile storage modulus of the thermosetting type die bond film at ?20° C. before thermal curing is 0.1 to 10 GPa.

Abstract: A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a plurality of additional parallel features perpendicularly intersecting the plurality of additional parallel features of the plurality over a substrate to define wells, each of the plurality of parallel features having substantially the same dimensions and relative spacing as each of the plurality of additional parallel features. A block copolymer material is formed in each of the wells. The block copolymer material is processed to form a patterned polymer material defining a pattern of openings. The pattern of openings is transferred to the substrate to form an array of openings in the substrate. A method of forming a semiconductor device structure, and a semiconductor device structure are also described.

Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.