Abstract: A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires.

Abstract: A method of making a diode and the diode wherein there is provided a substrate of p-type group II-VI semiconductor material and an electrically conductive material capable of forming an ohmic contact with the substrate is forced into the lattice of the substrate to create an n-type region in the substrate in contact with the material and forming an electrical contact to the p-type region of said substrate. The substrate is preferably HgCdTe and the electrically conductive material is preferably tungsten or tin coated tungsten or tungsten coated with a mercury amalgam.

Abstract: A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.

Abstract: A high frequency carrier is provided which comprises: (a) a planar ceramic substrate having first and second faces and (b) at least one feed-through extending from the first face to the second face. The at least one feed-through comprises a pedestal of doped semiconductor that is at least partially surrounded by a conductive metal layer. Also described is an electrical assembly, which comprises the above high frequency carrier and a metallized substrate. The first face of the carrier is attached to the metallized substrate such that the at least one feed-through is electrically connected to the metallized substrate. The electrical assembly can also comprise at least one electronic element (such as an electronic component or an electronic circuit) that is attached to the second face of the carrier such that the at least one electronic element is electrically connected to at least one feed-through.

Abstract: A semiconductor device having a single substrate made of silicon carbide; an epitaxial film made of AlxInyGa(1−x−y)N which is selectively formed on the single substrate; an amplifier section including a gate formed on the single substrate and a source layer and a drain layer which are formed within the single substrate; and another amplifier section formed on the epitaxial film.

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate, and establishing an electrical connection between the bond pad and the terminal.

Abstract: A wafer level package structure. The method of forming the wafer level package structure includes covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation layer. Next, a plurality of bonding pads is formed on the periphery of the silicon chip above the insulation layer. The bonding pads are formed such that each bonding pad is electrically connected to the terminal of an integrated circuit device. Thereafter, a passivation layer is deposited over the insulation layer and the bonding pads, and then openings that expose a portion of the bonding pad are formed. Subsequently, a metallic layer is formed on the sidewalls and the exposed bonding pad area. The metallic layer also extends over the passivation layer in the neighborhood of the opening and towards the edge of the wafer chip. Next, a layer of packaging material is deposited over the passivation layer. Finally, a metallic bump is formed over the exposed metallic layer lying above each opening.

Abstract: The present invention is about a method for filling an opening in an insulating layer in a fast and highly reliable way and can be used to fill openings such as trenches and via holes simultaneously. This method is based on the principle of reaction enhanced wetting and simultaneous seed layer formation. The idea is, in contrast to trying to avoid the TiAl3 formation, to use this reaction to its advantage for the creation of an ultra-thin continuous Al-containing seed layer. The latter allows a bottom to top fill during the subsequent Al-containing metal deposition. As a consequence, the filling process proceeds much faster and is production worthy.

Abstract: A lateral RF MOS device having a combined source connection structure is disclosed. The combined source connection structure utilizes a diffusion area and a conductive plug region. In one embodiment, the diffusion source area forms a contact region connecting the top surface of the semiconductor material to a highly conductive substrate of the lateral RF MOS transistor structure. In another embodiment, the diffusion source area is located completely within the epitaxial layer of the lateral RF MOS transistor structure. The conductive plug region makes a direct physical contact between a backside of the semiconductor material and the diffusion contact area.

Abstract: A microwave monolithic integrated circuit includes a coplanar waveguide (CPW) formed by a composite silicon structure constituted by a relatively high resistivity substrate, a first oxide layer on the upper surface thereof, a relatively thin silicon layer formed on the surface of the first oxide layer, and a very thin second oxide layer formed on the surface of the thin silicon layer. The silicon layer and the first oxide layer on which it is formed constitutes a silicon-on-insulator or SOI structure. A metallic signal line and ground planes are bonded to the surface of the second oxide layer. The zone of the thin silicon layer which extends between the ground planes is doped with an active impurity to produce high conductivity therein. As a result, the electric component of a quasi-TEM wave traversing the waveguide is substantially restricted to the thin silicon layer and does not penetrate to the underlying bulk silicon substrate.

Abstract: Buried layers are formed within a semiconductor. Metallic or insulating buried layers are produced several microns within a semiconductor substrate. The buried layer can confine current to the buried layer itself by using a conductive material to create the buried layer. The buried layer can also confine current to a specified area of the semiconductor, by using an insulating material inside of the buried layer or by leaving a created void within the material. The buried layer is useful in the construction of a semiconductor Vertical Cavity Laser (VCL). A buried isolation layer confines the current to a narrow active region increasing efficiency of the VCL. The buried layer is also useful in fabricating discrete devices, such as diodes, transistors, and photodetectors, as well as fabricating integrated circuits.

Abstract: A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, are applied.

Abstract: A process has been developed in which photoresist thinning at the edges of silicon chips, resulting from photoresist flowing from semiconductor chips, exhibiting features with raised topographies, to flat scribe regions, has been reduced. The reduction in photoresist flowing has been accomplished by creating a chessboard pattern of raised insulator and metal features, in the scribe line region, thus reducing the differences in topography between the scribe line and chip regions. The areas between the raised mesas, in the scribe line regions, are used for laser or optical endpoint detection of RIE processes.

Abstract: A high voltage silicon rectifier includes a substrate portion and an epitaxial mesa portion that is a frustrum of a pyramid with a substantially square cross section and side walls that make a forty five degree angle with the substrate portion. The mesa portion includes three germanium doped layers that introduce strain to speed up recombination of charge carriers.

Abstract: This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semi-conducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

Abstract: A large scale semiconductor apparatus is provided which includes at least one semiconductor chip having electrodes. The semiconductor chip is bonded on an electrically insulating circuit substrate on which electrically conductive interconnection films are separately formed, and a plurality of through holes are formed in the semiconductor chip so as to pierce the semiconductor chip in the direction of the thickness thereof. Electrically conductive bodies are formed in the through holes, respectively, wherein each of the conductive bodies electrically connects a predetermined electrode of the semiconductor chip to a predetermined interconnection film formed on the circuit substrate.

Abstract: A silicon-based monolithic microwave integrated circuit architecture is described. This architecture, called MICROX.TM., is a combination of silicon material growth and wafer processing technologies. A wafer is fabricated using a substrate of high resistivity silicon material. An insulating layer is formed in the wafer below the surface area of active silicon, preferably using the SIMOX process. A monolithic circuit is fabricated on the wafer. A ground plane electrode is formed on the back of the wafer. Direct current and rf capacitive losses under microstrip interconnections and transistor source and drain electrodes are thereby minimized. Reduction in the resistivity of the substrate material as a result of CMOS processing can be minimized by maintaining a shielding layer over the bottom surface of the wafer. Microstrip and airbridge connectors, salicide processing and nitride side wall spacing can be used to further enhance device performance.

Abstract: A semiconductor structure having an active layer formed over a first surface of a substrate. The semiconductor structure includes an electrode formed over a first surface of the structure. A conductive layer is formed over a second surface of the substrate. A conductor section passes through the semiconductor structure between the electrode and the conductive layer. The conductor section includes two conductive elements, one having a first end connected to the electrode and a second end terminating in the semiconductor structure; and the other conductive element having a first end connected to the conductive layer and a second end connected to the second end of the first conductive element. The second end terminates at, or in, an etch resistant layer disposed in the semiconductor structure between the active layer and the substrate. The method for forming the conductive sections includes etching the second via hole from the second surface of the substrate until the etching reaches an etch resistant layer.

Abstract: A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.

Abstract: A semiconductor device is made by etching a III-V compound semiconductor layer having a (100) surface using a mask having an opening defined by edges including at least one edge along an [011] direction of the layer so that the surface revealed by etching has a (111) orientation. An electrode is formed on the (111) surface by vacuum vapor deposition.

Abstract: A bipolar transistor in which a buried collector region, a base region and an emitter region are formed in a device forming region surrounded by an isolation region and in which a base contact electrode and a collector contact electrode are arranged in symmetry with each other, and a process for preparing the transistor. The collector contact electrode is formed through an opening formed in a portion of the isolation region for connection with the buried collector region. In this manner, the collision between the base region and the collector contact region may be avoided effectively.

Abstract: The present invention provides a semiconductor-type laminated ceramic capacitor with a grain boundary-insulated structure made of Sr.sub.(1-x) Ba.sub.x TiO.sub.3 as a main component, comprising the functions of a conventional capacitor which absorbs low voltage noises and high frequency noises, and a varistor when high voltage noises and electrostatic charges invade, wherein simultaneous sintering of the materials of ceramic capacitor together with the materials of inner electrodes was made possible in the manufacturing process. Besides a material to be made semiconductive is added to the main component of Sr.sub.(1-x) Ba.sub.x TiO.sub.3 with excess Ti, the materials of Mn-Si, which are converted to MnO.sub.2 and SiO.sub.2 in the sintering process, are also added to the main component.