Combined With Passivating Coating Patents (Class 257/626)
  • Patent number: 7968976
    Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventors: Nicole Meier Chang, George J. Korsh, Shafqat Ahmed, John M. Nugent, Ed Nabighian
  • Patent number: 7952173
    Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Mascolo, Gianfranco Cerofolini, Gianguido Rizzotto
  • Patent number: 7943529
    Abstract: A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: May 17, 2011
    Assignee: United Microelectronics Corp.
    Inventor: Jian-Bin Shiu
  • Patent number: 7935553
    Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 3, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Steven Radigan
  • Patent number: 7915173
    Abstract: A method for manufacturing a shallow trench isolation structure comprises etching a plurality of trenches into a silicon substrate. The trenches have an upright wall portion, a bottom floor portion, and a corner portion connecting the upright wall portion and the bottom floor portion. The method further comprises conformally depositing a dielectric layer into the trenches. The dielectric layer covers at least part of the upright wall portion, at least part of the bottom floor portion, and at least part of the corner portion. The method further comprises oxidizing the dielectric layer. A portion of the dielectric layer deposited over the corner portion is oxidized at a first oxidization rate, and a portion of the dielectric layer deposited over the upright wall portion is oxidized at a second oxidization rate. The first oxidization rate is less than the second oxidization rate. The method further comprises depositing an electrically insulating material into the trenches over the dielectric layer.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: March 29, 2011
    Assignee: Macronix International Co., Ltd.
    Inventor: Pei-Ren Jeng
  • Patent number: 7915712
    Abstract: A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide material. The germanium carbide material may be formed by microwave plasma-enhanced chemical vapor deposition by exposing the germanium material to a microwave-generated plasma that is formed from a carbon-containing source gas and hydrogen. The source gas may be a carbon-containing gas selected from the group consisting of ethylene, acetylene, ethanol, a hydrocarbon gas having from one to ten carbon atoms per molecule, and mixtures thereof. The resulting germanium carbide material may be amorphous and hydrogenated. The germanium material may be carburized without forming a distinct boundary at an interface between the germanium material and the germanium carbide material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the germanium carbide material, are also disclosed.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: March 29, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 7902639
    Abstract: Improved methods and articles providing conformal coatings for a variety of devices including electronic, semiconductor, and liquid crystal display devices. Peptide formulations which bind to nanoparticles and substrates, including substrates with trenches and vias, to provide conformal coverage as a seed layer. The seed layer can be further enhanced with use of metallic films deposited on the seed layer. Seed layers can be characterized by AFM measurements and improved seed layers provide for better enhancement layers including lower resistivity in the enhancement layer. Peptides can be identified by phage display.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: March 8, 2011
    Assignee: Siluria Technologies, Inc.
    Inventors: Philip E. Garrou, Michael R. Knapp, Hash Pakbaz, Florian Pschenitzka, Xina Quan, Michael A. Spaid
  • Patent number: 7898065
    Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7888779
    Abstract: There is provided a method of fabricating InGaAlN film on a silicon substrate, which comprises the following steps of forming a pattern structured having grooves and mesas on the silicon substrate, and depositing InGaAlN film on the surface of substrate, wherein the depth of the grooves is more than 6 nm, and the InGaAlN film formed on the mesas of both sides of the grooves are disconnected in the horizontal direction. The method may grow high quality, no crack and large area of InGaAlN film by simply treating the substrate. At the same time, there is also provided a method of fabricating InGaAlN light-emitting device by using the silicon substrate.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: February 15, 2011
    Assignee: Lattice Power (Jiangxi) Corporation
    Inventors: Fengyi Jiang, Wenqing Fang, Li Wang, Chunlan Mo, Hechu Liu, Maoxing Zhou
  • Patent number: 7872333
    Abstract: A layer system is described including a silicon layer and a passivation layer which is applied at least regionally to the silicon layer's surface, the passivation layer having a first, at least largely inorganic partial layer and a second partial layer, the second partial layer being made of an organic compound including silicon or containing such a material. In particular, the second partial layer is structured in the form of a “self-assembled monolayer.” Furthermore, a method is described for creating a passivation layer on a silicon layer, a first, inorganic partial layer being created on the silicon layer and a second partial layer, containing an organic compound including silicon or being made thereof, being created at least in certain areas on the first partial layer. Both partial layers form the passivation layer. The described layer system or the described method is particularly suited for creating self-supporting structures in silicon.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: January 18, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Franz Laermer, Lutz Mueller, Winfried Bernhard
  • Patent number: 7834437
    Abstract: The semiconductor package includes a plate having first via patterns formed on a center portion and second via patterns formed on edge portions; a connection wiring formed on a top surface of the plate to connect at least one first via patterns to at least one second via patterns; a plurality of passive elements formed on the top surface of the plate having a connection wiring formed thereon; a semiconductor chip having a plurality of bonding pads attached to a bottom surface of the plate and electrically connected to the first via patterns; and a plurality of external connection terminals each of which being attached to each of the second via pattern on the bottom surface of the plate.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: November 16, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Taek Yang
  • Patent number: 7763907
    Abstract: A semiconductor light emitting element includes: an {0001} n-type semiconductor substrate formed of a III-V semiconductor, which is in a range of 0° to 45° in inclination angle into a <1-100> direction, and which is in a range of 0° to 10° in inclination angle into a <11-20> direction; an n-type layer formed of a III-V semiconductor on the n-type semiconductor substrate; an n-type guide layer formed of a III-V semiconductor above the n-type layer; an active layer formed of a III-V semiconductor above the n-type guide layer; a p-type first guide layer formed of a III-V semiconductor above the active layer; a p-type contact layer formed of a III-V semiconductor above the p-type first guide layer; and an concavo-convex layer formed of a III-V semiconductor between the p-type first guide layer and the p-type contact layer.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: July 27, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Shinji Saito, Shinya Nunoue, Genichi Hatakoshi
  • Patent number: 7745908
    Abstract: A Semiconductor component that contains AlxGayIn1-x-yAszSb1-z, whereby the parameters x, y, and z are selected such that a bandgap of less than 350 meV is achieved, whereby it features a mesa-structuring and a passivation layer containing AlnGa1-nAsmSb1-m is applied at least partially on at least one lateral surface of the structuring, and the parameter n is selected in the range of 0.4 to 1 and the parameter m in the range of 0 to 1.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: June 29, 2010
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.
    Inventors: Frank Fuchs, Robert Rehm, Martin Walther
  • Patent number: 7701028
    Abstract: The pixel for use in an image sensor comprises a low-doped semiconductor substrate (A). On the substrate (A), an arrangement of a plurality of floating areas e.g., floating gates (FG2-FG6), is provided. Neighboring floating gates are electrically isolated from each other yet capacitively coupled to each other. By applying a voltage (V2-V1) to two contact areas (FG1, FG7), a lateral steplike electric field is generated. Photogenerated charge carriers move along the electric-field lines to the point of highest potential energy, where a floating diffusion (D) accumulate the photocharges. The charges accumulated in the various pixels are sequentially read out with a suitable circuit known from image-sensor literature, such as a source follower or a charge amplifier with row and column select mechanisms. The pixel of offers at the same time a large sensing area, a high photocharge-detection sensitivity and a high response speed without any static current consumption.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: April 20, 2010
    Assignee: MESA Imaging AG
    Inventors: Rolf Kaufmann, Michael Lehmann, Peter Seitz
  • Patent number: 7671377
    Abstract: Provided is a highly efficient silicon-based light emitting diode (LED) including a Distributed Bragg Reflector (DBR), an n-type doping layer, and a p-type substrate structure. The silicon-based LED includes: a substrate having a p-type mesa substrate structure; an active layer that is formed on the substrate and has a first surface and a second surface opposite the first surface; a first reflective layer facing the first surface of the active layer; a second reflective layer that is located on either side of the p-type substrate structure and faces the second surface of the active layer; an n-type doping layer sandwiched between the active layer and the first reflective layer; a first electrode electrically connected to the n-type doping layer; and a second electrode electrically connected to the p-type substrate structure.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: March 2, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Tae-Youb Kim, Nae-Man Park, Kyung-Hyun Kim, Gun-Yong Sung
  • Patent number: 7642626
    Abstract: A semiconductor device including a semiconductor structure defining a mesa having a mesa surface and mesa sidewalls, and first and second passivation layers. The first passivation layer may be on at least portions of the mesa sidewalls, at least a portion of the mesa surface may be free of the first passivation layer, and the first passivation layer may include a first material. The second passivation layer may be on the first passivation layer, at least a portion of the mesa surface may be free of the second passivation layer, and the second passivation layer may include a second material different than the first material.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 5, 2010
    Assignee: Cree, Inc.
    Inventors: Kevin Ward Haberern, Raymond Rosado, Michael John Bergman, David Todd Emerson
  • Patent number: 7629672
    Abstract: A semiconductor device is provided with a semiconductor substrate having circuit elements formed therein, and an insulating protective film formed on the semiconductor substrate. Hydroxyl groups (OH) are attached to a surface of the protective film. As a result, the contact angle between surface of the protective film and a water droplet is less than or equal to 40 degrees.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: December 8, 2009
    Assignees: Toyota Jidosha Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kanata, Shinichi Umekawa, Koji Terada, Yasushi Takahashi
  • Patent number: 7612414
    Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: November 3, 2009
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd.
    Inventors: Xiangdong Chen, Jun Jung Kim, Young Gun Ko, Jae-Eun Park, Haining S. Yang
  • Patent number: 7613219
    Abstract: Methods of forming a semiconductor device can include forming a semiconductor structure on a substrate, the semiconductor structure having mesa sidewalls and a mesa surface opposite the substrate. A contact layer can be formed on the mesa surface wherein the contact layer has sidewalls and a contact surface opposite the mesa surface and wherein the contact layer extends across substantially an entirety of the mesa surface. A passivation layer can be formed on the mesa sidewalls and on portions of the contact layer sidewalls adjacent the mesa surface, and the passivation layer can expose substantially an entirety of the contact surface of the contact layer. Related devices are also discussed.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: November 3, 2009
    Assignee: Cree, Inc.
    Inventors: Kevin Ward Haberern, Raymond Rosado, Michael John Bergman, David Todd Emerson
  • Patent number: 7602047
    Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: October 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Chai Kwon, Dong-Ho Lee, In-Young Lee
  • Publication number: 20090189257
    Abstract: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N?-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N?-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N?-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 30, 2009
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.
    Inventors: Katsuyuki SEKI, Akira Suzuki, Keita Odajima
  • Patent number: 7547949
    Abstract: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: June 16, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Publication number: 20090102023
    Abstract: One possible embodiment is a method for manufacturing a structure on a substrate which can be used in the manufacturing of a semiconductor device, including the steps of: forming a first structure on the substrate having at least one sidewall, forming at least one layer as a second structure selectively on the at least one sidewall of the first structure by an epitaxial technique, electroplating, selective silicon dioxide deposition, selective low pressure CVD or an atomic layer deposition technique. Furthermore semiconductor devices, uses of equipment and structures are covered.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 23, 2009
    Inventors: Stephan Wege, Chirstoph Noelscher, Alfred Kersch, Hocine Boubekeur, Christoph Ludwig
  • Patent number: 7514274
    Abstract: The present invention describes a test structure with a first set of features which is a subset of product features; and a second set of features adjacent to the first set of features, the second set occupying a smaller area than the first set and the second set being similar to the first set yet being distinguishable from surrounding structures.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Gary Cao, Alan Wong
  • Patent number: 7479687
    Abstract: Methods of forming a continuous seed layer in a high aspect via and its associated structures are described. Those methods comprise forming a recess in a substrate, forming a non-continuous metal layer within the recess, activating the non-continuous metal layer and a plurality of non-deposited regions within the recess, electrolessly depositing a seed layer on the activated non-continuous metal layer and the plurality of non-deposited regions within the recess, and electroplating a metal fill layer over the seed layer, to form a substantially void-free metal filled recess.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Thomas S. Dory, Kenneth N. Wong
  • Publication number: 20080251891
    Abstract: The layers of a semiconductor device have exposed edges. The layers that are susceptible to oxidation are protected from oxidation by coating them with a nitride passivation layer. The nitride passivation layer can be applied using plasma enhanced chemical vapor deposition (PECVD). A method of making a passivated sidewall semiconductor includes the steps of applying a nitride or other protective material over a wafer using PECVD or other appropriate deposition method.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 16, 2008
    Inventors: Yeong-Chang Chou, Peter S. Nam, Chun H. Lin, Augusto Gutierrez, Jeffrey Ming-Jer Yang, Michael Wojtowicz
  • Patent number: 7432582
    Abstract: A method of manufacturing a microelectronics device is provided, wherein the microelectronics device is formed on a substrate having a frontside and a backside. The method comprises forming a circuit element on the frontside of the substrate from a plurality of layers deposited on the frontside of the substrate, wherein the plurality of layers includes an intermediate electrical contact layer, and forming an interconnect structure after forming the electrical contact layer. The interconnect structure includes a contact pad formed on the backside of the substrate, and a through-substrate interconnect in electrical communication with the contact pad, wherein the through-substrate interconnect extends from the backside of the substrate to the electrical contact layer.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: October 7, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Diane Lai, Samson Berhane, Barry C. Snyder, Ronald A. Hellekson, Hubert Vander Plas
  • Patent number: 7423291
    Abstract: A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereby the characteristics of the thin-film transistor can be made stable.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: September 9, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Publication number: 20080135982
    Abstract: A semiconductor device including a semiconductor structure defining a mesa having a mesa surface and mesa sidewalls, and first and second passivation layers. The first passivation layer may be on at least portions of the mesa sidewalls, at least a portion of the mesa surface may be free of the first passivation layer, and the first passivation layer may include a first material. The second passivation layer may be on the first passivation layer, at least a portion of the mesa surface may be free of the second passivation layer, and the second passivation layer may include a second material different than the first material.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 12, 2008
    Inventors: Kevin Ward Haberern, Raymond Rosado, Michael John Bergman, David Todd Emerson
  • Patent number: 7345368
    Abstract: A semiconductor device has a semiconductor substrate having first and second surface, a first resin film formed on the first surface of the semiconductor substrate and a second resin film formed on the second surface of the semiconductor substrate. A projection electrode or an interconnection is formed on the first surface of the semiconductor substrate, the second resin film is made of low elastic resin which is capable of absorbing an impact applied to the second surface of the semiconductor substrate and the second resin film is thinner than the semiconductor substrate.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 18, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 7245002
    Abstract: A semiconductor substrate which effectively prevents a chipping phenomenon, wherein the outer peripheral extremity of the insulation layer is located between the outer peripheral extremity of the semiconductor layer and the outer peripheral extremity of the support member, and wherein the semiconductor layer and the insulation layer produce a stepped profile.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: July 17, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yutaka Akino, Tadashi Atoji
  • Patent number: 7193301
    Abstract: A plurality of semiconductor chips (14) each having a first main surface (14b) formed with electrode pads (21) and a second main surface (14c) opposite to the first main surface are respectively mounted on a chip mounting surface (12a) larger in area than the second main surface, of a wafer-shaped mounting substrate (12) at equal intervals so as to extend along first and second trenches (18a, 18b) defined in the chip mounting surface with these trenches as target lines. Thereafter, solder balls (25) electrically connected to the electrode pads of the semiconductor chips are disposed on their corresponding wiring patterns 34 that extend from above first regions (100) located above the semiconductor chips, of a surface region of an encapsulating layer (32) covering the semiconductor chips to above second regions (200) that surround the first regions. Afterwards, the encapsulating layer and the mounting substrate are cut and thereby fractionized into semiconductor devices each having a fan-out structure.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: March 20, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tadashi Yamaguchi
  • Patent number: 7187058
    Abstract: The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an amorphous passivation layer (70) arranged at least in sections on a surface (101) of the semiconductor body (100), the following holding true for the minimum Ds,min of an interface state density Ds at the junction between the passivation layer (70) and the semiconductor body (100): D s , min ? N S , Bd E g where NS,Bd is the breakdown charge and Eg is the band gap of the semiconductor material used for the semiconductor body (100).
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 6, 2007
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 7166861
    Abstract: The present invention provides a thin-film transistor that is formed by using a patterning method capable of forming a semiconductor channel layer in sub-micron order and a method for manufacturing thereof that provides a thin-film transistor with a larger area, and suitable for mass production. These objects are achieved by a thin-film transistor formed on a substrate 1 with a finely processed concavoconvex surface 2, in which a source electrode and a drain electrode are formed on adjacent convex portions of the concavoconvex surface 2, with a channel and a gate being formed on a concave area between the convex portions. A gate electrode 5, a gate insulating film 6 and a semiconductor channel layer 7 are laminated in this order on the concave area from the bottom surface of the concave portion toward the top surface.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: January 23, 2007
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Wataru Saito, Yudai Yamashita
  • Patent number: 7112545
    Abstract: The surface of a semiconductor material, e.g., gallium arsenide, is passivated by irradiating the surface with ultra-short laser pulses, until a stable passive surface is achieved. The passive surface so prepared is devoid of a superficial oxide layer.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: September 26, 2006
    Assignee: The Board of Trustees of the University of Arkansas
    Inventors: Tarak A. Railkar, Ajay P. Malshe, William D. Brown
  • Patent number: 7054469
    Abstract: A conductor layer is patterned into flat portions, for example of a fingerprint sensor that effects capacitive measurement. The conductor layer is fragmented in a lattice-like manner by cutouts so that an applied passivation layer rests on a base layer that is present beneath the conductor layer. The interlaminar shear strength of the passivation is increased in this way.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: May 30, 2006
    Assignee: Infineon Technologies AG
    Inventors: Siegfried Röhl, Paul-Werner Von Basse, Thomas Scheiter, Thorsten Sasse, Heinz Opolka
  • Patent number: 6992325
    Abstract: An active matrix organic electroluminescence display device capable of maintaining the brightness of the organic light emitting diode. The active matrix organic electroluminescence display device comprises a thin film transistor and an organic light emitting diode. By improving the structure of the passivation layer of the thin film transistor to reduce the leakage current occurring in the TFT, the brightness of the organic light emitting diode can be stably maintained.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: January 31, 2006
    Assignee: Au Optronics Corp.
    Inventor: Wei-Pang Huang
  • Patent number: 6972477
    Abstract: To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and second conductive patterns 11B, onto which comparatively thick second circuit elements 12B are mounted, are formed thinly. Also, fine wiring parts may be formed using the thinly formed second conductive patterns 12B. Thus even in the case where thick circuit elements are incorporated, by affixing such circuit elements onto the thinly formed second conductive patterns 11B, the total thickness can be made thin. Thinning of circuit device 10 as a whole can thus be accomplished.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: December 6, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
  • Patent number: 6936868
    Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: August 30, 2005
    Assignee: Anritsu Corporation
    Inventors: Jun Hiraoka, Kazuo Mizuno, Yuichi Sasaki
  • Patent number: 6924197
    Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: August 2, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Ronald A. Weimer
  • Patent number: 6921937
    Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: July 26, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Ronald A. Weimer
  • Patent number: 6906401
    Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Natalie B. Feilchenfeld, Qizhi Liu, Andreas D. Stricker
  • Patent number: 6900523
    Abstract: The termination of a MOSgated device is formed by a trench bevel which surrounds the active device area. The trench bevel has flat walls which extend into and through the epitaxial layer containing the active area which has a lateral extend equal to or less than the thickness of the epitaxial layer. The surface of the bevel is coated with a resistive film, preferably, an amorphous silicon which connects the device source to the device drain to cause the electric field in the epitaxial silicon to the linearly distributed over the length of the bevel.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: May 31, 2005
    Assignee: International Rectifier Corporation
    Inventor: Zhijun Qu
  • Patent number: 6888171
    Abstract: A semi-conductor light emitting diode includes closely spaced n and p electrodes formed on the same side of a substrate to form an LED with a small foot-print. A semi-transparent U shaped p contact layer is formed along three sides of the top surface of the underlying window layer. The p electrode is formed on the p contact layer centered on the closed end of the U shaped layer. An n contact layer is formed on an n cladding layer and centered in the open end of the U of the p contact layer. The n electrode is formed on the n contact layer. The n and p electrodes are electrically isolated from one another by either a trench or an insulator, situated between the electrodes.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: May 3, 2005
    Assignee: Dallan Luming Science & Technology Group Co., Ltd.
    Inventors: Heng Liu, Changhua Chen
  • Patent number: 6882031
    Abstract: A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include silicon nitride, prevents hydrogen species from escaping therethrough as high temperature processes are subsequently conducted. Once high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Semiconductor device structures that have been passivated in such a manner are also disclosed.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: April 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Ronald A. Weimer, Fernando Gonzalez
  • Patent number: 6883159
    Abstract: A photomask and method of patterning a photosensitive layer using a photomask, the photomask including a substrate and a film coupled to substrate. The film is etched with a phase shifted assist feature, a low aspect ratio assist feature or phase shifted low aspect primary features.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: April 19, 2005
    Assignee: Intel Corporation
    Inventors: Richard Schenker, Gary Allen
  • Patent number: 6879020
    Abstract: Via-shaped copper interconnect lines (2) buried in an interlayer insulating film (8) are connected to gate interconnect lines (1) in the lowermost layer. A copper interconnect line (6) of a shield ring (5) is buried in the interlayer insulating film (8), closer to outside than the copper interconnect lines (2). A silicon nitride film (9) is provided on the via-shaped copper interconnect lines (2), on the copper interconnect line (6) of the shield ring (5), and on the interlayer insulating film (8). Provided on the silicon nitride film (9) is a silicon oxide film (10) which holds therein a fuse line (3) for connecting different ones of copper interconnect lines (2). The silicon oxide film (10) is also provided on the upper surfaces of the fuse line (3) and the aluminum interconnect line (7). A silicon nitride film (11) is provided on the silicon oxide film (10). The silicon nitride film (11) defined over the fuse line (3) is removed, thereby creating an opening (4).
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: April 12, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Yasuo Yamaguchi
  • Patent number: 6876062
    Abstract: An apparatus and method for protecting die corners in a semiconductor integrated circuit. At least one irregular seal ring having two sides can be configured, wherein the irregular seal ring is located at a corner of a die utilized in fabricating a semiconductor integrated circuit. A dummy configuration for stress relief can then be arranged, wherein the dummy configuration is located at the two sides of the at least one irregular seal ring, thereby protecting the corner of the die against thermal stress and the semiconductor integrated circuit against moisture and metallic impurities. The irregular seal ring can be configured to generally comprise a non-rectangular seal ring. The irregular seal preferably comprises an octangular seal ring.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: April 5, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Tze-Liang Lee, Shih-Chung Chen, Ming-Soah Liang, Chen-Hua Yu
  • Patent number: 6828220
    Abstract: A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: December 7, 2004
    Assignee: ChipPAC, Inc.
    Inventors: Rajendra D. Pendse, Marcos Karnezos, Walter A. Bush, Jr.
  • Patent number: 6825547
    Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate and establishing an electrical connection between the bond pad and the terminal.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: November 30, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Larry D. Kinsman, Walter L. Moden