With Specified Crystal Plane Or Axis Patents (Class 257/627)
  • Publication number: 20140264777
    Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
  • Publication number: 20140264439
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least a first N-type germanium (Ge) structure and at least a first P-type Ge structure. The first N-type Ge structure is formed on the substrate and has two end parts and at least a first central part bonded between the two end parts thereof. The first central part is floated over the substrate, and a side surface of the first central part is a {111} Ge crystallographic surface. The first P-type Ge structure is formed on the substrate and has two end parts and at least a second central part bonded between the two end parts thereof. The side surface of the second central part is a {110} Ge crystallographic surface.
    Type: Application
    Filed: August 27, 2013
    Publication date: September 18, 2014
    Applicant: National Applied Research Laboratories
    Inventors: Chee-Wee Liu, Yen-Ting Chen
  • Patent number: 8829617
    Abstract: A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian S. Haran, Sanjay Mehta, Shom Ponoth, Ravikumar Ramachandran, Stefan Schmitz, Theodorus E. Standaert
  • Patent number: 8829658
    Abstract: A method of manufacturing a nitride substrate includes the following steps. Firstly, a nitride crystal is grown. Then, the nitride substrate including a front surface is cut from the nitride crystal. In the step of cutting, the nitride substrate is cut such that an off angle formed between an axis orthogonal to the front surface and an m-axis or an a-axis is greater than zero. When the nitride crystal is grown in a c-axis direction, in the step of cutting, the nitride substrate is cut from the nitride crystal along a flat plane which passes through a front surface and a rear surface of the nitride crystal and does not pass through a line segment connecting a center of a radius of curvature of the front surface with a center of a radius of curvature of the rear surface of the nitride crystal.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Satoshi Arakawa, Michimasa Miyanaga, Takashi Sakurada, Yoshiyuki Yamamoto, Hideaki Nakahata
  • Patent number: 8815710
    Abstract: Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode).
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: August 26, 2014
    Assignee: Sumco Corporation
    Inventors: Masayuki Ishibashi, Shinji Nakahara, Tetsuro Iwashita
  • Patent number: 8809852
    Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Patent number: 8810009
    Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semiconductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: August 19, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Seth A. Fortuna
  • Patent number: 8803294
    Abstract: A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Shin Harada, Keiji Wada, Toru Hiyoshi
  • Patent number: 8796721
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 8786052
    Abstract: A nitride semiconductor crystal producing method, a nitride semiconductor epitaxial wafer, and a nitride semiconductor freestanding substrate, by which it is possible to suppress the occurrence of cracking in the nitride semiconductor crystal and to ensure the enhancement of the yield of the nitride semiconductor crystal. The nitride semiconductor crystal producing method includes growing a nitride semiconductor crystal over a seed crystal substrate, while applying an etching action to an outer end of the seed crystal substrate during the growing of the nitride semiconductor crystal.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: July 22, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Hajime Fujikura, Taichiroo Konno, Yuichi Oshima
  • Patent number: 8786057
    Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: July 22, 2014
    Assignee: Synopsys, Inc.
    Inventors: Tsu-Jae King, Victor Moroz
  • Patent number: 8779437
    Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8779440
    Abstract: Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventor: Martin Henning Albrecht Vielemeyer
  • Publication number: 20140191330
    Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.
    Type: Application
    Filed: January 9, 2013
    Publication date: July 10, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8771552
    Abstract: A group III nitride crystal substrate is provided in which a uniform distortion at a surface layer of the crystal substrate represented by a value of |d1 ?d2 |/d2 obtained from a plane spacing d1 at the X-ray penetration depth of 0.3 ?m and a plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 1.9 ×10?3, and the main surface has a plane orientation inclined in the <10-10> direction at an angle equal to or greater than 10° and equal to or smaller than 80° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 8, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Yusuke Yoshizumi
  • Patent number: 8709923
    Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 29, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8710555
    Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang, Junga Choi
  • Patent number: 8704340
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal gallium nitride. In each of the first substrate and the second substrate, one surface is a (0001) Ga-face and an opposite surface is a (000-1) N-face. The first substrate and the second substrate are bonded to each other in a state where the (000-1) N-face of the first substrate and the (000-1) N-face of the second substrate face each other, and the (0001) Ga-face of the first substrate and the (0001) Ga-face of the second substrate are exposed.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 22, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • Publication number: 20140103497
    Abstract: A production process for a micromechanical component includes at least partially structuring at least one structure from at least one monocrystalline silicon layer by at least performing a crystal-orientation-dependent etching step on an upper side of the silicon layer with a given (110) surface orientation of the silicon layer. For the at least partial structuring of the at least one structure, at least one crystal-orientation-independent etching step is additionally performed on the upper side of the silicon layer with the given (110) surface orientation of the silicon layer.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 17, 2014
    Applicant: Robert Bosch GmbH
    Inventors: Friedjof Heuck, Christoph Schelling, Mirko Hattass, Benjamin Schmidt
  • Patent number: 8698284
    Abstract: A nitride-based semiconductor substrate may includes a plurality of hollow member patterns arranged on a substrate, a nitride-based seed layer formed on the substrate between the plurality of hollow member patterns, and a nitride-based buffer layer on the nitride-based seed layer so as to cover the plurality of hollow member patterns, wherein the plurality of hollow member patterns contact the substrate in a first direction and both ends of each of the plurality of hollow member patterns are open in the first direction.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Moon Lee
  • Patent number: 8698255
    Abstract: A simple and cost-effective form of implementing a semiconductor component having a micromechanical microphone structure, including an acoustically active diaphragm as a deflectable electrode of a microphone capacitor, a stationary, acoustically permeable counterelement as a counter electrode of the microphone capacitor, and means for applying a charging voltage between the deflectable electrode and the counter electrode of the microphone capacitor. In order to not impair the functionality of this semiconductor component, even during overload situations in which contact occurs between the diaphragm and the counter electrode, the deflectable electrode and the counter electrode of the microphone capacitor are counter-doped, at least in places, so that they form a diode in the event of contact. In addition, the polarity of the charging voltage between the deflectable electrode and the counter electrode is such that the diode is switched in the blocking direction.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: April 15, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Frank Reichenbach, Arnim Hoechst, Thomas Buck
  • Patent number: 8686398
    Abstract: A semiconductor light emitting device includes a first conductivity-type first semiconductor layer, a second conductivity-type second semiconductor layer, a semiconductor light emitting layer, and first and second electrodes. The semiconductor light emitting layer is provided between the first semiconductor layer and the second semiconductor layer, and includes a multiple quantum well structure. The quantum well structure includes well layers and barrier layers each laminated alternately, each of the well layers being not less than 6 nm and not more than 10 nm. The first and second electrodes are electrically connected to the first and second semiconductor layers such that current flows in a direction substantially vertical to the main surface.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tanaka, Yoko Motojima
  • Patent number: 8686434
    Abstract: There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1021 cm?3.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: April 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Takeyoshi Masuda, Keiji Wada, Masato Tsumori
  • Patent number: 8686561
    Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Ryou Kato
  • Patent number: 8674438
    Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Bin Yang, Man Fai Ng
  • Patent number: 8664737
    Abstract: A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: March 4, 2014
    Assignee: Selexel, Inc.
    Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi
  • Patent number: 8653568
    Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka
  • Patent number: 8633090
    Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.
    Type: Grant
    Filed: July 10, 2010
    Date of Patent: January 21, 2014
    Assignees: Shanghai Simgui Technology Co., Ltd., Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xiang Wang, Xing Wei, Miao Zhang, Chenglu Lin, Xi Wang
  • Patent number: 8629065
    Abstract: A method of growing planar non-polar m-plane III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE. Various alternative methods are disclosed.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: January 14, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Philippe Spiberg, Hussein S. El-Ghoroury, Alexander Usikov, Alexander Syrkin, Bernard Scanlan, Vitali Soukhoveev
  • Patent number: 8618639
    Abstract: According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8614121
    Abstract: Back gate triggered silicon controlled rectifiers (SCR) and methods of manufacture are disclosed. The method includes forming a first diffusion type and a second diffusion type in a semiconductor layer of a silicon on insulator (SOI) substrate. The method further includes forming a back gate of a first diffusion type in a substrate under an insulator layer of the SOI substrate. The method further includes forming raised diffusion regions of a first dopant type and a second dopant type, adjacent to the second diffusion type and the first diffusion type, respectively. The back gate is formed to cover the second diffusion type, the first diffusion type and the second dopant type of the raised diffusion regions.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gauthier, Jr., Junjun Li
  • Publication number: 20130320294
    Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
    Type: Application
    Filed: December 23, 2011
    Publication date: December 5, 2013
    Inventors: Annalisa Cappellani, Peter G. Tolchinsky, Kelin J. Kuhn, Glenn A. Glass, Van H. Le
  • Patent number: 8569801
    Abstract: A three-dimensional CMOS circuit having at least a first N-conductivity field-effect transistor and a second P-conductivity field-effect transistor respectively formed on first and second crystalline substrates. The first field-effect transistor is oriented, in the first substrate, with a first secondary crystallographic orientation. The second field-effect transistor is oriented, in the second substrate, with a second secondary crystallographic orientation. The orientations of the first and second transistors form a different angle from the angle formed, in one of the substrates, by the first and second secondary crystallographic directions. The first and second substrates are assembled vertically.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: October 29, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Benjamin Vincent
  • Publication number: 20130277809
    Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.
    Type: Application
    Filed: November 10, 2011
    Publication date: October 24, 2013
    Applicant: SILTRONIC AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo
  • Patent number: 8541869
    Abstract: A III-nitride edge-emitting laser diode is formed on a surface of a III-nitride substrate having a semipolar orientation, wherein the III-nitride substrate is cleaved by creating a cleavage line along a direction substantially perpendicular to a nonpolar orientation of the III-nitride substrate, and then applying force along the cleavage line to create one or more cleaved facets of the III-nitride substrate, wherein the cleaved facets have an m-plane or a-plane orientation.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: September 24, 2013
    Assignee: The Regents of the University of California
    Inventors: Shuji Nakamura, James S. Speck, Steven P. DenBaars, Anurag Tyagi
  • Patent number: 8531010
    Abstract: A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first <100> direction.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Kiyonori Oyu, Kazuhiro Nojima
  • Patent number: 8519416
    Abstract: A nitride-based semiconductor light-emitting device capable of suppressing reduction of characteristics and a yield and method of fabricating the same is described. The method of fabricating includes the steps of forming a groove portion on a nitride-based semiconductor substrate by selectively removing a prescribed region of a second region of the nitride-based semiconductor substrate other than a first region corresponding to a light-emitting portion of a nitride-based semiconductor layer up to a prescribed depth and forming the nitride-based semiconductor layer having a different composition from the nitride-based semiconductor substrate on the first region and the groove portion of the nitride-based semiconductor substrate.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: August 27, 2013
    Assignee: Future Light, LLC
    Inventors: Takashi Kano, Masayuki Hata, Yasuhiko Nomura
  • Patent number: 8513779
    Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
  • Patent number: 8513676
    Abstract: A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than ?3° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm?3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 20, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Toru Hiyoshi, Keiji Wada, Takeyoshi Masuda
  • Patent number: 8507921
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 13, 2013
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • Patent number: 8502354
    Abstract: A break pattern of a silicon wafer includes a line to be cut which is set in the silicon wafer assuming a surface as a (110) face in a surface direction of a first (111) face perpendicular to the (110) face; and through holes which are provided in a plurality of rows on the line to be cut, wherein each of the through holes has a first (111) face, a second (111) face which intersects the first (111) face, and a third (111) face which intersects the second (111) face and the first (111) face, an intersecting point with end edges of the second (111) face and the third (111) face is assumed as a point closest to the adjacent through holes.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: August 6, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Isamu Togashi
  • Publication number: 20130193448
    Abstract: A patterned substrate is provided, including: a substrate having a (0001) crystal plane and a plurality of alternatively arranged recess structures therein, thereby forming a plurality of alternatively arranged top surfaces; and a dielectric barrier layer covering the bottom surface and/or the sidewalls of the recess structures. Each of the alternatively arranged recess structures includes a bottom surface and a plurality of sidewalls surrounding the bottom surface.
    Type: Application
    Filed: January 28, 2013
    Publication date: August 1, 2013
    Applicant: LEXTAR ELECTRONICS CORPORATION
    Inventor: Lextar Electronics Corporation
  • Patent number: 8497532
    Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: July 30, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka
  • Patent number: 8487327
    Abstract: A III-nitride semiconductor device has a support base comprised of a III-nitride semiconductor and having a primary surface extending along a first reference plane perpendicular to a reference axis inclined at a predetermined angle with respect to a c-axis of the III-nitride semiconductor, and an epitaxial semiconductor region provided on the primary surface of the support base. The epitaxial semiconductor region includes GaN-based semiconductor layers. The reference axis is inclined at a first angle from the c-axis of the III-nitride semiconductor toward a first crystal axis, either the m-axis or a-axis. The reference axis is inclined at a second angle from the c-axis of the III-nitride semiconductor toward a second crystal axis, the other of the m-axis and a-axis. Morphology of an outermost surface of the epitaxial semiconductor region includes a plurality of pits. A pit density of the pits is not more than 5×104 cm?2.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: July 16, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yohei Enya, Yusuke Yoshizumi, Takashi Kyono, Takamichi Sumitomo, Katsushi Akita, Masaki Ueno, Takao Nakamura
  • Publication number: 20130153026
    Abstract: Provided is a substrate for a solar cell, wherein a flat chamfered portion is formed on one corner of a silicon substrate having a square shape in a planar view, or a notch is formed on the corner or close to the corner. This invention makes it possible to easily check the position of the substrate and determine the direction of the substrate in a solar cell manufacturing step, and suppresses failures generated due to the direction of the substrate.
    Type: Application
    Filed: August 16, 2011
    Publication date: June 20, 2013
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hideo Ooiwa, Takenori Watabe, Hiroyuki Otsuka, Kazuo Hara
  • Patent number: 8466538
    Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: June 18, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
  • Patent number: 8441045
    Abstract: The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate.
    Type: Grant
    Filed: February 27, 2011
    Date of Patent: May 14, 2013
    Assignee: The Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Haizhou Yin, Zhijiong Luo
  • Patent number: 8441108
    Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes a Zn layer 32 and a metal layer 34 provided on the Zn layer 32. The Zn layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: May 14, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuaki Oya, Toshiya Yokogawa, Atsushi Yamada, Akihiro Isozaki
  • Patent number: 8436366
    Abstract: A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than ?40 ?m and not greater than ?5 ?m, and a value for warp at the main surface being not smaller than 5 ?m and not greater than 40 ?m. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: May 7, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Makoto Sasaki, Takeyoshi Masuda
  • Patent number: RE44215
    Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: May 14, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Yamamoto, Hidetoshi Fujimoto, Yoshihiro Kokubun, Masayuki Ishikawa, Shinji Saito, Yukie Nishikawa, John Rennie