With Specified Crystal Plane Or Axis Patents (Class 257/627)
  • Publication number: 20130082357
    Abstract: A base layer of a semiconductor material is formed with a naturally textured surface. The base layer may be incorporated within a photovoltaic structure. A controlled spalling technique, in which substrate fracture is propagated in a selected direction to cause the formation of facets, is employed. Spalling in the [110] directions of a (001) silicon substrate results in the formation of such facets of the resulting base layer, providing a natural surface texture.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 4, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ibrahim Alhomoudi, Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 8404042
    Abstract: III-nitride crystal composites are made up of especially processed crystal slices cut from III-nitride bulk crystal having, ordinarily, a {0001} major surface and disposed adjoining each other sideways, and of III-nitride crystal epitaxially on the bulk-crystal slices. The slices are arranged in such a way that their major surfaces parallel each other, but are not necessarily flush with each other, and so that the [0001] directions in the slices are oriented in the same way.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: March 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8399915
    Abstract: Provided is a semiconductor device which can reduce on-resistance by improving hole mobility of a channel region. A trench gate type MOSFET (semiconductor device) is provided with a p+-type silicon substrate whose crystal plane of a main surface is a (110) plane; an epitaxial layer formed on the silicon substrate; a trench, which is formed on the epitaxial layer and includes a side wall parallel to the thickness direction (Z direction) of the silicon substrate; a gate electrode formed inside the trench through a gate dielectric film; an n-type channel region formed along the side wall of the trench; and a p+-type source region and a p?-type drain region which are formed to sandwich the channel region in the thickness direction (Z direction) of the silicon substrate. The trench is formed to have the crystal plane of the side wall as a (110) plane.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: March 19, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Publication number: 20130064261
    Abstract: An edge emitting solid state laser and method. The laser comprises at least one AlInGaN active layer on a bulk GaN substrate with a non-polar or semi-polar orientation. The edges of the laser comprise {1 1?2±6} facets. The laser has high gain, low threshold currents, capability for extended operation at high current densities, and can be manufactured with improved yield. The laser is useful for optical data storage, projection displays, and as a source for general illumination.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 14, 2013
    Applicant: Soraa, Inc.
    Inventors: Rajat Sharma, Eric M. Hall, Christiane Poblenz, Mark P. D'Evelyn
  • Publication number: 20130062738
    Abstract: To form a single crystal silicon membrane with a suspension layer, a single crystal silicon substrate with crystal orientation <111> is prepared. A doped layer is formed on the top surface of the single crystal silicon substrate. Multiple main etching windows are formed through the doped layer. A cavity is formed through the single crystal silicon substrate by anisotropic etching. The doped layer is above the cavity to form a suspension layer. If two electrode layers are formed on the two ends of the suspension layer, a micro-heater is constructed. The main etching windows extend in parallel to a crystal plane {111}. By both the single crystal structure and different impurity concentrations of the single crystal silicon substrate, the single crystal silicon substrate has a higher etch selectivity. When a large-area cavity is formed, the thickness of the suspension layer is still controllable.
    Type: Application
    Filed: May 29, 2012
    Publication date: March 14, 2013
    Inventor: Chung-Nan Chen
  • Publication number: 20130062739
    Abstract: A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group.
    Type: Application
    Filed: February 8, 2011
    Publication date: March 14, 2013
    Applicant: Takafumi YAO
    Inventors: Takafumi Yao, Hyun-Jae Lee, Katsushi Fujii
  • Patent number: 8395218
    Abstract: The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: March 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Dong-Won Kim, Kyoung-Hwan Yeo
  • Patent number: 8384183
    Abstract: An integrated circuit and a method of making the integrated circuit provide a Hall effect element having a germanium Hall plate. The germanium Hall plate provides an increased electron mobility compared with silicon, and therefore, a more sensitive Hall effect element.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 26, 2013
    Assignee: Allegro Microsystems, Inc.
    Inventors: Harianto Wong, William P. Taylor, Ravi Vig
  • Patent number: 8378463
    Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001>direction predominantly towards either the <11 20> or the <1 100> family of directions. For a <11 20> off-cut substrate, a laser diode cavity may be oriented along the <1 100> direction parallel to lattice surface steps of the substrate in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For a <1 100> off-cut substrate, the laser diode cavity may be oriented along the <1 100> direction orthogonal to lattice surface steps of the substrate in order to provide a cleaved laser facet that is aligned with the surface lattice steps.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: February 19, 2013
    Assignee: Cree, Inc.
    Inventors: George R. Brandes, Robert P. Vaudo, Xueping Xu
  • Patent number: 8368147
    Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: February 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan, Hsueh-Chang Sung, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
  • Patent number: 8368183
    Abstract: A nitride semiconductor device is provided that prevents development of cracks, that has nitride semiconductor thin films with uniform thicknesses and good growth surface flatness, and is thus consistent in characteristics, and that can be fabricated at a satisfactory yield. In this nitride semiconductor device, the nitride semiconductor thin films are grown on a substrate having an off-angle between a direction normal to the surface of ridges and the crystal direction <0001>. This helps either reduce or intentionally promote diffusion or movement of the atoms or molecules of a source material of the nitride semiconductor thin films through migration thereof. As a result, a nitride semiconductor growth layer with good surface flatness can be formed, and thus a nitride semiconductor device with satisfactory characteristics can be obtained.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: February 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Eiji Yamada, Takeshi Kamikawa, Masahiro Araki
  • Publication number: 20130026482
    Abstract: A silicon wafer used in manufacturing GaN for LEDs includes a silicon substrate, a buffer layer of boron aluminum nitride (BxAl1-xN) and an upper layer of GaN, for which 0.35?x?0.45. The BAlN forms a wurtzite-type crystal with a cell unit length about two-thirds of a silicon cell unit length on a Si(111) surface. The C-plane of the BAlN crystal has approximately one atom of boron for each two atoms of aluminum. Across the entire wafer substantially only nitrogen atoms of BAlN form bonds to the Si(111) surface, and substantially no aluminum or boron atoms of the BAlN are present in a bottom-most plane of atoms of the BAlN. A method of making the BAlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and triethylboron and then a subsequent amount of ammonia through the chamber.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Applicant: Bridgelux, Inc.
    Inventor: William E. Fenwick
  • Patent number: 8361888
    Abstract: The present invention provides a method for manufacturing an SOI wafer wherein an HCl gas is mixed in a reactive gas at a step of forming a silicon epitaxial layer on an entire surface of an SOI layer of the SOI wafer having an oxide film on a terrace portion. As a result, it is possible to provide the method for manufacturing an SOI wafer that can easily grow the silicon epitaxial layer on the SOI layer of the SOI wafer having the oxide film on the terrace portion, suppress warpage of the SOI wafer to be manufactured, reduce generation of particles even at subsequent steps, e.g., device manufacture, and decrease a cost for manufacturing such an SOI wafer.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 29, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Nobuhiko Noto
  • Patent number: 8357954
    Abstract: A method for forming a nanowhisker of, e.g., a III-V semiconductor material on a silicon substrate, comprises: preparing a surface of the silicon substrate with measures including passivating the substrate surface by HF etching, so that the substrate surface is essentially atomically flat. Catalytic particles on the substrate surface are deposited from an aerosol; the substrate is annealed; and gases for a MOVPE process are introduced into the atmosphere surrounding the substrate, so that nanowhiskers are grown by the VLS mechanism. In the grown nanowhisker, the crystal directions of the substrate are transferred to the epitaxial crystal planes at the base of the nanowhisker and adjacent the substrate surface.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: January 22, 2013
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Thomas M. I. Martensson
  • Patent number: 8350273
    Abstract: Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: January 8, 2013
    Assignee: Infineon Technologies AG
    Inventor: Martin Henning Albrecht Vielemeyer
  • Patent number: 8344403
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: January 1, 2013
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 8344402
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: January 1, 2013
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 8329520
    Abstract: An island-shaped single crystal semiconductor layer whose top surface has a plane within ±10° from a {211} plane is formed on an insulating surface; a non-single-crystal semiconductor layer is formed in contact with the top surface and a side surface of the single crystal semiconductor layer and on the insulating surface; the non-single-crystal semiconductor layer is irradiated with laser light to melt the non-single-crystal semiconductor layer, and to crystallize the non-single-crystal semiconductor layer formed on the insulating surface with use of the single crystal semiconductor layer as a seed crystal, so that a crystalline semiconductor layer is formed. A semiconductor device having an n-channel transistor and a p-channel transistor formed with use of the crystalline semiconductor layer is provided.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Masahiro Takahashi, Takuya Hirohashi
  • Publication number: 20120299015
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate and a semiconductor functional layer. The substrate is a single crystal. The semiconductor functional layer is provided on a major surface of the substrate and includes a nitride semiconductor. The substrate includes a plurality of structural bodies disposed in the major surface. Each of the plurality of structural bodies is a protrusion provided on the major surface or a recess provided on the major surface. An absolute value of an angle between a nearest direction of an arrangement of the plurality of structural bodies and a nearest direction of a crystal lattice of the substrate in a plane parallel to the major surface is not less than 1 degree and not more than 10 degrees.
    Type: Application
    Filed: February 27, 2012
    Publication date: November 29, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi TACHIBANA, Hisashi Yoshida, Hiroshi Ono, Hajime Nago, Yoshiyuki Harada, Toshiki Hikosaka, Maki Sugai, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 8319285
    Abstract: A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Jiang Yan, Matthias Hierlemann
  • Patent number: 8313967
    Abstract: A method of epitaxial growth of cubic phase, nitrogen-based compound semiconductor thin films on a semiconductor substrate, for example a <001> substrate, which is periodically patterned with grooves oriented parallel to the <110> crystal direction and terminated in sidewalls, for example <111> sidewalls. The method can provide an epitaxial growth which is able to supply high-quality, cubic phase epitaxial films on a <001> silicon substrate. Controlling nucleation on sidewall facets, for example <111>, fabricated in every groove and blocking the growth of the initial hexagonal phase at the outer region of an epitaxial silicon layer with barrier materials prepared at both sides of each groove allows growth of cubic-phase thin film in each groove and either be extended to macro-scale islands or coalesced with films grown from adjacent grooves to form a continuous film. This can result in a wide-area, cubic phase nitrogen-based compound semiconductor film on a <001> substrate.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 20, 2012
    Assignee: STC.UNM
    Inventors: Seung-Chang Lee, Steven R. J. Brueck
  • Patent number: 8304794
    Abstract: A light emitting device includes a substrate having a first surface and a second surface not parallel to the first surface, and a light emission layer disposed over the second surface to emit light. The light emission layer has a light emission surface which is not parallel to the first surface.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: November 6, 2012
    Assignee: SiPhoton Inc.
    Inventor: Shaoher X. Pan
  • Publication number: 20120267606
    Abstract: A group III nitride crystal substrate is provided, wherein, a uniform distortion at a surface layer of the crystal substrate is equal to or lower than 1.7×10?3, and wherein a plane orientation of the main surface has an inclination angle equal to or greater than ?10° and equal to or smaller than 10° in a [0001] direction with respect to a plane including a c axis of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.
    Type: Application
    Filed: June 18, 2012
    Publication date: October 25, 2012
    Inventors: Keiji ISHIBASHI, Yusuke Yoshizumi, Shugo Minobe
  • Patent number: 8294246
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
  • Patent number: 8288756
    Abstract: The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: October 16, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hemant Adhikari, Rusty Harris
  • Patent number: 8278739
    Abstract: A method for manufacturing is: forming an insulating film over a substrate; forming an amorphous semiconductor film over the insulating film; forming over the amorphous semiconductor film, a silicon nitride film in which a film thickness is equal to or more than 200 nm and equal to or less than 1000 nm, equal to or less than 10 atomic % of oxygen is included, and a relative proportion of nitrogen to silicon is equal to or more than 1.3 and equal to or less than 1.5; irradiating the amorphous semiconductor film with a continuous-wave laser light or a laser light with repetition rate of equal to or more than the wave length of 10 MHz transmitting the silicon nitride film to melt and later crystallize the amorphous semiconductor film to form a crystalline semiconductor film.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka
  • Patent number: 8278672
    Abstract: A semiconductor light-emitting device is disclosed. The semiconductor light-emitting device comprises a multilayer epitaxial structure disposed on a semiconductor substrate. The semiconductor substrate has a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is angled toward [0 11] or [01 1] from [100], or toward [011] or [0 11] from [ 100] so that the upper surface of the semiconductor substrate comprises at least two lattice planes with different lattice plane directions. The multilayer epitaxial structure has a roughened upper surface perpendicular to the predetermined lattice direction. The invention also discloses a method for fabricating a semiconductor light-emitting device.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: October 2, 2012
    Assignee: Epistar Corporation
    Inventors: Ya-Ju Lee, Ta-Cheng Hsu, Ming-Ta Chin, Yen-Wen Chen, Wu-Tsung Lo, Chung-Yuan Li, Min-Hsun Hsieh
  • Patent number: 8263988
    Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: September 11, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Thomas Gehrke
  • Patent number: 8263451
    Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
  • Patent number: 8258051
    Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).
    Type: Grant
    Filed: May 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8242555
    Abstract: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 14, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Hussein I. Hanafi
  • Patent number: 8242564
    Abstract: A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 14, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory S. Spencer, Jill C. Hildreth, Robert E. Jones
  • Patent number: 8237247
    Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
  • Publication number: 20120187418
    Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a semiconductor fin located on the semiconductor substrate, and an etch stop layer located between the semiconductor substrate and the semiconductor fin, wherein a lateral sidewall of the semiconductor fin is substantially on the Si {111} crystal plane. Since the semiconductor fin exhibits better surface quality and less crystal defects, it is favorable for manufacturing FINFET.
    Type: Application
    Filed: March 4, 2011
    Publication date: July 26, 2012
    Inventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu
  • Publication number: 20120187422
    Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.
    Type: Application
    Filed: September 7, 2010
    Publication date: July 26, 2012
    Applicants: TOKAI CARBON CO., LTD., THE UNIVERSITY OF TOKYO
    Inventors: Hiroshi Fujioka, Tetsuro Hirasaki, Hitoshi Ue, Junya Yamashita, Hiroaki Hatori
  • Patent number: 8227898
    Abstract: A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface 13a of a p-type semiconductor region 13 extends along a plane tilting from a c-axis (axis <0001>) of hexagonal group-III nitride. A metal layer 15 is deposited on the principal surface 13a of the p-type semiconductor region 13. The metal layer 15 and the p-type semiconductor region 13 are separated by an interface 17 such that the metal layer functions as a non-alloy electrode. Since the hexagonal group-III nitride contains gallium as a group-III element, the principal surface 13a comprising the hexagonal group-III nitride is more susceptible to oxidation compared to the c-plane of the hexagonal group-III nitride. The interface 17 avoids an increase in amount of oxide after the formation of the metal layer 15 for the electrode.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: July 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinji Tokuyama, Masahiro Adachi, Takashi Kyono, Yoshihiro Saito
  • Patent number: 8212294
    Abstract: A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is <111> and wherein the crystallographic orientation of the silicon layer is <100>. In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the <100> silicon layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: July 3, 2012
    Assignee: Raytheon Company
    Inventors: William E. Hoke, Jeffrey R. LaRoche
  • Patent number: 8212336
    Abstract: FET configurations in which two (or more) facets are exposed on a surface of a semiconductor channel, the facets being angled with respect to the direction of the channel, allow for conformal deposition of a convex or concave S/D. A convex tip of the S/D enhances electric fields at the interface, reducing the resistance between the S/D and the channel. In contrast, a S/D having a concave tip yields a dual-gate FET that emphasizes reduced short-channel effects rather than electric field enhancement. The use of self-limiting, selective wet etches to expose the facets facilitates process control, control of interface chemistry, and manufacturability.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: July 3, 2012
    Assignee: Acorn Technologies, Inc.
    Inventors: Andreas Goebel, Paul A. Clifton, Daniel J. Connelly, Vaishali Ukirde
  • Patent number: 8207544
    Abstract: A III-nitride semiconductor device has a support base comprised of a III-nitride semiconductor and having a primary surface extending along a first reference plane perpendicular to a reference axis inclined at a predetermined angle ALPHA with respect to the c-axis of the III-nitride semiconductor, and an epitaxial semiconductor region provided on the primary surface of the support base. The epitaxial semiconductor region includes a plurality of GaN-based semiconductor layers. The reference axis is inclined at a first angle ALPHA1 in the range of not less than 10 degrees, and less than 80 degrees from the c-axis of the III-nitride semiconductor toward a first crystal axis, either one of the m-axis and a-axis. The reference axis is inclined at a second angle ALPHA2 in the range of not less than ?0.30 degrees and not more than +0.30 degrees from the c-axis of the III-nitride semiconductor toward a second crystal axis, the other of the m-axis and a-axis.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: June 26, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yohei Enya, Yusuke Yoshizumi, Takashi Kyono, Takamichi Sumitomo, Katsushi Akita, Masaki Ueno, Takao Nakamura
  • Patent number: 8198706
    Abstract: A method for making a multi-level nanowire structure includes establishing a first plurality of nanowires on a substrate surface, wherein at least some of the nanowires are i) aligned at a predetermined crystallographically defined angle with respect to the substrate surface, ii) aligned substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii. An insulating layer is established between the nanowires of the first plurality such that one of two opposed ends of at least some of the nanowires positioned i) at the predetermined crystallographically defined angle, ii) substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii is exposed. Regions are grown from each of the exposed ends, and such regions coalesce to form a substantially continuous layer on the insulating layer. A second plurality of nanowires is established on the substantially continuous layer.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: June 12, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I. Kamins, Nathaniel Quitoriano
  • Patent number: 8198199
    Abstract: There are disclosed an epitaxial film, comprising: heating an Si substrate provided with an SiO2 layer with a film thickness of 1.0 nm or more to 10 nm or less on a surface of the substrate; and forming on the SiO2 layer by use of a metal target represented by the following composition formula: yA(1?y)B??(1), in which A is one or more elements selected from the group consisting of rare earth elements including Y and Sc, B is Zr, and y is a numeric value of 0.03 or more to 0.20 or less, the epitaxial film represented by the following composition formula: xA2O3?(1?x)BO2??(2), in which A and B are respectively same elements as A and B of the composition formula (1), and x is a numeric value of 0.010 or more to 0.035 or less.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: June 12, 2012
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Jumpei Hayashi, Takanori Matsuda, Tetsuro Fukui, Hiroshi Funakubo
  • Publication number: 20120138951
    Abstract: A semiconductor chip of the present invention is a semiconductor device that includes a hexagonal semiconductor layer having anisotropic mechanical properties. A semiconductor chip (21), when viewed from a direction perpendicular to the semiconductor chip (21), has a rectangular shape that has a first side (1A) and a second side (1B) orthogonal to the first side (1A). The amount of thermal deformation along a direction in which the first side (1A) extends and the amount of thermal deformation along a direction in which the second side (1B) extends are substantially equal to each other.
    Type: Application
    Filed: May 13, 2011
    Publication date: June 7, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Masashi Hayashi, Masao Uchida, Kunimasa Takahashi
  • Patent number: 8193616
    Abstract: A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masafumi Hamaguchi, Ryoji Hasumi
  • Patent number: 8183647
    Abstract: The present invention provides a semiconductor device comprising: a silicon based semiconductor substrate provided with a step including an non-horizontal surface, a horizontal surface and a connection region for connecting the non-horizontal surface and the horizontal surface; a gate insulating film formed in at least a part of the step; and a gate electrode formed on the gate insulating film, wherein the entirety or a part of the gate insulating film is formed of a silicon oxynitride film that contains a rare gas element at a area density of 1010 cm?2 or more in at least a part of the silicon oxynitride film.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: May 22, 2012
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Tadahiro Omi, Naoki Ueda
  • Patent number: 8174095
    Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
  • Publication number: 20120104565
    Abstract: When a mixed gas of trichlorosilane and dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 1000 to 1100° C., preferably, 1040 to 1080° C. When dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 900 to 1150° C., preferably, 1000 to 1150° C. According to this, a silicon epitaxial wafer, which has low haze level, excellent flatness (edge roll-off), and reduced orientation dependence of epitaxial growth rate, and is capable of responding to the higher integration of semiconductor devices, can be obtained, and this epitaxial wafer can be used widely in production of semiconductor devices.
    Type: Application
    Filed: July 8, 2010
    Publication date: May 3, 2012
    Applicant: SUMCO CORPORATION
    Inventor: Naoyuki Wada
  • Patent number: 8169019
    Abstract: A metal-oxide-semiconductor chip having a semiconductor substrate, an epitaxial layer, at least a MOS cell, and a metal pattern layer is provided. The epitaxial layer is located on the semiconductor substrate and has an active region, a termination region, and a scribe line preserving region defined on an upper surface thereof. An etched sidewall of the epitaxial layer is located in the scribe line preserving region. The boundary portion of the upper surface of the semiconductor substrate is thus exposed. The MOS cell is located in the active region. The metal pattern layer is located on the epitaxial layer and has a gate pad coupled to the gate of the MOS cell, a source pad coupled to the source of the MOS cell, and a drain pattern, which is partly located on the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: May 1, 2012
    Assignee: Niko Semiconductor Co., Ltd.
    Inventors: Kuo-Chang Tsen, Kao-Way Tu
  • Patent number: 8159006
    Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong-Hwan Yang, Junga Choi
  • Patent number: 8159050
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Patent number: 8158993
    Abstract: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: April 17, 2012
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ji-Hao Liang, Masahiko Tsuchiya, Takako Chinone, Masataka Kajikawa