With Specified Crystal Plane Or Axis Patents (Class 257/627)
  • Patent number: 8159051
    Abstract: In one aspect of the present invention, a semiconductor device may include a first semiconductor layer of a first conductivity type and having a main surface that has a first plane orientation, a second semiconductor layer of the first conductivity type and having a main surface that has a second plane orientation different from the first plane orientation, the second semiconductor layer being directly provided on the first semiconductor layer, a third semiconductor layer having a main surface that has the first plane orientation, and being formed on the first semiconductor layer and on a side face of the second semiconductor layer, a gate electrode formed on the second semiconductor layer via a gate insulating film, first impurity diffusion regions of a second conductivity type, and being formed in the second semiconductor layer so that the gate electrode is located on a region sandwiched in a gate length direction between the first impurity diffusion regions, the first impurity diffusion regions extending t
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: April 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuaki Yasutake
  • Publication number: 20120074453
    Abstract: A patterned substrate for epitaxially forming a light-emitting diode includes: a top surface; a plurality of spaced apart recesses, each of which is indented downwardly from the top surface and each of which is defined by a recess-defining wall, the recess-defining wall having a bottom wall face, and a surrounding wall face that extends from the bottom wall face to the top surface; and a plurality of protrusions, each of which protrudes upwardly from the bottom wall face of the recess-defining wall of a respective one of the recesses. A light-emitting diode having the patterned substrate is also disclosed.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 29, 2012
    Applicant: National Chung-Hsing University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng, Wei-Ting Lin
  • Patent number: 8143702
    Abstract: A group III-V nitride-based semiconductor substrate includes a group III-V nitride-based semiconductor crystal. A surface area of the substrate is greater than or equal to 45 cm2. A thickness of the substrate is greater than or equal to 200 ?m. An in-plane dislocation density of the substrate is less than or equal to 2×107 cm?2 in average. The in-plane dislocation density of the substrate is less than or equal to 150% of the average at maximum.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: March 27, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventor: Yuichi Oshima
  • Patent number: 8134163
    Abstract: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: March 13, 2012
    Assignee: Taiwan Semiconductor Manfacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Hung-Ta Lin, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu
  • Patent number: 8119571
    Abstract: Novel articles and methods to fabricate same with self-assembled nanodots and/or nanorods of a single or multicomponent material within another single or multicomponent material for use in electrical, electronic, magnetic, electromagnetic and electrooptical devices is disclosed. Self-assembled nanodots and/or nanorods are ordered arrays wherein ordering occurs due to strain minimization during growth of the materials. A simple method to accomplish this when depositing in-situ films is also disclosed. Device applications of resulting materials are in areas of superconductivity, photovoltaics, ferroelectrics, magnetoresistance, high density storage, solid state lighting, non-volatile memory, photoluminescence, thermoelectrics and in quantum dot lasers.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: February 21, 2012
    Inventors: Amit Goyal, Sukill Kang
  • Patent number: 8110459
    Abstract: A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the substrate. A first layer is formed to cover the n-channel MOSFET, wherein the first layer has a first flexure-induced stress. A second layer is formed to cover the p-channel MOSFET, wherein the second layer has a second flexure-induced stress.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 7, 2012
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Koichi Matsumoto
  • Patent number: 8084818
    Abstract: A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: Mohamad A. Shaheen, Brian Doyle, Suman Dutta, Robert S. Chau, Peter Tolchinksy
  • Patent number: 8084781
    Abstract: A compound semiconductor device (1) includes a compound semiconductor having a stacked structure (100) of a hexagonal single crystal layer (101), a boron phosphide-based semiconductor layer (102) formed on a surface of the hexagonal single crystal layer and a compound semiconductor layer (103) disposed on the boron phosphide-based semiconductor layer, and electrodes (108, 109) disposed on the stacked structure, wherein the boron phosphide-based semiconductor layer is formed of a hexagonal crystal disposed on a surface formed of a (1.1.-2.0.) crystal face of the hexagonal single crystal layer.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: December 27, 2011
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8067820
    Abstract: Provided is a method applicable to the production of silicon wafers having crystal orientation <100> or <110> and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment jig for use in carrying out that method. It becomes possible to suppress the shear stress which contributes to the extension of the slip generated at each wafer-supporting element contact point as an initiation, suppress slip growth and thus markedly improve the yield of heat-treated silicon wafers. The heat-treated wafer obtained by using the supporting method and the heat treatment jig has few slip, in particular has no long and large slip, and is high in quality.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: November 29, 2011
    Assignee: Sumco Corporation
    Inventor: Takayuki Kihara
  • Patent number: 8053262
    Abstract: A method for manufacturing a nitride semiconductor laser element having a nitride semiconductor layer including at least an active layer provided on a substrate, a pair of cavity planes formed on the nitride semiconductor layer, and a protruding part where part of the substrate protrudes from said cavity plane, said method comprises: a step of forming the nitride semiconductor layer on the substrate; a first etching step of forming a first groove by etching at least the nitride semiconductor layer; and a second etching step of forming the cavity plane, in the second etching step, the inner wall of the first groove and part of the nitride semiconductor layer surface adjacent to the first groove are etched to form a second groove, and form the upper face of the protruding part.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: November 8, 2011
    Assignee: Nichia Corporation
    Inventor: Shingo Tanisaka
  • Patent number: 8048767
    Abstract: A bonded wafer is produced by directly bonding a silicon wafer for active layer and a silicon wafer for support substrate without an insulating film and thinning the silicon wafer for active layer to a given thickness, in which a silicon wafer cut out from an ingot at a cutting angle of 0-0.1° (compound angle) with respect to a predetermined crystal face is used in each of the silicon wafer for active layer and silicon wafer for support substrate.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: November 1, 2011
    Assignee: Sumco Corporation
    Inventors: Nobuyuki Morimoto, Akihiko Endo
  • Patent number: 8039878
    Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 18, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Igor Peidous, Thorsten Kammler, Andy Wei
  • Patent number: 8034709
    Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: October 11, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng, Li-Lin Su, Jing-Cheng Lin, Shao-Lin Shue, Mong-Song Liang
  • Publication number: 20110220915
    Abstract: A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers.
    Type: Application
    Filed: December 13, 2010
    Publication date: September 15, 2011
    Inventors: James Edgar, Michael Dudley, Martin Kuball, Yi Zhang, Guan Wang, Hui Chen, Yu Zhang
  • Patent number: 8016941
    Abstract: A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation, comprising amorphizing at least a portion of the second layer, applying a stress to the second layer and heating the second layer above a recrystallization temperature.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: September 13, 2011
    Assignees: Infineon Technologies AG, Samsung Electronics Co., Ltd.
    Inventors: Matthias Hierlemann, Ja-Hum Ku
  • Patent number: 8008751
    Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
  • Publication number: 20110198560
    Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 18, 2011
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Hiroaki Okagawa, Hiromitsu Kudo, Teruhisa Nakai, Seong-Jin Kim
  • Publication number: 20110193201
    Abstract: The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate (1), an oxide layer (3) and a thin layer (2) of semiconducting material, according to which: 1) a mask is formed on said thin layer (2) so as to define exposed regions (20), on the surface of said layer, which are not covered by the mask; 2) heat treatment is applied so as to urge at least part of the oxygen of the oxide layer (3) to diffuse through the thin layer (2), leading to controlled removal of the oxide in the regions (30) of the oxide layer (3) corresponding to the desired pattern; characterized in that said carrier substrate (1) and thin layer (2) are arranged relative to each other so that their crystal lattices, in a plane parallel to their interface (I), together form an angle called a “twist angle” of no more than 1°, and in a plane perpendicular to their interface (I) an angle called a “tilt angle” of no more than 1°, and in that a th
    Type: Application
    Filed: October 9, 2009
    Publication date: August 11, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Oleg Kononchuk, Eric Guiot, Fabrice Gritti, Didier Landru, Christelle Veytizou
  • Publication number: 20110180857
    Abstract: A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is <111> and wherein the crystallographic orientation of the silicon layer is <100>. In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the <100> silicon layer.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 28, 2011
    Applicant: Raytheon Company
    Inventors: William E. Hoke, Jeffrey R. LaRoche
  • Patent number: 7982205
    Abstract: A III-V group compound semiconductor light-emitting diode, containing a substrate 1 having plural crystal planes, and a grown layer formed on the substrate by epitaxial growth, the grown layer at least including a barrier layer 2 and 3 and an active layer 8, wherein at least the active layer of the grown layer has plural crystal planes each having a different bandgap energy in the in-plane direction, and an Ohmic electrode 4 for current injection is formed on a crystal plane (3) having a higher bandgap energy among the plural crystal planes.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 19, 2011
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Xue-Lun Wang
  • Patent number: 7977701
    Abstract: A GaN layer is grown on a sapphire substrate, an SiO2 film is formed on the GaN layer, and a GaN semiconductor layer including an MQW active layer is then grown on the GaN layer and the SiO2 film using epitaxial lateral overgrowth. The GaN based semiconductor layer is removed by etching except in a region on the SiO2 film, and a p electrode is then formed on the top surface of the GaN based semiconductor layer on the SiO2 film, to join the p electrode on the GaN based semiconductor layer to an ohmic electrode on a GaAs substrate. An n electrode is formed on the top surface of the GaN based semiconductor layer.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: July 12, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuhiko Hayashi, Takashi Kano
  • Patent number: 7973388
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: July 5, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
  • Patent number: 7972943
    Abstract: A cap film is formed over semiconductor films formed over an insulating substrate; the semiconductor films are irradiated with a laser beam which is capable of completely melting the semiconductor film in a film-thickness direction to completely melt the semiconductor film. By controlling the laser beam, a crystalline semiconductor films are formed over the substrate, in each of which orientations of crystal planes are controlled. In addition, an n-channel thin film transistor is formed using a crystalline region in which crystal planes are oriented along {001} and a p-channel thin film transistor is formed using a crystalline region in which crystal planes are oriented along {211} or {101}.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: July 5, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka
  • Patent number: 7964899
    Abstract: An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventor: Tomoyuki Ishizu
  • Patent number: 7960801
    Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventor: Dureseti Chidambarrao
  • Patent number: 7955983
    Abstract: A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: June 7, 2011
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Bilge M. Imer, James S. Speck, Steven P. DenBaars
  • Publication number: 20110127639
    Abstract: The present disclosure relates to a semiconductor nanostructure. The semiconductor nanostructure includes a substrate and at least one ridge. The substrate includes a first crystal plane and a second crystal plane perpendicular to the first crystal plane. The at least one ridge extends from the first crystal plane along a crystallographic orientation of the second crystal plane. A width of cross section at a position of half the height of the at least one ridge is less than 17 nm. The semiconductor nanostructure is a patterned structure which can lead to generate a quantum confinement effect, such that the impurity scattering phenomenon is reduced.
    Type: Application
    Filed: July 23, 2010
    Publication date: June 2, 2011
    Applicants: TSINGHUA UNIVERSITY, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: JIAN WU, ZHENG LIU, WEN-HUI DUAN, BING-LIN GU
  • Publication number: 20110121434
    Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semi-conductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.
    Type: Application
    Filed: April 24, 2009
    Publication date: May 26, 2011
    Inventors: Xiuling Li, Seth A. Fortuna
  • Patent number: 7948061
    Abstract: A characteristic feature of the invention is to form, in a Group III nitride-based compound semiconductor device, a negative electrode on a surface other than a Ga-polar C-plane. In a Group III nitride-based compound semiconductor light-emitting device, there are formed, on an R-plane sapphire substrate, an n-contact layer, a layer for improving static breakdown voltage, an n-cladding layer made of a multi-layer structure having ten stacked sets of an undoped In0.1Ga0.9N layer, an undoped GaN layer, and a silicon (Si)-doped GaN layer, a multi-quantum well (MQW) light-emitting layer made of a combination of In0.25Ga0.75N well layers and GaN barrier layers stacked alternatingly, a p-cladding layer made of a multi-layer structure including a p-type Al0.3Ga0.7N layer and a p-In0.08Ga0.92N layer, and a p-contact layer (thickness: about 80 nm) made of a stacked structure including two p-GaN layers having different magnesium concentrations.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: May 24, 2011
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yoshiki Saito, Yasuhisa Ushida
  • Publication number: 20110114998
    Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.
    Type: Application
    Filed: January 25, 2011
    Publication date: May 19, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Tomoaki MORIWAKA
  • Patent number: 7935987
    Abstract: Group III nitride layers have a wide range of uses in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and recently Si(111). For the purpose inter alia of integration with Si-CMOS electronics, growth on Si(001) is indicated, which is possible only with difficulty because of the different symmetries and is currently limited solely to misoriented Si(001) substrates, which restricts the range of use. In addition, the layer quality is not at present equal to that produced on Si(111) material. Growth on exactly oriented Si(001) and an improvement in material quality can now be simply achieved by a modification of the surface structure possible with a plurality of methods.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: May 3, 2011
    Assignee: AZZURO Semiconductors AG
    Inventors: Fabian Schulze, Armin Dadgar, Alois Krost
  • Patent number: 7936049
    Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 3, 2011
    Assignee: Panasonic Corporation
    Inventors: Masayuki Kuroda, Tetsuzo Ueda
  • Patent number: 7928568
    Abstract: A nanowire-based device includes the pair of isolated electrodes and a nanowire bridging between respective surfaces of the isolated electrodes of the pair. Specifically, the nanowire-based device having isolated electrodes comprises: a substrate electrode having a crystal orientation; a ledge electrode that is an epitaxial semiconductor having the crystal orientation of the substrate electrode; and a nanowire bridging between respective surfaces of the substrate electrode and the ledge electrode.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: April 19, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shashank Sharma, Theodore I Kamins
  • Patent number: 7928518
    Abstract: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: April 19, 2011
    Assignees: Yazaki Corporation
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii, Takanori Watanabe
  • Publication number: 20110079883
    Abstract: Provided is a ferroelectric thin film formed on a substrate and having an amount of remanent polarization increased in its entirety. The ferroelectric thin film contains a perovskite-type metal oxide formed on a substrate, the ferroelectric thin film containing a column group formed of multiple columns each formed of a spinel-type metal oxide, in which the column group is in a state of standing in a direction perpendicular to a surface of the substrate, or in a state of slanting at a slant angle in a range of ?10° or more to +10° or less with respect to the perpendicular direction.
    Type: Application
    Filed: September 24, 2010
    Publication date: April 7, 2011
    Applicants: CANON KABUSHIKI KAISHA, TOKYO INSTITUTE OF TECHNOLOGY, KYOTO UNIVERSITY
    Inventors: MIKIO SHIMADA, TOSHIAKI AIBA, TOSHIHIRO IFUKU, JUMPEI HAYASHI, MAKOTO KUBOTA, HIROSHI FUNAKUBO, YUICHI SHIMAKAWA, MASAKI AZUMA, YOSHITAKA NAKAMURA
  • Patent number: 7915152
    Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 29, 2011
    Assignee: Cree, Inc.
    Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
  • Patent number: 7915713
    Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Qimonda AG
    Inventors: Juergen Faul, Juergen Holz
  • Patent number: 7915714
    Abstract: There are provided a semiconductor light emitting element which allows an improvement in light extraction efficiency without increasing the number of fabrication steps, and a wafer. In a semiconductor light emitting element 1 formed by laminating a compound semiconductor layer 3 on a single crystal substrate, and dividing the single crystal substrate into pieces, the side faces 21 to 24 of each of substrate pieces 2 as the divided single crystal substrate are formed such that the side face 21 used as the reference of the substrate piece 2 forms an angle of 15° with respect to the (1-100) plane, and that the side faces 21 to 24 are formed of planes different from cleaved planes of a crystalline structure in the single crystal substrate.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: March 29, 2011
    Assignee: Panasonic Corporation
    Inventors: Hidenori Kamei, Syuuichi Shinagawa
  • Publication number: 20110049681
    Abstract: Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Inventor: Martin Henning Albrecht Vielemeyer
  • Patent number: 7898012
    Abstract: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: March 1, 2011
    Assignee: Fujitsu Limited
    Inventor: Kenji Maruyama
  • Patent number: 7898033
    Abstract: A semiconductor device according to this invention is provided with a MOS transistor of at least one type, wherein the MOS transistor has a semiconductor layer (SOI layer) provided on an SOI substrate and a gate electrode provided on the SOI layer and is normally off by setting the thickness of the SOI layer so that the thickness of a depletion layer caused by a work function difference between the gate electrode and the SOI layer becomes greater than that of the SOI layer.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: March 1, 2011
    Assignees: Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto
  • Patent number: 7892879
    Abstract: This invention relates to the manufacture of Cadmium Mercury Telluride (CMT) on patterned silicon, especially to growth of CMT on silicon substrates bearing integrated circuitry. The method of the invention involves growing CMT in selected growth windows on the silicon substrate by first growing one or more buffer layers by MBE and then growing the CMT by MOVPE. The growth windows may be defined by masking the area outside of the growth windows. Growth within the growth windows is crystalline whereas any growth outside the growth windows is polycrystalline and can be removed by etching. The invention offers a method of growing CMT structures directly on integrated circuits removing the need for hybridisation.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: February 22, 2011
    Assignee: Qinetiq Limited
    Inventors: Louise Buckle, John W Cairns, Jean Giess, Neil T Gordon, Andrew Graham, Janet E Hails, David J Hall, Colin J Hollier, Graham J Pryce, Andrew J Wright
  • Publication number: 20110037150
    Abstract: A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.
    Type: Application
    Filed: May 18, 2009
    Publication date: February 17, 2011
    Inventor: Bich-Yen Nguyen
  • Patent number: 7888780
    Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Publication number: 20110031592
    Abstract: Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode).
    Type: Application
    Filed: April 17, 2009
    Publication date: February 10, 2011
    Applicant: SUMCO CORPORATION
    Inventors: Masayuki Ishibashi, Shinji Nakahara, Tetsuro Iwashita
  • Patent number: 7884448
    Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 7884010
    Abstract: A wiring structure has a silicon layer, a backing layer provided on the silicon layer, the backing layer comprising a copper alloy containing a manganese, and a copper layer provided on the backing layer, and a diffusion barrier layer having an electrical conductivity, the diffusion barrier layer being provided at a region including an interface between the silicon layer and the backing layer, in which a manganese in the diffusion barrier layer is enriched compared with the backing layer.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: February 8, 2011
    Assignee: Hitachi Cable, Ltd.
    Inventors: Noriyuki Tatsumi, Tatsuya Tonogi
  • Patent number: 7884447
    Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate (201). In an illustrative implementation, a laser diode is oriented on a GaN substrate (201) wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <1120> or the <1100> family of directions. For a <1120> off-cut substrate, a laser diode cavity (207) may be oriented along the <1100> direction parallel to lattice surface steps (202) of the substrate (201) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For <1100> off-cut substrate, the laser diode cavity may be oriented along the <1100> direction orthogonal to lattice surface steps (207) of the substrate (201) in order to provide a cleave laser facet that is aligned with the surface lattice steps.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: February 8, 2011
    Assignee: Cree, Inc.
    Inventors: George R. Brandes, Robert P. Vaudo, Xueping Xu
  • Patent number: 7879658
    Abstract: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: February 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Ichiro Mizushima, Takashi Suzuki, Hirokazu Ishida, Yoshitaka Tsunashima
  • Patent number: 7875959
    Abstract: The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: January 25, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hu Ke, Wen-Chin Lee, Chenming Hu