Abstract: To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do not need to be prepared. One of two semiconductor wafers having a notch or an orientation flat provided in the same crystal orientation <110> is set to be a wafer (1) for the support substrate and the other is set to be a wafer for the device formation. Both wafers are bonded with the notches or orientation flats shifted from each other (for example, a crystal orientation <100> of the wafer for the device formation and the crystal orientation <110> of the wafer (1) for the support substrate are set to the same direction). The wafer for the device formation is divided to obtain an SOI layer (3). A MOS transistor (TR1) or the like is formed on the SOI layer (3).

Abstract: A semiconductor device has a structure in which a GaAs substrate and an InP substrate, different in lattice constant, are bonded to each other. An amorphous layer made of constituent atoms of the GaAs and InP substrates is formed at the interface between the GaAs and InP substrates. Forming the amorphous layer makes it possible to prevent a reduction of light-emitting efficiency caused by a thermal stress at the interface, even when a light-emitting layer by laser oscillation is formed near the interface. Besides, a linear current-voltage characteristic can be obtained at the interface.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.

Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

Abstract: In a semiconductor device including n-channel field-effect transistors and p-channel field-effect transistors, in which the channel direction is parallel to a axis, a semiconductor device in provided which has excellent drain current characteristics at both n-channel field-effect transistors and p-channel field-effect transistors. In a semiconductor device including n-channel field-effect transistors N1 and N2 and p-channel field-effect transistors P1 and P2, a stress control film that covers the gate electrodes of the n-channel and p-channel field-effect transistors from upper surfaces thereof is not formed, or is made thin, above shallow trench isolations adjacent to active regions formed by the p-channel field-effect transistors P1 and P2, in a case where the stress control film is a tensile film stress. Thus, improvement of the drain currents of both the n-channel and p-channel transistors can be expected. For this reason, it is possible to improve overall characteristics.

Abstract: Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.

Abstract: A method of making an electronic device comprising the steps of: providing a plurality of wafers, each wafer comprising a bonding surface; etching one or more trenches into one or more bonding surfaces, the trenches substantially perpendicular to a preferred direction of diffusion along one or more of the bonding surfaces; rendering the bonding surfaces hydrophobic; and bonding the bonding surfaces together by direct wafer bonding. A semiconductor structure comprising a plurality of wafers, each wafer comprising a bonding surface, one or more bonding surfaces comprising one or more trenches substantially perpendicular to a preferred direction of diffusion along one or more of the bonding surfaces; and the bonding surfaces bonded together by a direct wafer bonding interface.

Abstract: A semiconductor film comprising a polycrystalline semiconductor film provided on a substrate having an insulating surface. Nearly all crystal orientation angle differences between adjacent crystal grains constituting the polycrystalline semiconductor film are present in the ranges of less than 10° or 58°-62°.

Abstract: A III nitride multilayer including a given substrate, a III nitride underfilm including an Al content of 50 atomic percent or more for all of the III elements present in the III nitride underfilm, and a III nitride film including a lower Al content than the Al content of the III nitride underfilm by 10 atomic percent or more. A full width at half maximum X-ray rocking curve value of the III nitride film is set to 800 seconds or below at the (100) plane. A full width at half maximum X-ray rocking curve value of the III nitride film is set to 200 seconds or below at the (002) plane.

Abstract: A semiconductor device is disclosed. The semiconductor device has a crystalline silicon film as an active layer region. The crystalline silicon film has needle-like or columnar crystals oriented parallel to the substrate and having a crystal growth direction of (111) axis. A method for preparing the semiconductor device comprises steps of adding a catalytic element to an amorphous silicon film; and heating the amorphous silicon film containing the catalytic element at a low temperature to crystallize the silicon film.

Abstract: A method for creating a MEMS structure is provided. In accordance with the method, an article is provided which comprises a substrate (101) and a single crystal semiconductor layer (105), and having a sacrificial layer (103) comprising a first dielectric material which is disposed between the substrate and the semiconductor layer. An opening (107) is created which extends through the semiconductor layer (105) and the sacrificial layer (103) and which exposes a portion of the substrate (101). An anchor portion (109) comprising a second dielectric material is then formed in the opening (107). Next, the semiconductor layer (105) is epitaxially grown to a suitable device thickness, thereby forming a device layer (111).

Abstract: A quantum wire field-effect transistor having at least one, one-dimensional, elongate conducting means (14) provided by at least a first semiconductor layer surrounded by a wider bandgap, second semiconductor layer (12, 13) and extending between source (24) and drain (26) electrodes, and in which there is provided a backgate structure (8, 23) to control conduction in the elongate conducting means. The transistor can be a Single Electron Transistor (SET) wherein two adjacent gate electrode (16, 18) are disposed over the elongate conducting means to induce a quantum dot (17) therein, and it can be made with the first semiconductor layer material as GaAs and the second semiconductor layer material as AlGaAs. A method of making the transistor involves preferentially growing the elongate conducting means at the bottom of a groove (6) lined with second semiconductor layer (12).

Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

Abstract: An electronic device substrate structure including a substrate 2, a metal thin film 4 as a (111)-oriented film of a face-centered cubic structure or as a (0001)-oriented film of a hexagonal closest packed structure formed on the substrate 2, and a wurtzite type thin film 5 as a (0001)-oriented film of a wurtzite crystal structure formed on the metal thin film 4, wherein: each of the two thin films is a polycrystalline film containing at least two kinds of crystal grains different in direction of crystal orientation in the plane; when the metal thin film 4 is a (111)-oriented film, <11-20> axes in the plane of the wurtzite type thin film 5 are parallel to <1-10> axes in the plane of the metal thin film 4; and when the metal thin film 4 is a (0001)-oriented film, <11-20> axes in the plane of the wurtzite type thin film 5 are parallel to <11-20> axes in the plane of the metal thin film 4.

Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.

Abstract: A SiC wafer comprises a 4H polytype SiC substrate 2 in which the crystal plane orientation is substantially {03-38}, and a buffer layer 4 composed of SiC formed over this SiC substrate 2. The {03-38} plane forms an angle of approximately 35° with respect to the <0001> axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer 6 on the buffer layer 4. Lattice mismatching between the SiC substrate 2 and the active layer 6 is suppressed by the buffer layer 4. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.

Abstract: A semiconductor device having a bipolar transistor which is capable of high integration, and a semiconductor device in which the bipolar transistor has good characteristic properties. A process for producing said semiconductor device.

Abstract: A ball-limiting metallurgy stack is disclosed for an electrical device that contains at least one copper layer disposed upon a titanium adhesion metal layer. The ball-limiting metallurgy stack resists tin migration toward the upper metallization of the device. An etch process flow is also disclosed which resists the redepostion of the tin during etching of a copper layer.

Abstract: The state of a surface of a substrate 11 or a GaN group compound semiconductor film 12 formed on the substrate 11 is modified with an anti-surfactant material and a GaN group compound semiconductor material is supplied by a vapor phase growth method to form dot structures made of the GaN group compound semiconductor on the surface of the semiconductor film 12, and the growth is continued until the dot structures join and the surface becomes flat. In this case, the dot structures join while forming a cavity 21 on an anti-surfactant region. A dislocation line 22 extending from the underlayer is blocked by the cavity 21, and therefore, the dislocation density of an epitaxial film surface can be reduced. As a result, the dislocation density of the GaN group compound semiconductor crystal can be reduced without using a masking material in the epitaxial growth, whereby a high quality epitaxial film can be obtained.

Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.

Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.

Abstract: The semiconductor substrate comprises a silicon substrate 10, a silicon germanium layer 12 formed on the silicon substrate; and a silicon layer 14 formed on the silicon germanium layer. At least one of an isotope composition ratio of one Si isotope and an isotope composition ratio of a Ge isotope of at least one of the silicon substrate, the silicon germanium layer and the silicon layer is above 95%. In at least one of the silicon substrate, the silicon germanium layer and the silicon layer, at lest one of an isotope composition ratio of one Si isotope and an isotope composition ratio of one Ge isotope is set higher, whereby the heat can be scattered in the direction horizontal to the substrate plane. Thus, the semiconductor substrate can have higher heat radiation.

Abstract: A surface orientation other than a (100) surface orientation is exposed to the surface portion of a silicon substrate having the (100) surface orientation, for example. A silicon epitaxial growth layer is formed only on a region containing a channel forming region on the (100) surface orientation.

Abstract: Disclosed is a polysilicon film adapted for use in a liquid crystal display, and method of manufacturing such film. In manufacturing the film, a native oxide layer formed on a surface of an amorphous silicon film is completely removed by a hydrofluoric acid solution, followed by immersing in an H2O2 solution to newly form an extremely thin oxide layer, prior to a crystallizing processing performed by a laser beam irradiation. The crystallizing processing forms a polysilicon film formed of crystal grains Preferentially oriented on the (111) plane in a direction parallel to the substrate surface, an average crystal grain size being not larger than 300 nm, the standard deviation of the grain sizes being not larger than 30% of the average grain size, and the standard deviation of the roughness being not larger than 10% of the average grain size.

Abstract: A semiconductor light emitting element includes: a first conductive type layer made of a nitride semiconductor which is deposited on a substrate; a quantum well active layer made of AlPGaQIn1−P−QN (O≦P, O≦Q, P+Q<1) which is deposited on the first conductive type layer, the quantum well active layer including a pair of barrier layers and a well layer interposed therebetween; and a second conductive type layer made of a nitride semiconductor which is deposited on the quantum well active layer, wherein light spontaneously emitted from end faces of the quantum well active layer to polarized in a direction parallel to the substrate.

Abstract: A nitride semiconductor having a large low-defect region in a surface thereof, and a semiconductor device using the same are provided. Also, a manufacturing method for a nitride semiconductor comprising a layer formation step using a transverse growth technique where surface defects can easily be reduced, and a manufacturing method for a semiconductor device using the same are provided. On a substrate, a seed crystal part is formed in a stripe pattern with a buffer layer in between. Next, crystals are grown from the seed crystal part in two stages of growth conditions to form a nitride semiconductor layer. Low temperature growing parts with a trapezoid shaped cross section are formed at a growth temperature of 1030° C. in the first stage and a transverse growth is dominantly advanced at a growth temperature of 1070° C. to form a high temperature growing part between the low temperature growing parts in the second stage.

Abstract: An optical receiver having a silicon substrate with a top surface cleaved from a [100] silicon crystallographic plane and a reflector, and a photodetector coupled to the top surface of the silicon substrate, the photodetector being adapted to receive an incoming signal from a fiber.

Abstract: The present invention provides FinFETs on the same substrate utilizing various crystal planes for FET current channels in order to optimize mobility and/or to reduce mobility. An embodiment of the present invention provides a substrate having a surface oriented on a first crystal plane that enables subsequent crystal planes for channels to be utilized. A first transistor is also provided having a first fin body. The first fin body has a sidewall forming a first channel, the sidewall oriented on a second crystal plane to provide a first carrier mobility. A second transistor is also provided having a second fin body. The second fin body has a sidewall forming a second channel, the sidewall oriented on a third crystal plane to provide a second carrier mobility that is different from the first carrier mobility.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.

Abstract: A laminated substrate is formed by laminating a device formation layer made of single crystalline semiconductor on a supporting substrate made of single crystalline semiconductor via an insulating layer with making one direction of a crystallographic axis of the device formation layer be shifted from a corresponding direction of a crystallographic axis of the supporting substrate. Semiconductor devices are formed in the device formation layer within a plurality of areas divided by scribe lines extending to a direction being parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved. The laminated substrate is split into a plurality of chips by cleaving the supporting substrate along the scribe lines. A semiconductor device can easily be split into chips even if a moving direction of carrier and an extending direction of wiring are shifted from an easy-cleaved direction of a crystallographic axis.

Abstract: There is disclosed a p-n junction diode structure whose electrical characteristics can be affected by the application of pressure or other mechanical stresses that will control sensitivity. The p-n junction consists of two different semiconductor materials, one being of p-type and the other of n-type, both having predetermined crystallographic axes which are fusion bonded together to form a p-n junction. Because of the ability to control the position of the crystallographic axes with respect to one another, one can affect the electrical characteristics of the p-n junction and thereby produce devices with improved operating capabilities such as Zener diodes, tunnel diodes as well as other diodes.

Abstract: This invention discloses a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface. A method for producing packaged integrated circuits is also disclosed.

Abstract: A method includes epitaxially growing a semiconductor layer with a free surface and performing an anneal that reduces atomic roughness on the free surface. The free surface has an orientation with respect to lattice axes of the layer for which atoms in flat regions of the free surface have more chemical bonds to the layer than do, at least, some of the atoms at edges of monolayer steps on the free surface.

Abstract: A semiconductor substrate has a main surface oriented to {1 1 1} face, a first orientation flat formed on a peripheral portion of a semiconductor substrate and oriented to one of {1 1 1} face and {1 1 2} face perpendicular to the {1 1 0} face. It is easy to select (determine) {1 1 1} face for forming a trench in the semiconductor substrate based on the first orientation flat. In addition, the trench whose face is oriented to {1 1 1} face has few defects on its inner surface.

Abstract: The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of &agr; (0°<&agr;<90°) for the [011] direction, &bgr; (0°<&bgr;<90°) for the [01-1] direction and &ggr; (0°≦&ggr;<45°) for the [10-1] or [101] direction. Thus, a single crystal wafer that can sufficiently bear device production processes even with a small wafer thickness is provided and thereby loss of single crystal raw material is reduced. Further, by using such a wafer, MIS type semiconductor devices and solar cells are provided at a low cost.

Abstract: Semiconductor devices based on thin film transistors formed over substrates. In one embodiment, a semiconductor device comprises at least two thin film transistors formed over a substrate, each of said thin film transistors having a crystalline semiconductor film comprising silicon formed on an insulating surface as an active region thereof, wherein said crystalline semiconductor film of each of said two thin film transistors has substantially no grain boundary therein, and a crystal axis of said crystalline semiconductor film in one of said two thin film transistors deviates from a crystal axis of the crystalline semiconductor film of the other, and the deviation of the crystal axis is within ±10°.

Abstract: A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <100> crystallographic plane and another one of such planes being the <1 10> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the <110> plane being oxidized at a higher rate than sidewalls in the <100> plane producing silicon dioxide on the silicon nitride layer having thickness over the <110> plane greater than over the <100> plane.

Abstract: A semiconductor device provided with an isolation oxide film formed by a trench isolation technique is described. The device prevents the development of crystal defects from the corners of a trench and secures stable operating characteristics. The semiconductor device is provided with an isolation oxide film formed so that boundaries between an active region and the isolation oxide film extend in a direction inclined at an angle in the range of 45°±10° to the cleavage plane of a silicon substrate. The isolation oxide film has a interior wall oxide film of a thickness in the range of 50 Å to 1000 Å coating the side walls and the bottom wall of a trench, and a filling oxide film filling up the trench coated with the interior wall oxide film. The edges of the active region contiguous to the isolation oxide film are rounded properly.

Abstract: A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.

Abstract: A semiconductor device has a semiconductor die with a rhombic shape and including a substrate with a hexagonal crystal structure, first and second semiconductor films formed on the substrate, and first and second metal contacts formed respectively on the semiconductor films. The hexagonal crystal structure has six equilateral sides. The semiconductor die has two parallel first side edges and two parallel second side edges, which extend in directions that are substantially parallel to respective ones of the six equilateral sides of the hexagonal crystal structure.

Abstract: A method is provided to optimize the channel characteristics of thin film transistors (TFTs) on polysilicon films. The method is well suited to the production of TFTs for use as drivers on liquid crystal display devices. Regions of polycrystalline silicon can be formed with different predominant crystal orientations. These crystal orientations can be selected to match the desired TFT channel orientations for different areas of the device. The crystal orientations are selected by rotating a mask pattern to a different orientation for each desired crystal orientation. The mask is used in connection with lateral crystallization ELA processes to crystallize deposited amorphous silicon films.

Abstract: In a sapphire substrate having a heteroepitaxial growth surface, the heteroepitaxial growth surface is parallel to a plane obtained by rotating a (01{overscore (1)}0) plane of the sapphire substrate about a c-axis of the sapphire substrate through 8° to 20° in a crystal lattice of the sapphire substrate. A semiconductor device, electronic component, and crystal growing method are also disclosed.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.

Abstract: LEDs employing a III-Nitride light emitting active region deposited on a base layer above a substrate show improved optical properties with the base layer grown on an intentionally misaligned substrate with a thickness greater than 3.5 &mgr;m. Improved brightness, improved quantum efficiency, and a reduction in the current at which maximum quantum efficiency occurs are among the improved optical properties resulting from use of a misaligned substrate and a thick base layer. Illustrative examples are given of misalignment angles in the range from 0.05° to 0.50°, and base layers in the range from 6.5 to 9.5 &mgr;m although larger values of both misalignment angle and base layer thickness can be used. In some cases, the use of thicker base layers provides sufficient structural support to allow the substrate to be removed from the device entirely.

Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}.

Abstract: To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do not need to be prepared. One of two semiconductor wafers having a notch or an orientation flat provided in the same crystal orientation <110> is set to be a wafer (1) for the support substrate and the other is set to be a wafer for the device formation. Both wafers are bonded with the notches or orientation flats shifted from each other (for example, a crystal orientation <100> of the wafer for the device formation and the crystal orientation <110> of the wafer (1) for the support substrate are set to the same direction). The wafer for the device formation is divided to obtain an SOI layer (3). A MOS transistor (TR1) or the like is formed on the SOI layer (3).