Major Crystal Plane Or Axis Other Than (100), (110), Or (111) (e.g., (731) Axis, Crystal Plane Several Degrees From (100) Toward (011), Etc.) Patents (Class 257/628)
  • Patent number: 7196400
    Abstract: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: March 27, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara
  • Patent number: 7187059
    Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the <110> and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Kathryn W. Guarini, Meikel Ieong, Kern Rim, Min Yang
  • Patent number: 7183585
    Abstract: To provide a semiconductor device that excels in the manufacturing efficiency and device reliability, and a method for the manufacture thereof. The side of a device is composed of scribed grooves 13 and a cleavage plane 100.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: February 27, 2007
    Assignee: NEC Corporation
    Inventor: Masaru Kuramoto
  • Patent number: 7173285
    Abstract: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes features therein.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: February 6, 2007
    Assignee: Cree, Inc.
    Inventors: Christer Hallin, Heinz Lendenmann
  • Patent number: 7148559
    Abstract: An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction. The <110> direction is perpendicular to the <100> direction. A method of fabricating such as integrated semiconductor structure is also provided.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: December 12, 2006
    Assignee: International Business Machines Corporation
    Inventors: Victor W. C. Chan, Meikei Leong, Min Yang
  • Patent number: 7141866
    Abstract: An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and therefore are (111) vertical lattice planes of the semiconductor substrate. The semiconductor substrate includes a plurality of vertical structures between the sidewalls, wherein the vertical structures may be nano-scale spaced apart. The method includes wet etching a trench with spaced apart (111) vertical sidewalls in an exposed portion of the (110) horizontal surface of the semiconductor substrate along (111) vertical lattice planes. A chemical etching solution is used that etches the (111) vertical lattice planes slower than the (110) horizontal lattice plane. The method further includes forming the imprinting mold.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: November 28, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: M. Saif Islam, Gun Young Jung, Yong Chen, R. Stanley Williams
  • Patent number: 7132730
    Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1.0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1.0 ?m thick and its surface dislocation density is less than 106/cm2.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: November 7, 2006
    Assignees: Ammono Sp. z.o.o., Nichia Corporation
    Inventors: Robert Dwiliński, Roman Doradziński, Jerzy Garczyński, Leszek P. Sierzputowski, Yasuo Kanbara
  • Patent number: 7109521
    Abstract: An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: September 19, 2006
    Assignee: Cree, Inc.
    Inventors: Christer Hallin, Heinz Lendenmann, Joseph John Sumakeris
  • Patent number: 7102166
    Abstract: A hybrid orientation semiconductor structure and method of forming the same. The structure includes (a) a semiconductor substrate comprising a first semiconductor material having a first lattice orientation; (b) a back gate region on the semiconductor substrate; (c) a back gate dielectric layer on the back gate region; (d) a semiconductor region on the back gate dielectric layer, wherein the semiconductor region is electrically insulated from the back gate region by the back gate dielectric layer, and wherein the semiconductor region comprises a second semiconductor material having a second lattice orientation different from the first lattice orientation; and (e) a field effect transistor (FET) formed on the semiconductor region, wherein changing a voltage potential applied to the back gate region causes a change in a threshold voltage of the FET.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Andres Bryant, William F. Clark, Jr., Edward J. Nowak
  • Patent number: 7087965
    Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Meikei Ieong, Alexander Reznicek, Devendra K. Sadana, Leathen Shi, Min Yang
  • Patent number: 7071513
    Abstract: An economical integration of trench VDMOS devices into a conventional BCD process is provided, with the optimization of key aspects of the device layout for low Rds(on) area. Specifically, trench orientation, array geometry, the number of source cells between drain pickups and drain-source spacing are independently optimized. In one embodiment of the invention, the optimized device utilizes a rectangular cell array with an elongation ratio in the range of 5/3–7/3, with a ratio of 5/3 being preferred, and a cell orientation at 45° with respect to the wafer flat on a 100 wafer.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: July 4, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Terry Dyer, Andrew Strachan
  • Patent number: 7064357
    Abstract: A nitride compound semiconductor light emitting device includes: a GaN substrate having a crystal orientation which is tilted away from a <0001> direction by an angle which is equal to or greater than about 0.05° and which is equal to or less than about 2°, and a semiconductor multilayer structure formed on the GaN substrate, wherein the semiconductor multilayer structure includes: an acceptor doping layer containing a nitride compound semiconductor; and an active layer including a light emitting region.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: June 20, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Ueta, Takayuki Yuasa, Atsushi Ogawa, Yuhzoh Tsuda, Masahiro Araki
  • Patent number: 7057216
    Abstract: In all representative embodiments presented, the Ge concentration in the source and drain 10 and the SiGe epitaxial channel layer 20 is in the 15% to 50% range, preferably between about 20% to 40%. The SiGe thicknesses in the source/drain 10 are staying below the critical thickness for the given Ge concentration. The critical thickness is defined such that above it the SiGe will relax and defects and dislocations will form. The thickness of the SiGe epitaxial layer 20 typically is between about 5nm and 15nm. The thickness of the epitaxial Si layer 30 is typically between about 5nm and 15nm. FIG. 1A shows an embodiment where the body is bulk Si. These type of devices are the most common devices in present day microelectronics. FIGS. 1B and 1C show representative embodiment of the heterojunction source/drain FET device when the Si body 40 is disposed on top of an insulating material 55. This type of technology is commonly referred to as silicon on insulator (SOI) technology.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: June 6, 2006
    Assignee: International Business Machines Corporation
    Inventors: Qiqing Christine Ouyang, Xiangdong Chen
  • Patent number: 7045879
    Abstract: The principal surface of a p-type SiC substrate (1) is formed of a face intersecting (0001) Si-face at 10 to 16°. An n+ source region (2) and an n+ drain region (3) are formed in a surface layer portion at the principal surface of the p-type SiC substrate (1) so as to be separated from each other. A gate electrode (5) is formed on a gate oxide film (4) on the principal surface of the p-type SiC substrate (1).
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: May 16, 2006
    Assignee: Denso Corporation
    Inventors: Yoshiyuki Hisada, Eiichi Okuno, Yoshihito Mitsuoka, Shinji Amano, Takeshi Endo, Shinichi Mukainakano, Ayahiko Ichimiya
  • Patent number: 7045880
    Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 16, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes, Alan R. Reinberg
  • Patent number: 7023055
    Abstract: A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Alexander Reznicek, Min Yang
  • Patent number: 7012318
    Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrate via a non-C-plane surface to the growing gallium nitride crystal. Otherwise, oxygen can be doped into a gallium nitride crystal by preparing a C-plane gallium nitride seed crystal or a three-rotationally symmetric plane foreign material seed crystal, supplying material gases including gallium, nitrogen and oxygen to the C-plane gallium nitride seed crystal or the three-rotationally symmetric foreign seed crystal, growing a faceted C-plane gallium nitride crystal having facets of non-C-planes on the seed crystal, maintaining the facets on the C-plane gallium nitride crystal and allowing oxygen to infiltrate via the non-C-plane facets to the gallium nitride crystal.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: March 14, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Masaki Ueno
  • Patent number: 6998639
    Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: February 14, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Takeshi Fukunaga, Hongyong Zhang
  • Patent number: 6960821
    Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: November 1, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes, Alan R. Reinberg
  • Patent number: 6936865
    Abstract: A visible light transmitting structure with photovoltaic effect comprises a transparent substrate and a PN junction layer having a P type semiconductor and an N type semiconductor, which is formed on the substrate. The visible light transmitting structure with photovoltaic effect may be used as a windowpane of a house or a business place for shutting out harmful ultraviolet rays by passing visible light through the windowpane.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: August 30, 2005
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Kazuhiko Tonooka
  • Patent number: 6882026
    Abstract: In a semiconductor apparatus, a plurality of HBTs (heterojunction bipolar transistors) are formed on a front surface consisting of a (100) crystal plane of a GaAs substrate. Via holes passing thorough the GaAs substrate are formed in proximity of the HBTs. Each via hole has a rectangular-shaped hole edge at the front surface side of the GaAs substrate. The longitudinal direction of the hole edge on the surface side of the via hole is parallel to the [011] direction of crystal orientation of the GaAs substrate. A width of the via hole in a direction perpendicular to the [011] direction of crystal orientation is larger at the back surface of the substrate than at the front surface thereof.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: April 19, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuhiko Shirakawa
  • Patent number: 6867460
    Abstract: An electronic device, and SRAM and a method of forming the electronic device and SRAM. The semiconductor device including: a pass gate transistor having a fin body having opposing sidewalls aligned in a first direction and having a first majority carrier mobility and a gate adjacent to both sidewalls of the fin body; a pull down latch transistor having a fin body having opposing sidewalls aligned in a second direction and having a second majority carrier mobility and a gate adjacent to both sidewalls of thc fin body; a pull up latch transistor having a fin body having opposing sidewalls aligned in a third direction and having a third majority carrier mobility and a gate adjacent to both sidewalls of the fin body; and CMOS chevron logic circuits, wherein crystal planes of each fin body and of CMOS transistor of the chevron logic are co-aligned.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: March 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 6849875
    Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: February 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masahiro Ishida
  • Patent number: 6844611
    Abstract: The crystal orientation of the main surface of a sapphire single crystal base material to constitute an epitaxial substrate is inclined from the <0001> orientation (c-axis) preferably for the <1-100> orientation (m-axis) by a range within 0.02-0.3 degrees. Then, a surface nitride layer is formed at the main surface of the base material. Then, a III nitride underfilm is formed on the main surface of the base material via the surface nitride layer. The III nitride underfilm includes at least Al element, and the full width at half maximum at (101-2) reflection in X-ray rocking curve of the III nitride underfilm is 2000 seconds. The surface roughness Ra within 5 ?m area is 3.5 ?.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: January 18, 2005
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Shigeaki Sumiya, Keiichiro Asai, Mitsuhiro Tanaka
  • Patent number: 6806172
    Abstract: Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: October 19, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Eric N. Paton, Susan Tover
  • Patent number: 6800927
    Abstract: Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: October 5, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes
  • Publication number: 20040188808
    Abstract: A structural element having a region of porous silicon or porous silicon oxide, which was obtained from a porization, starting from an edge area of the region, in at least largely crystalline silicon. Relative to the edge area, the crystalline silicon has a crystal orientation that has an orientation that differs from a <100> orientation or from an orientation that is equivalent for reasons of symmetry. This structural element is suited for use in a mass-flow sensor, in a component for the thermal decoupling of sensor and/or actuator structures, or a gas sensor. Furthermore, methods for setting the thermal conductivity of a region of porous silicon or porous silicon oxide of a structural element are described.
    Type: Application
    Filed: December 18, 2003
    Publication date: September 30, 2004
    Inventors: Hans Artmann, Thorsten Pannex, Hans-Peter Trah, Franz Laermer
  • Patent number: 6797991
    Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: September 28, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masahiro Ishida
  • Patent number: 6765234
    Abstract: A semiconductor light emitting device includes: a silicon substrate; and a plurality of column-shaped multilayered structures formed on the silicon substrate in such a manner that the column-shaped multilayered structures are insulated from one another, the column-shaped multilayered structures being made of a nitride semiconductor material, and each column-shaped multilayered structure including a light emitting layer, wherein the column-shaped multilayered structures are connected to one another by an electrode.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: July 20, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Norikatsu Koide
  • Patent number: 6765244
    Abstract: A III nitride multilayer including a given substrate, a III nitride underfilm including an Al content of 50 atomic percent or more for all of the III elements present in the III nitride underfilm, and a III nitride film including a lower Al content than the Al content of the III nitride underfilm by 10 atomic percent or more. A full width at half maximum X-ray rocking curve value of the III nitride film is set to 800 seconds or below at the (100) plane. A full width at half maximum X-ray rocking curve value of the III nitride film is set to 200 seconds or below at the (002) plane.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: July 20, 2004
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Shigeaki Sumiya, Keiichiro Asai, Mitsuhiro Tanaka
  • Publication number: 20040130004
    Abstract: A semiconductor element is formed in the major surface of a semiconductor chip. Curved surfaces having a radius of curvature of 0.5 to 50 &mgr;m are formed at at least some of edges where the side surfaces and backside surface of the semiconductor chip cross.
    Type: Application
    Filed: October 16, 2003
    Publication date: July 8, 2004
    Inventor: Tetsuya Kurosawa
  • Patent number: 6759684
    Abstract: An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: July 6, 2004
    Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology Corporation
    Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi
  • Publication number: 20040108576
    Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.
    Type: Application
    Filed: December 5, 2003
    Publication date: June 10, 2004
    Applicant: Semiconductor Energy Laboratory, Co., Ltd., a Japan corporation
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
  • Publication number: 20040108575
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 10, 2004
    Applicant: Tadahiro OHMI
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Publication number: 20040099918
    Abstract: An electronic device substrate structure including a substrate 2, a metal thin film 4 as a (111)-oriented film of a face-centered cubic structure or as a (0001)-oriented film of a hexagonal closest packed structure formed on the substrate 2, and a wurtzite type thin film 5 as a (0001)-oriented film of a wurtzite crystal structure formed on the metal thin film 4, wherein: each of the two thin films is a polycrystalline film containing at least two kinds of crystal grains different in direction of crystal orientation in the plane; when the metal thin film 4 is a (111)-oriented film, <11-20> axes in the plane of the wurtzite type thin film 5 are parallel to <1-10> axes in the plane of the metal thin film 4; and when the metal thin film 4 is a (0001)-oriented film, <11-20> axes in the plane of the wurtzite type thin film 5 are parallel to <11-20> axes in the plane of the metal thin film 4.
    Type: Application
    Filed: August 29, 2003
    Publication date: May 27, 2004
    Applicant: TDK CORPORATION
    Inventors: Takao Noguchi, Hisatoshi Saitou, Hidenori Abe, Yoshinari Yamashita
  • Patent number: 6734530
    Abstract: A GaN-based compound semiconductor epi-wafer includes: a substrate 11 made of a first nitride semiconductor belonging to a hexagonal system; and an element layer 12 for forming a semiconductor element, which is made of a second nitride semiconductor belonging to the hexagonal system and which is grown on a principal surface of the substrate 11. An orientation of the principal surface of the substrate 11 has an off-angle in a predetermined direction with respect to a (0001) plane, and the element layer 12 has a surface morphology of a stripe pattern extending substantially in parallel to the predetermined direction.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industries Co., Ltd.
    Inventor: Yuzaburo Ban
  • Patent number: 6734461
    Abstract: A SiC wafer comprises a 4H polytype SiC substrate 2 in which the crystal plane orientation is substantially {03-38}, and a buffer layer 4 composed of SiC formed over this SiC substrate 2. The {03-38} plane forms an angle of approximately 35° with respect to the <0001> axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer 6 on the buffer layer 4. Lattice mismatching between the SiC substrate 2 and the active layer 6 is suppressed by the buffer layer 4. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 11, 2004
    Assignees: Sixon Inc., Kansai Electric Power C.C., Inc., Mitsubishi Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Tsunenobu Kimoto, Hiroyuki Matsunami
  • Patent number: 6727524
    Abstract: There is disclosed a p-n junction diode structure whose electrical characteristics can be affected by the application of pressure or other mechanical stresses that will control sensitivity. The p-n junction consists of two different semiconductor materials, one being of p-type and the other of n-type, both having predetermined crystallographic axes which are fusion bonded together to form a p-n junction. Because of the ability to control the position of the crystallographic axes with respect to one another, one can affect the electrical characteristics of the p-n junction and thereby produce devices with improved operating capabilities such as Zener diodes, tunnel diodes as well as other diodes.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: April 27, 2004
    Assignee: Kulite Semiconductor Products, Inc.
    Inventor: Anthony D. Kurtz
  • Patent number: 6727514
    Abstract: At least one of a semiconductor thin-film for forming a picture display portion and a semiconductor thin-film for forming a peripheral circuit portion, which are accumulated on one common insulative substrate, is constructed with a semiconductor thin-film having a plural number of semiconductor crystalline portions formed to be divided and disposed in a matrix-like, and TFTs are provided in the semiconductor thin-film by bringing those semiconductor single crystal portions into active portions thereof. For that purpose, a crystallization accelerating material is adhered at the position of lattice points of a matrix and is treated with heating process, for forming the single crystal portions disposed in the matrix-like manner, so as to form the TFTs on the surface thereof, thereby completing the thin-film semiconductor integrated circuit device.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Seong-kee Park, Kiyokazu Nakagawa, Nobuyuki Sugii, Shinya Yamaguchi
  • Patent number: 6690068
    Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: February 10, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
  • Patent number: 6680494
    Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: January 20, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Augusto L. Gutierrez-Aitken, Aaron K. Oki, Eric N. Kaneshiro, Dwight C. Streit
  • Publication number: 20040004271
    Abstract: The semiconductor substrate comprises a silicon substrate 10, a silicon germanium layer 12 formed on the silicon substrate; and a silicon layer 14 formed on the silicon germanium layer. At least one of an isotope composition ratio of one Si isotope and an isotope composition ratio of a Ge isotope of at least one of the silicon substrate, the silicon germanium layer and the silicon layer is above 95%. In at least one of the silicon substrate, the silicon germanium layer and the silicon layer, at lest one of an isotope composition ratio of one Si isotope and an isotope composition ratio of one Ge isotope is set higher, whereby the heat can be scattered in the direction horizontal to the substrate plane. Thus, the semiconductor substrate can have higher heat radiation.
    Type: Application
    Filed: June 27, 2003
    Publication date: January 8, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuo Fukuda, Katsushi Hirata
  • Patent number: 6674151
    Abstract: A semiconductor device having trap sites passivated with deuterium has enhanced immunity to hot carrier effects. The trap sites which are passivated with deuterium are encapsulated beneath a barrier film and are therefore resistant to having the deuterium diffuse away from the trap sites during subsequent high temperature processing operations.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: January 6, 2004
    Assignee: Agere Systems Inc.
    Inventors: Sundar S. Chetlur, Pradip K. Roy, Anthony S. Oates, Sidhartha Sen, Jonathan Z-N. Zhou
  • Patent number: 6670638
    Abstract: Disclosed is a polysilicon film adapted for use in a liquid crystal display, and method of manufacturing such film. In manufacturing the film, a native oxide layer formed on a surface of an amorphous silicon film is completely removed by a hydrofluoric acid solution, followed by immersing in an H2O2 solution to newly form an extremely thin oxide layer, prior to a crystallizing processing performed by a laser beam irradiation. The crystallizing processing forms a polysilicon film formed of crystal grains Preferentially oriented on the (111) plane in a direction parallel to the substrate surface, an average crystal grain size being not larger than 300 nm, the standard deviation of the grain sizes being not larger than 30% of the average grain size, and the standard deviation of the roughness being not larger than 10% of the average grain size.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: December 30, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takuo Tamura, Kiyoshi Ogata, Yoichi Takahara, Hironaru Yamaguchi, Yoshinobu Kimura, Makoto Ohkura, Hironobu Abe, Shigeo Shimomura, Masakazu Saitou, Michiko Takahashi
  • Patent number: 6670694
    Abstract: A surface orientation other than a (100) surface orientation is exposed to the surface portion of a silicon substrate having the (100) surface orientation, for example. A silicon epitaxial growth layer is formed only on a region containing a channel forming region on the (100) surface orientation.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: December 30, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisayo Momose
  • Patent number: 6667492
    Abstract: The present invention provides a quantum structure product comprising a substrate having quantum ridges and quantum tips on at least one surface thereof. In some embodiments of the invention quantum ridges may support quantum wires and the quantum tips may support quantum dots. Grooves which separate the quantum ridges and quantum tips from each other may be shallow or deep, and may contain organic molecules, fullerene tubes, and fullerene balls.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: December 23, 2003
    Inventor: Don L. Kendall
  • Patent number: 6657272
    Abstract: An optical receiver having a silicon substrate with a top surface cleaved from a [100] silicon crystallographic plane and a reflector, and a photodetector coupled to the top surface of the silicon substrate, the photodetector being adapted to receive an incoming signal from a fiber.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: December 2, 2003
    Assignee: Triquint Technology Holding Co.
    Inventors: Jing-Hua He, Muhammad Arif, Rao Yelamarty, Hak Byun, Christina Arnold
  • Patent number: 6657259
    Abstract: The present invention provides FinFETs on the same substrate utilizing various crystal planes for FET current channels in order to optimize mobility and/or to reduce mobility. An embodiment of the present invention provides a substrate having a surface oriented on a first crystal plane that enables subsequent crystal planes for channels to be utilized. A first transistor is also provided having a first fin body. The first fin body has a sidewall forming a first channel, the sidewall oriented on a second crystal plane to provide a first carrier mobility. A second transistor is also provided having a second fin body. The second fin body has a sidewall forming a second channel, the sidewall oriented on a third crystal plane to provide a second carrier mobility that is different from the first carrier mobility.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: David M. Fried, Edward J. Nowak
  • Patent number: 6653663
    Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: November 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masahiro Ishida
  • Patent number: 6639280
    Abstract: A laminated substrate is formed by laminating a device formation layer made of single crystalline semiconductor on a supporting substrate made of single crystalline semiconductor via an insulating layer with making one direction of a crystallographic axis of the device formation layer be shifted from a corresponding direction of a crystallographic axis of the supporting substrate. Semiconductor devices are formed in the device formation layer within a plurality of areas divided by scribe lines extending to a direction being parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved. The laminated substrate is split into a plurality of chips by cleaving the supporting substrate along the scribe lines. A semiconductor device can easily be split into chips even if a moving direction of carrier and an extending direction of wiring are shifted from an easy-cleaved direction of a crystallographic axis.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: October 28, 2003
    Assignee: Fujitsu Limited
    Inventors: Shinji Sugatani, Satoshi Sekino