Multiple Layers Patents (Class 257/635)
  • Patent number: 7968187
    Abstract: A composite is provided, comprising a substrate and a film on the substrate. The film has an RMS surface roughness of 25 nm to 500 nm, a film coverage of 25% to 60%, a surface energy of less than 70 dyne/cm; and a durability of 10 to 5000 microNewtons. Depending on the particular environment in which the film is to be used, a durability of 10 to 500 microNewtons may be preferred. A film thickness 3 to 100 times the RMS surface roughness of the film is preferred.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 28, 2011
    Assignee: Integrated Surface Technologies
    Inventors: Jeff Chinn, W. Robert Ashurst, Adam Anderson
  • Patent number: 7960826
    Abstract: A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile hydrophobic film. The ILD layer further includes a low-k dielectric layer, and the single tensile hydrophobic film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: June 14, 2011
    Assignee: United Microelectronics Corp.
    Inventor: Chin-Hsiang Lin
  • Publication number: 20110133313
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Inventors: Vishwanathan Rangarajan, Andrew Antonelli, Bart van Schravendijk
  • Patent number: 7955994
    Abstract: An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: June 7, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Noriyoshi Suzuki
  • Publication number: 20110121436
    Abstract: Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.
    Type: Application
    Filed: February 1, 2011
    Publication date: May 26, 2011
    Inventors: Michael P. Chudzik, Rashmi Jha, Naim Moumen, Keith Kwong Hon Wong, Ying H. Tsang
  • Patent number: 7936050
    Abstract: A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: May 3, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Yong Wook Shin
  • Patent number: 7927971
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: April 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen, Koji Dairiki, Takuya Tsurume
  • Patent number: 7923384
    Abstract: In a formation method of a porous insulating film by supplying at least organosiloxane and an inert gas to a reaction chamber and forming an insulating film by a plasma vapor deposition method, a partial pressure of the organosiloxane in the reaction chamber is changed by varying a volume ratio of the organosiloxane and the inert gas to be supplied during deposition. Thus, the dielectric constant of the insulating film in the semiconductor device is reduced while the adhesion of the insulating film with other materials is improved. It is desirable that the organosiloxane be cyclic organosiloxane including at least silicon, oxygen, carbon, and hydrogen, and that the total pressure of the reaction chamber be constant during deposition.
    Type: Grant
    Filed: November 24, 2006
    Date of Patent: April 12, 2011
    Assignee: NEC Corporation
    Inventors: Munehiro Tada, Naoya Furutake, Tsuneo Takeuchi, Yoshihiro Hayashi
  • Patent number: 7919835
    Abstract: The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes: a semiconductor substrate having a first surface and a second surface facing each other; a first insulating film formed on the first surface of the semiconductor substrate and having a specific permittivity of 4 or higher; a circuit constituent element formed on the first surface of the semiconductor substrate and covered with the first insulating film); a contact plug formed in the first insulating film and electrically connected to the circuit constituent element; a through-substrate contact plug penetrating through the semiconductor substrate and the first insulating film; a second insulating film formed on the first insulating film and having a specific permittivity of 3.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: April 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Patent number: 7911026
    Abstract: Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 22, 2011
    Assignee: Qimonda AG
    Inventors: Florian Binder, Thomas Haneder, Judith Lehmann, Manfred Schneegans, Grit Sommer
  • Patent number: 7911037
    Abstract: A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and signal trace trenches are formed into the substrate body using LASER ablation, or other ablation, techniques. Using ablation techniques to form the bias and signal trace trenches allows for extremely accurate control of the depth, width, shape, and horizontal displacement of the bias and signal trace trenches. As a result, the distance between the bias traces and the signal traces eventually formed in the trenches, and therefore the electrical properties, such as impedance and noise shielding, provided by the bias traces, can be very accurately controlled.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: March 22, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Jon Hiner, Nozad Osman Karim
  • Publication number: 20110062560
    Abstract: Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 ? and about 350 ?. The cap layer may be formed using a low temperature CVD process that is controlled for density by adjusting the amount of silicon precursor in the gas-phase. In some embodiments, the cap layer is deposited on the BPSG layer followed immediately by the BPSG film deposition prior to any annealing of the BPSG layer. The cap layer may prevent dopant out-diffusion and/or out-gassing during storage and high-temperature annealing, and moisture penetration into the BPSG layer, as well as suppress defect nucleation on the as-deposited BPSG surface and defect formation during high temperature annealing, while still allowing flow ability of the BPSG layer. Other embodiments are also described.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Inventor: Yuri Sokolov
  • Patent number: 7907434
    Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: March 15, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasurou Matsuzaki, Yasuharu Sato, Tadao Aikawa, Masafumi Yamazaki, Takaaki Suzuki
  • Patent number: 7902641
    Abstract: The present invention relates to a semiconductor device. The semiconductor device includes a fluorocarbon film formed on a substrate and a film containing metal formed on the fluorocarbon film, wherein the content amount of fluorine atom on the fluorocarbon film, which contacts the film containing metal, is in a predetermined range.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: March 8, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Yoshiyuki Kikuchi
  • Patent number: 7902083
    Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: March 8, 2011
    Assignee: Raytheon Company
    Inventors: John M. Bedinger, Michael A. Moore, Robert B. Hallock, Kamal Tabatabaie Alavi, Thomas E. Kazior
  • Publication number: 20110042790
    Abstract: A method of double patterning a semiconductor structure with a single material which after patterning becomes a permanent part of the semiconductor structure. More specifically, a method to form a patterned semiconductor structure with small features is provided which are difficult to obtain using conventional exposure lithographic processes. The method of the present invention includes the use of patternable low-k materials which after patterning remain as a low-k dielectric material within the semiconductor structure. The method is useful in forming semiconductor interconnect structures in which the patternable low-k materials after patterning and curing become a permanent element, e.g., a patterned interlayer low-k material, of the interconnect structure.
    Type: Application
    Filed: August 24, 2009
    Publication date: February 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Qinghuang Lin
  • Patent number: 7888741
    Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Alfred Grill, Vishnubhai V. Patel, Darryl D. Restaino
  • Patent number: 7871687
    Abstract: A microstructure device is made by processing a material substrate consisting of e.g. a first process layer, a second process layer and a middle layer arranged between the first and the second process layers. The microstructure device includes a first structural part and a second structural part that has a portion facing the first structural part via a gap. The first and the second structural parts are connected to each other by a connecting part extending across the gap. This connecting part is formed in the first process layer to be in contact with the middle layer. The microstructure device also includes a protective part extending from the first structural part toward the second structural part or vice versa. The protective part is formed in the first or second process layer to be in contact with the middle layer.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: January 18, 2011
    Assignee: Fujitsu Limited
    Inventors: Norinao Kouma, Yoshihiro Mizuno, Hisao Okuda, Hiromitsu Soneda, Tsuyoshi Matsumoto, Osamu Tsuboi, Ippei Sawaki
  • Patent number: 7868349
    Abstract: A light source apparatus and a fabrication method thereof can prevent light interference between light emitting devices adjacent to each other and increase the luminous efficiency by collecting light emitted from the side of the light emitting device toward the front of a metal stem by forming grooves at a sub-mounts, bonding the light emitting device to the inside of the groove by a flip chip bonding method and forming a reflective layer inside the groove.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: January 11, 2011
    Assignee: LG Electronics Inc.
    Inventors: Geun-Ho Kim, Ki-Chang Song
  • Patent number: 7863116
    Abstract: It is an object of the present invention to provide a highly sophisticated functional IC card that can ensure security by preventing forgery such as changing a picture of a face, and display other images as well as the picture of a face. An IC card comprising a display device and a plurality of thin film integrated circuits; wherein driving of the display device is controlled by the plurality of thin film integrated circuits; a semiconductor element used for the plurality of thin film integrated circuits and the display device is formed by using a polycrystalline semiconductor film; the plurality of thin film integrated circuits are laminated; the display device and the plurality of thin film integrated circuits are equipped for the same printed wiring board; and the IC card has a thickness of from 0.05 mm to 1 mm.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: January 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno, Mai Akiba
  • Publication number: 20100327377
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 7859087
    Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Murata, Hiroaki Ueno, Hidetoshi Ishida, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
  • Patent number: 7855114
    Abstract: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: December 21, 2010
    Assignee: Spansion LLC
    Inventors: Wei Zheng, Mark Randolph, Hidehiko Shiraiwa
  • Publication number: 20100314725
    Abstract: A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 16, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: Shiqun Gu, Arvind Chandrasekaran, Urmi Ray, Yiming Li
  • Patent number: 7851891
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Naohisa Sengoku, Michikazu Matsumoto
  • Patent number: 7843041
    Abstract: A thin-film circuit device includes a substrate and a thin-film circuit layer, disposed on the substrate, having an element region and a low-strength region. The element region includes thin-film elements. The low-strength region extends between an end portion of the thin-film circuit layer and the element region and has a mechanical strength less than that of the surroundings of the low-strength region.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: November 30, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Taimei Kodaira, Sumio Utsunomiya
  • Patent number: 7842385
    Abstract: A coated nano particle and an electronic device using the composite nano particle as an illuminator are provided. The composite nano particle includes a nano particle receiving light and emitting light; and a coating material formed on a surface of the nano particle and having an index of refraction different from that of the nano particle. The coated nano particle is made by coating a surface of the nano particle with a material having an index of refraction, which has an intermediate value between an index of refraction of a matrix and an index of refraction of the nano particle as an illuminator, with a predetermined thickness. The light emitted from the nano particle is efficiently transferred to the outside as the light reflected from the matrix and absorbed by the nano particle is suppressed. Therefore, a luminous efficiency of the illuminator is improved, and an electronic device using the illuminator is provided.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: November 30, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Eun-joo Jang, Shin-ae Jun
  • Patent number: 7834426
    Abstract: The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Jun-Fei Zheng, George Chen, Wilman Tsai
  • Patent number: 7834399
    Abstract: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Thomas S. Kanarsky, Qiqing Ouyang, Haizhou Yin
  • Patent number: 7833891
    Abstract: A semiconductor device and method is provided that has an oxygen diffusion barrier layer between a high-k dielectric and BOX. The method includes depositing a diffusion barrier layer on a BOX layer and gate structure and etching a portion of the diffusion barrier layer from sidewalls of the gate structure. The method further includes depositing a high-k dielectric on the diffusion barrier layer and the gate structure.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kagguo Cheng, Bruce B. Doris
  • Patent number: 7829978
    Abstract: An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: November 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Chih Chen, Shih-Hsieng Huang, Chih-Hao Wang
  • Patent number: 7808806
    Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 5, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasurou Matsuzaki, Yasuharu Sato, Tadao Aikawa, Masafumi Yamazaki, Takaaki Suzuki
  • Publication number: 20100244206
    Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Applicant: International Business Machines Corporation
    Inventors: Huiming Bu, Michael P. Chudzik, Wei He, Rashmi Jha, Young-Hee Kim, Siddarth A. Krishnan, Renee T. Mo, Naim Moumen, Wesley C. Natzle
  • Publication number: 20100244207
    Abstract: Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Mariko Takayanagi
  • Patent number: 7781268
    Abstract: A manufacturing method for an array substrate, comprising forming a gate metal on a base substrate, patterning the gate metal to form a gate part having a gate electrode, a gate line and a gate pad. Then, a gate insulating layer, an active layer and a data metal are sequentially formed on the base substrate to cover the gate part. The data metal is patterned to form a data part having a data electrode, a data pad and a pixel electrode. Then, the exposed portion of the active layer is removed, and the exposed portion of the gate insulation layer is removed. When the data electrode is divided into a source electrode and a drain electrode, a switching device is completed.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Seong Byun, Ho-Min Kang, Bae-Hyoun Jung
  • Publication number: 20100193919
    Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, forming a main mask over the dielectric layer, the main mask comprising a plurality of main mask openings arranged in a regular pattern extending over the dielectric layer, using a selector mask to select some of the plurality of main mask openings and removing portions of the dielectric layer through the selected some of the plurality of main mask openings to provide openings extending through the dielectric layer to the layer.
    Type: Application
    Filed: July 27, 2007
    Publication date: August 5, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Scott Warrick, Massud Abubaker Aminpur
  • Patent number: 7767589
    Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: August 3, 2010
    Assignee: Raytheon Company
    Inventors: John M. Bedinger, Michael A. Moore, Robert B. Hallock, Kamal Tabatabaie Alavi, Thomas E. Kazior
  • Publication number: 20100181655
    Abstract: A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 22, 2010
    Applicants: Board of Regents, The University of Texas System, Texas Instruments, Inc.
    Inventors: Luigi Colombo, Sanjay Banerjee, Seyoung Kim, Emanuel Tutuc
  • Publication number: 20100176495
    Abstract: A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; and a semiconductor layer formed on the upper insulating layer.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 15, 2010
    Applicant: International Business Machines Corporation
    Inventors: Jack O. Chu, Robert H. Dennard, John A. Ott, Devendra K. Sadana, Leathen Shi
  • Publication number: 20100176453
    Abstract: A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 15, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Dennard, David R. Greenberg, Amlan Majumdar, Leathen Shi, Jeng-Bang Yau
  • Publication number: 20100176496
    Abstract: To provide a material for forming an exposure light-blocking film which includes at least one of a silicon compound expressed by the following structural formula (1) and a silicon compound expressed by the following structural formula (2), wherein at least one of R1 and R2 is replaced by a substituent capable of absorbing exposure light.
    Type: Application
    Filed: March 22, 2010
    Publication date: July 15, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Yoshihiro Nakata
  • Publication number: 20100164074
    Abstract: The present invention describes a method including: providing a substrate; stacking interlevel dielectric layers over said substrate, and separating said interlevel dielectric layers with a dielectric separator layer.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventor: Sean King
  • Publication number: 20100155908
    Abstract: A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Inventor: Jian-Bin Shiu
  • Patent number: 7737052
    Abstract: A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: June 15, 2010
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc., Applied Materials, Inc.
    Inventors: Ritwik Bhatia, Griselda Bonilla, Alfred Grill, Joshua L. Herman, Son Van Nguyen, E. Todd Ryan, Hosadurga Shobha
  • Publication number: 20100140705
    Abstract: An electronic device including in any sequence: (a) a semiconductor layer; and (b) a dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a lower concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to the semiconductor layer.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 10, 2010
    Applicant: XEROX CORPORATION
    Inventors: Yiliang Wu, Paul F. Smith
  • Publication number: 20100140756
    Abstract: An object of the present invention is to provide a semiconductor thin film device which employs a silicon oxide thin film having an equivalent level of high insulating performance to those currently used in electronic devices, through a low-temperature printing process on a plastic substrate having plasticity or other types of substrates at a temperature equal to or lower than the heat resistant temperature of the substrate, and to provide a method for forming the device. The semiconductor thin film device is formed as follows: a coating film of a silicon compound including a silazane structure or a siloxane structure is formed on a plastic substrate having plasticity; the coating film is converted into a silicon oxide thin film; and the thin film is utilized as part of an insulating layer or a sealing layer.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 10, 2010
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Kenji Kozasa, Toshihide Kamata
  • Publication number: 20100117204
    Abstract: The present invention may be a semiconductor device including of a fluorinated insulating film and a SiCN film deposited on the fluorinated insulating film directly, wherein a density of nitrogen in the SiCN film decreases from interface between the fluorinated insulating film and the SiCN film. In the present invention, the SiCN film that is highly fluorine-resistant near the interface with the CFx film and has a low dielectric constant as a whole can be formed as a hard mask.
    Type: Application
    Filed: July 24, 2008
    Publication date: May 13, 2010
    Applicant: Tokyo Electron Limited
    Inventors: Takaaki Matsuoka, Kohei Kawamura
  • Patent number: 7714414
    Abstract: In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad and conducting ion implantation to recover dielectric properties of the insulation layer.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: May 11, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiu-Mei Yu, Ken-Shen Chou, Shun-Liang Hsu
  • Publication number: 20100090250
    Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.
    Type: Application
    Filed: December 14, 2009
    Publication date: April 15, 2010
    Applicant: PANASONIC CORORATION
    Inventors: Tomohiro MURATA, Hiroaki Ueno, Hidetoshi Ishida, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
  • Patent number: RE41948
    Abstract: A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a low dielectric constant film, a second wiring layer formed in the second insulating film and coupled to the first wiring layer through a first connection section, and a third insulating film formed above the second wiring layer and the second insulating film and serving as one of an interlayer insulating film and a passivation film, and at least one of the first and third insulating films being one of a film formed mainly of SiON, a film formed mainly of SiN, and a laminated film being the films formed mainly of SiON or SiN respectively.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: November 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Noriaki Matsunaga