With Discontinuous Or Varying Thickness Layer (e.g., Layer Covers Only Selected Portions Of Semiconductor) Patents (Class 257/638)
  • Patent number: 10586013
    Abstract: Techniques are provided for calibrating physical directed self-assembly (DSA) models. For example, an experimental DSA process is performed using a block copolymer (BCP) material and a DSA guiding pattern with a predefined defect formed as part of the DSA guiding pattern. A difference in size (e.g., shrinkage) is determined between a size of the predefined defect of the DSA guiding pattern and a remaining size of a morphological defect in the BCP material as assembled at a completion of the experimental DSA process. The difference in size is utilized as calibration data in a DSA simulation system to calibrate a simulated physical DSA model which defines a simulated DSA process that corresponds to the experimental DSA process. The simulated physical DSA model defines a simulated guiding pattern with a programmed defect, which corresponds to the DSA guiding pattern and the predefined defect.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kafai Lai
  • Patent number: 10164109
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang
  • Patent number: 9391024
    Abstract: Embodiments of the disclosure generally provide multi-layer dielectric stack configurations that are resistant to plasma damage. Methods are disclosed for the deposition of thin protective low dielectric constant layers upon bulk low dielectric constant layers to create the layer stack. As a result, the dielectric constant of the multi-layer stack is unchanged during and after plasma processing.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 12, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bo Xie, Kang Sub Yim, Cheng Pan, Sure Ngo, Taewan Kim, Alexandros T. Demos
  • Patent number: 9299380
    Abstract: Provided herein is a method including oxidizing tops of features of a patterned magnetic layer to form oxidized tops of the features; removing an excess of an applied first protective material down to at least the oxidized tops of the features to form a planarized layer; and applying a second protective material over the planarized layer.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: March 29, 2016
    Assignee: Seagate Technology LLC
    Inventors: Michael R. Feldbaum, Koichi Wago, Bin Lu, David S. Kuo
  • Patent number: 8987800
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
  • Patent number: 8963330
    Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: John Smythe
  • Patent number: 8937369
    Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
  • Patent number: 8895359
    Abstract: A semiconductor chip (1) is flip-chip mounted on a circuit board (4) with an underfill resin (6) interposed between the semiconductor chip (1) and the circuit board (4) and a container covering the semiconductor chip (1) is bonded on the circuit board (4). At this point, the semiconductor chip (1) positioned with the underfill resin (6) interposed between the circuit board (4) and the semiconductor chip (1) is pressed and heated by a pressure-bonding tool (8); meanwhile, the surface of the underfill resin (6) protruding around the semiconductor chip (1) is pressed by the pressure-bonding tool (8) through a film (13) on which a surface unevenness is formed in a periodically repeating pattern, so that a surface unevenness (16a) is formed. The inner surface of the container covering the semiconductor chip (1) is bonded to the surface unevenness (16a) on the surface of the underfill resin.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomura, Kazumichi Shimizu, Kentaro Kumazawa
  • Patent number: 8836088
    Abstract: A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mei-Hsuan Lin, Chih-Hsun Lin, Chih-Kang Chao, Ling-Sung Wang
  • Patent number: 8766410
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Patent number: 8669645
    Abstract: Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Timothy A. Quick, J. Neil Greeley
  • Patent number: 8653666
    Abstract: A semiconductor storage device comprises a peripheral circuit region including a wiring layer having wiring patterns, a cavity formed in a non-wiring region between the wiring patterns of the wiring layer, and an insulating film forming at least a part of a wall defining the cavity, and a memory cell region.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: February 18, 2014
    Inventor: Keizo Kawakita
  • Patent number: 8614500
    Abstract: According one embodiment, a film forming apparatus includes a stage, a coating section, a vapor supply section, a blower section, and a controller. On the stage, an coating target is placed. The coating section applies a material to a predetermined region on the coating target placed on the stage to form a coating film. The vapor supply section generates solvent vapor capable of dissolving the coating film. The blower section blows the solvent vapor generated by the vapor supply section onto the coating film on the coating target placed on the stage. The controller controls an amount of the solvent vapor to be blown by the blower section so that: the coating film is dissolved; viscosity in a part of the coating film on a surface layer side is lower than that in a part thereof on the coating target side; and the viscosity in the part on the surface layer side and the viscosity of the coating target side take such values that prevent the coating film on the coating target from spreading.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Sato, Hiroyasu Kondo, Naoaki Sakurai, Katsuyuki Soeda, Kenichi Ooshiro, Shuichi Kimura
  • Patent number: 8552537
    Abstract: A semiconductor device according to an embodiment, includes a dielectric film and an Si semiconductor part. The dielectric film is formed by using one of oxide, nitride and oxynitride. The Si semiconductor part is arranged below the dielectric film, having at least one element of sulfur (S), selenium (Se), and tellurium (Te) present in an interface with the dielectric film, and formed by using silicon (Si).
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Satoshi Itoh, Hideyuki Nishizawa
  • Patent number: 8487412
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 8455985
    Abstract: An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 4, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-hee Han, Sang-hoon Ahn, Eunkee Hong
  • Patent number: 8441077
    Abstract: A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: May 14, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Sam Yang
  • Patent number: 8394668
    Abstract: Oxide thin film, electronic devices including the oxide thin film and methods of manufacturing the oxide thin film, the methods including (A) applying an oxide precursor solution comprising at least one of zinc (Zn), indium (In) and tin (Sn) on a substrate, (B) heat-treating the oxide precursor solution to form an oxide layer, and (C) repeating the steps (A) and (B) to form a plurality of the oxide layers.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: March 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Baek Seon, Myung-Kwan Ryu, Kyung-Bae Park, Sang-Yoon Lee, Bon-Won Koo
  • Patent number: 8350365
    Abstract: A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: January 8, 2013
    Assignee: Xilinx, Inc.
    Inventors: Yun Wu, Hong-Tsz Pan, Qi Lin, Bang-Thu Nguyen
  • Patent number: 8274071
    Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Mong-Song Liang, Tze-Liang Lee, Jr.-Hung Li
  • Patent number: 8132709
    Abstract: A semiconductor device comprises a semiconductor element having electrodes, a metal member, wires that electrically connect the semiconductor element and the metal member and/or electrodes within the semiconductor element, wherein the wires constitute at least a first wire loop and a second wire loop, the first wire loop is bonded at one end to a first bonding point and at the other end to a second bonding point, and has a flat part which includes the surface of a boll part and the wire located contiguously the ball part surface, and the second wire loop connects the surface of the ball part and a third bonding point.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: March 13, 2012
    Assignee: Nichia Corporation
    Inventors: Tadao Hayashi, Yoshiharu Nagae
  • Patent number: 8120184
    Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventor: John Smythe
  • Patent number: 8080485
    Abstract: A method of forming a semiconductor structure comprises providing a substrate and forming an insulator layer on the substrate. A first film is formed on the insulator layer. Thus, the first film can correspond to a device region of the semiconductor structure. A second film, comprising a second material that is different from the first material, is also formed on the insulator layer adjacent to the first film. The second material can comprise an isolation material (e.g., an oxide and/or nitride material) and can, for example comprise the same dielectric material as the insulator layer (e.g., silicon dioxide). The second film can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure. The second film is specifically formed with a first section having a first thickness and a second section having a second thickness that is different from the first thickness.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7999328
    Abstract: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densification of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: August 16, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Sukesh Sandhu, Gurtej Sandhu
  • Patent number: 7985633
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Patent number: 7973391
    Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, Gary Yasumura
  • Patent number: 7964917
    Abstract: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventor: Susumu Akamatsu
  • Patent number: 7939915
    Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: May 10, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Hok Min Ho, Ching Tien Ma, Woei Ji Song
  • Patent number: 7932542
    Abstract: A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: April 26, 2011
    Assignee: Infineon Technologies AG
    Inventors: Joerg Berthold, Winfried Kamp, Fritz Rothacher
  • Patent number: 7928512
    Abstract: A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: April 19, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Lang
  • Patent number: 7928537
    Abstract: A functional device having, on a substrate, a pair of electrodes, a functional layer which is sandwiched between the electrodes and has an output that varies in accordance with an applied electric current, and a terminal arranged to apply an electric current to at least one of the electrodes, wherein an insulator is arranged between the electrodes and the density of the insulator decreases as the distance from the terminal increases, or wherein at least one of the electrodes has a notch section, and the ratio of the area of the notch section to the area of the electrode decreases as the distance from the terminal increases. This is an improved functional device which is excellent in production suitability and gives a uniform in-plane output, and can be rendered, in particular, an organic electroluminescence device.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: April 19, 2011
    Assignee: Fujifilm Corporation
    Inventors: Toshiro Takahashi, Kazuo Hakamata
  • Patent number: 7902083
    Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: March 8, 2011
    Assignee: Raytheon Company
    Inventors: John M. Bedinger, Michael A. Moore, Robert B. Hallock, Kamal Tabatabaie Alavi, Thomas E. Kazior
  • Patent number: 7898065
    Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7879639
    Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: February 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yao Ko, Chung-Wei Chang, Han-Chi Liu, Shou-Gwo Wuu
  • Patent number: 7868317
    Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: January 11, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Mong-Song Liang, Tze-Liang Lee, Jr-Hung Li
  • Patent number: 7851891
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Naohisa Sengoku, Michikazu Matsumoto
  • Patent number: 7843041
    Abstract: A thin-film circuit device includes a substrate and a thin-film circuit layer, disposed on the substrate, having an element region and a low-strength region. The element region includes thin-film elements. The low-strength region extends between an end portion of the thin-film circuit layer and the element region and has a mechanical strength less than that of the surroundings of the low-strength region.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: November 30, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Taimei Kodaira, Sumio Utsunomiya
  • Patent number: 7829400
    Abstract: In fabricating a semiconductor device, an element forming surface formation step of forming a plurality of element forming surfaces of different heights on a semiconductor layer to have different levels, a semiconductor element formation step of forming a plurality of semiconductor elements and, one in each of a corresponding number of regions of the semiconductor layer, each region including an associated one of the plurality of element forming surfaces, a level-difference compensation insulating film formation step of forming a level-difference compensation insulating film on the semiconductor layer to cover the semiconductor elements and have a surface with different levels along the element forming surfaces, a release layer formation step of forming a release layer in the semiconductor layer by ion-implanting a peeling material through the level-difference compensation insulating film into the semiconductor layer, and a separation step of separating part of the semiconductor layer along the release layer
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: November 9, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Masao Moriguchi
  • Patent number: 7777294
    Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: August 17, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Masatoshi Taya
  • Patent number: 7767589
    Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: August 3, 2010
    Assignee: Raytheon Company
    Inventors: John M. Bedinger, Michael A. Moore, Robert B. Hallock, Kamal Tabatabaie Alavi, Thomas E. Kazior
  • Patent number: 7759238
    Abstract: The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to a gate to be formed; removing the exposed first oxide layer; immersing the substrate into deionized water to grow a second oxide layer; forming a polysilicon layer on the surfaces of the first oxide layer and the second oxide layer; and etching the polysilicon layer to form a gate. The method for fabricating semiconductor device according to the present invention, which is capable of adjusting the thickness of gate oxide layer, can control the thickness of gate oxide layer precisely to satisfy the requirement for different threshold voltages.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: July 20, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Tai Chiang Chen, Xin Wang
  • Patent number: 7745909
    Abstract: Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: June 29, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7744996
    Abstract: An adhesive structure for use in a liquid crystal display (LCD) and a method for manufacturing the adhesive structure are provided. The adhesive structure includes a releasing paper which is provided with two anisotropic conductive films (ACFs) thereon. When the adhesive structure is attached onto the LCD, the two ACFs can be simultaneously attached onto the glass substrate of the LCD for connecting the integrated circuit and flexible printed circuit, respectively.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: June 29, 2010
    Assignee: AU Optronics Corp.
    Inventor: Chih-Chia Chen
  • Patent number: 7679166
    Abstract: Disclosed herein are embodiments of a semiconductor structure and an associated method of forming the semiconductor structure with shallow trench isolation structures having selectively adjusted reflectance and absorption characteristics in order to ensure uniform temperature changes across a wafer during a rapid thermal anneal and, thereby, limit variations in device performance. Also disclosed are embodiments of another semiconductor structure and an associated method of forming the semiconductor structure with devices having selectively adjusted reflectance and absorption characteristics in order to either selectively vary the performance of individual devices (e.g., to form devices with different threshold voltages (Vt) on the same wafer) and/or to selectively optimize the anneal temperature of individual devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals).
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7675118
    Abstract: A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Yaocheng Liu, William K. Henson
  • Patent number: 7652354
    Abstract: Disclosed is a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an insulating layer and a metal interconnection. An insulating layer may include a first layer including fluorine and a second layer including SRO (silicon rich oxide) having a dangling bond. A metal interconnection may be formed over the insulating layer.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: January 26, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Tae Young Lee
  • Patent number: 7629672
    Abstract: A semiconductor device is provided with a semiconductor substrate having circuit elements formed therein, and an insulating protective film formed on the semiconductor substrate. Hydroxyl groups (OH) are attached to a surface of the protective film. As a result, the contact angle between surface of the protective film and a water droplet is less than or equal to 40 degrees.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: December 8, 2009
    Assignees: Toyota Jidosha Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kanata, Shinichi Umekawa, Koji Terada, Yasushi Takahashi
  • Patent number: 7612433
    Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: November 3, 2009
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
  • Patent number: 7566950
    Abstract: The present invention provides a method for fabricating a flexible pixel array substrate as follows. First, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that between the release layer and the polymer film. The polymer film is formed by spin coating a polymer monomer and performing a curing process to form a polymer layer. Afterwards, a pixel array is formed on the polymer film. The polymer film with the pixel array formed thereon is separated from the rigid substrate.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: July 28, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Chin-Jen Huang, Jung-Fang Chang, Yih-Rong Luo, Yu-Hung Chen
  • Patent number: RE44303
    Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: June 18, 2013
    Assignee: Raytheon Company
    Inventors: John Bedinger, Michael A. Moore, Robert B Hallock, Kamal Tabatabaie, Thomas E. Kazior