Abstract: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.

Abstract: A method for forming a rough ruthenium-containing layer on the surface of a substrate assembly includes providing a ruthenium-containing precursor into the reaction chamber. A rough ruthenium layer may be deposited on the surface of the substrate assembly at a rate of about 100 Å/minute to about 500 Å/minute using the ruthenium-containing precursor. Further, a rough ruthenium oxide layer may be formed by providing a ruthenium-containing precursor and an oxygen-containing precursor into the reaction chamber to deposit the rough ruthenium oxide layer on the surface of the substrate assembly at a rate of about 100 Å/minute to about 1200 Å/minute. An anneal of the layers may be performed to further increase the roughness. In addition, conductive structures including a rough ruthenium layer or a rough ruthenium oxide layer are provided. Such layers may be used in conjunction with non-rough ruthenium and/or non-rough ruthenium oxide layers to form conductive structures.

Abstract: A silicon oxide film with a film thickness of 5 to 7 nm is formed on a first region, a silicon oxynitride film with a film thickness of 2 to 3 nm, and a nitrogen concentration of 1 to 3 atom % is formed on a second region, and a silicon oxynitride film with a film thickness of 1 to 2 nm, and a nitrogen concentration of 3 to 5 atom % is formed on a third region on a silicon substrate. Then, radical nitriding is applied to the silicon oxide film, and the silicon oxynitride films.

Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over a wafer so that an edge position of the first low dielectric constant film aligns with a first position along the circumference of the wafer. Then, a first protection layer having a gas permeability lower than that of the first low dielectric constant film is formed over the first low dielectric constant film and the wafer so that an edge of the first protection layer aligns with a second position that is located outside the first position. Then, a second low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over the first protection layer so that an edge of the second low dielectric constant film is located at the first position.

Abstract: The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming such a structure.

Abstract: A new multilayer dielectric film for improving dielectric constant and thermal stability of gate dielectrics is provided. The multilayer dielectric film comprises a first layer formed of a metal oxide material having a high dielectric constant, and a second layer formed on the first layer. The second layer is formed of a metal silicate material having a dielectric constant lower than the dielectric constant of the first layer. A semiconductor transistor incorporating the multilayer dielectric film is also provided.

Abstract: A semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, a layer of undoped silicate glass disposed on the dielectric layer, a layer of borophosphorous silicate glass on the layer of undoped silicate glass, and a planar dielectric layer disposed on the layer of borophosphorous silicate glass, the layers of undoped silicate glass, borophosphorous silicate glass, and planar dielectric together forming a pre-metal dielectric stack. The planar dielectric may include plasma-enhanced tetraethyl orthosilicate.

Abstract: A method for depositing a silicon oxycarbide hard mask on a low k dielectric layer is provided. Substrates containing a silicon oxycarbide hard mask on a low k dielectric layer are also disclosed. The silicon oxycarbide hard mask may be formed by a processing gas comprising a siloxane.

Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

Abstract: The present invention relates to nanoporous dielectric films and to a process for their manufacture. A substrate having a plurality of raised lines on its surface is provided with a relatively high porosity, low dielectric constant, silicon containing polymer composition positioned between the raised lines and a relatively low porosity, high dielectric constant, silicon containing composition positioned on the lines.

Abstract: A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings and field plates provides a resulting guard ring structure which allows for such device to achieve higher voltage applications.

Abstract: A photomask and method of patterning a photosensitive layer using a photomask, the photomask including a substrate and a film coupled to substrate. The film is etched with a phase shifted assist feature, a low aspect ratio assist feature or phase shifted low aspect primary features.

Abstract: Disclosed is a thin film transistor (TFT) for a liquid crystal display (LCD) and a method for manufacturing the same that allows the number of photomasks used in a photolithography process to be decreased as compared to conventional methods. A passivation film is formed as a single layered organic insulating film, and the number of needed exposure steps is reduced, so as to decrease the number of needed photomask sheets and thereby improve the efficiency of the TFT production process. Applications of the disclosed method include reflection and transmission composite type LCDs as well as a reflection type LCD.

Abstract: Integrated circuitry includes a semiconductive substrate, an insulative material over the semiconductive substrate, and a series of alternating first and second conductive lines, the first and second lines being spaced and positioned laterally adjacent one another over the insulating layer. At least some of the laterally adjacent conductive lines may have different cross-sectional shapes in a direction perpendicular to the respective line. Alternatively, or in addition, individual second series conductive lines may be spaced from adjacent first series conductive lines a distance that is less than a minimum width of the first series lines.

Abstract: The semiconductor device comprises a silicon substrate, a first metal pattern layer which is deposited on the silicon substrate, an inter metal dielectric which is deposited on the silicon substrate including the first metal pattern layer and on which a connection hole is formed to partially expose the upper surface of the first metal pattern layer, a second metal pattern layer which is deposited on the inter metal dielectric and electrically interconnected to the first metal pattern layer by the connection hole, and a passivation layer which coats the silicon substrate including the second metal pattern layer and has an opening to partially expose the second metal pattern layer for electrically connecting the semiconductor device to external circuitry. The first metal pattern layer comprises a Ti/TiN layer, an Al layer, and a TiN layer, and the second metal pattern layer comprises a Ti layer and an Al layer.

Abstract: Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines while the films over the metal lines have higher dielectric constant due to removal of carbon from these films during ion bombardment. Films over the metal lines have properties similar to silicon dioxide and are ready for sequential integration processes.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A method for manufacturing an electronic component includes forming an aggregate electronic component including a plurality of electronic components and dividing the aggregate electronic component to separate the plurality of electronic components to form individual electronic components. Through-holes are formed in a laminated body providing an aggregate electronic component wherein via-hole conductors are arranged so as not pass through the aggregate electronic component in a thickness direction thereof, the via-hole conductors are divided by the through-holes, and each divided portion provides an external terminal electrode. Then, by dividing the laminated body along the dividing lines passing through the through-holes, a plurality of individual electronic components are produced.

Abstract: An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

Abstract: A semiconductor device includes, on a protective film laminated on a circuit principal part, (i) a light blocking film provided so as to cover the circuit principal part, (ii) an aluminum oxide film provided so as to completely cover the light blocking film, and (iii) a light-blocking upper wiring provided on the aluminum oxide film. An attempt to exfoliate the light blocking film or the light blocking upper wiring causes the resistance-detection-use upper wiring to break or thin, thereby resulting in an increase in the resistance of the resistance-detection-use wiring. The increase in the resistance is detected by the resistance detecting circuit part, and malfunction or inoperativeness of the circuit principal part is caused in response of detection. By so doing, the circuit principal part can be protected from analysis.

Abstract: This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.

Abstract: A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate insulating film. The upper part is longer than the lower part in a lengthwise direction of a gate electrode. The first insulating film is interposed between the lower surface of the upper part of the gate electrode and a semiconductor substrate. The first insulating film surrounds at least the sides of the lower part of the gate electrode, which face drain and source regions, and having parts interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate and made thicker than the other parts.

Abstract: Novel semiconductor devices containing a discontinuous cap layer and possessing a relatively low dielectric constant are provide herein. The novel semiconductor devices includes at least a substrate, a first dielectric layer applied on at least a portion of the substrate, a first set of openings formed through the dielectric layer to expose the surface of the substrate so that a conductive material deposited within and filling the openings provides a first set of electrical contact conductive elements and a discontinuous layer of cap material covering at least the top of the conductive elements to provide a first set of discontinuous cap elements. Methods for forming the semiconductor devices are also provided.

Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.

Abstract: An epitaxial wafer comprises epitaxial layers 3-6 formed on a main surface of a compound semiconductor single crystal substrate 2, wherein the epitaxial layer 3a on the main surface is exposed in a back surface of the compound semiconductor single crystal substrate 2, and an exposed portion 8 of the epitaxial layer 3a has a carrier concentration of 1×1017 cm−3 to 2×1018 cm−3. The epitaxial wafer provides for an ultra thin type light emitting diode where generation of ohmic electrode failure is suppressed.

Abstract: It is an object to provide an insulating film which enables not only to obtain a good film quality but to achieve an excellent filling property, thick film formation and planarization simultaneously, and to provide an insulating film forming coating solution for forming the insulating film, and to provide a method of manufacturing the insulating film. An insulating film forming coating solution containing as a main component a solution of a polymer obtained by co-hydrolysis of trialkoxysilane expressed by a general formula, SiH(OR)3, methyltrialkoxysilane expressed by a general formula, SiCH3(OR)3, and tetraalkoxysilane expressed by a general formula, Si(OR)4 is coated on a semiconductor substrate (1) having a step portion, and after it is heated and dried in an inert gas atmosphere, an insulating film (6) which is composed of a silane-derived compound expressed by a general formula, SiHx(CH3)yO2−(x+y)/2, where, 0<x<1, 0<y<1, x+y≦1 is formed.

Abstract: A semiconductor package which includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

Abstract: A substrate, preferably silicon, or other suitable material has a layer of glass material disposed thereon. The glass material of the present disclosure has a substantially increased uniformity due to the reduction in bubbles as well as a relatively smooth top surface. By virtue of the reduction in the number and size of the bubbles in the glass the dielectric properties of the glass are more uniform. Additionally, the fact that the surface of the glass is much more smooth reduces the potential of prior structures to have an unacceptably thin glass layer due to the need to grind the surface smooth.

Abstract: A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

Abstract: Varying the porosity through the thickness of a porous silicon layer allows conflicting needs to be met by the same layer: a low porosity surface layer allows a high-quality epitaxial layer of silicon to be grown, or can provide structural support, while greater porosity in other portions of the layer increases circuit isolation and provides stress relief between layers.

Abstract: In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is non-conformal in that the oxide is thicker over the gate and over the substrate than it is on the side of the gate. A second non-conformal oxide is provided over the first non-conformal oxide. The second oxide is annealed in a boron-containing atmosphere, and the first oxide prevents boron diffusion from the second oxide into the gate and substrate. The second oxide may then serve as an etch stop, a CMP stop, or both.

Abstract: A semiconductor device comprises a semiconductor substrate having an area in which a circuit element is formed, and a passivation film formed on an upper surface of the semiconductor substrate, at least part of the passivation film being uneven shaped film, an upper surface of which is formed into an uneven shape independent of a shape of a lower surface of the passivation film layer.

Abstract: A ball grid array resistor network has a substrate that has top and bottom surfaces. Resistors are disposed on the top surface. Conductors are disposed on the top surface, and each conductor is electrically connected to an end of each resistor. Vias extend through the substrate and are electrically connected to the conductors. Solder spheres are disposed on the bottom surface, and are electrically connected to the vias. A cover coat is disposed over the conductors and resistors. In an alternative embodiment, the vias are eliminated and the resistor network is formed on the bottom surface of the substrate. The resistor network provides a high density of resistors per unit area.

Abstract: There is a problem in that, in a liquid crystal display panel in which a color filter is formed on an opposing substrate, it is necessary to assemble an element substrate and the opposing substrate by extremely high precision position alignment, and when this precision is low, the aperture ratio decreases and the display becomes darker. With the present invention, red color filters (R) are formed on driving circuits (402, 403), peripheral circuits, and a color filter (405d) for protecting a pixel TFT portion (407) is formed for each pixel.

Abstract: A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.

Abstract: A semiconductor device comprises a semiconductor substrate having an area in which a circuit element is formed; and a passivation film formed on an upper surface of the semiconductor substrate,

Abstract: A novel dielectric composition is provided that is useful in the manufacture of integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by imidizing and curing an oligomeric precursor compound comprised of a central polybenzoxazole, polybenzothiazole, polyamic acid or polyamic acid ester segment end-capped at each terminus with an aryl-substituted acetylene moiety such as an ortho-bis(arylethynyl)aryl group, e.g., 3,4-bis(phenylethynyl)phenyl. Integrated circuit devices, integrated circuit packaging devices, and methods of synthesis and manufacture are provided as well.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: A laser trimming is favorably performed by a strengthened laser beam energy. A level difference portion having a taper portion that is oblique with respect to the thicknesswise direction of a semiconductor substrate is formed at a surface of a semiconductor substrate. An insulating film is formed thereon and has its surface made flat, and then the thin film element is formed thereon. Thereafter, laser trimming is performed with respect to the thin film resistor. As a result, a state of interference between incident laser beam and reflected laser beam reflected from the interface between the semiconductor substrate and the insulating film is varied to thereby enable the production of a zone where laser beam energy is strengthened and a zone where laser beam energy is weakened.

Abstract: A wiring structure for a semiconductor device comprises a first interlayer insulating film formed on a semiconductor substrate, first level wiring conductors formed on the first interlayer insulating film, a second interlayer insulating film formed to cover the first level wiring conductors and including a SOG film, and a second level wiring conductors formed on the second interlayer insulating film. A first level wiring conductor which is formed in a peripheral zone of a semiconductor chip and which has to have a wide line width, is divided into a plurality of divided wiring conductors having a narrow line width. Alternatively, the first interlayer insulating film in the peripheral zone of the semiconductor chip is etched by a predetermined thickness so that the first level wiring conductor located in the peripheral zone of the semiconductor chip is formed at a level lower than the first interlayer insulating film located in an inside of the semiconductor chip.

Abstract: A method is provided for selective oxidation on source/drain regions of transistors on an integrated circuit. The method includes the steps of a) incorporating a neutral species into first kind of the source/drain regions, and b) forming oxidation regions over the first kind of source/drain regions and second kind of the source/drain regions, wherein the oxidation regions over the second kind are thicker than the oxidation regions over the first kind.

Abstract: A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A MOS transistor for high-speed operation includes a gate insulator formed over a semiconductor substrate and a gate formed over the gate insulator. An insulating layer is formed on both sides of the gate insulator at the edge of the gate and thicker than the gate insulator. The device is also formed with LDD regions which form an LDD structure in the semiconductor substrate at least partially under the gate. The LDD structure defines a channel region under the gate insulator between the LDD regions. In one embodiment, the insulating layer formed on both sides of the gate extends toward the channel region but not beyond the LDD regions. In another embodiment, the insulating layer does extend beyond the LDD region but for a distance of less than 10 nm.

Abstract: Providing a method for die bonding semiconductor elements surely without causing damage thereto in a shorter time with less steps of operations, thereby improving the productivity.

Abstract: A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.

Abstract: A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO.sub.2) above the fluorinated layer. The fill layer is substantially free of materials formed in part with fluorine. A top surface of the fill layer can be planarized. Surface treatments and oxide caps can be applied to the planarized surface to form fluorine barriers if part of the fluorinated layer is exposed to higher layers. Such a method, and a semiconductor device or integrated circuit manufactured according to the method, allow the dielectric constant of an inter-layer dielectric ("ILD") to be lowered while also minimizing the complexity and expense of the manufacturing process.

Abstract: A device isolation film is formed on one major surface of a semiconductor substrate so as to surround a device formation region. The device isolation film consists of a first layer made of silicon dioxide, a second layer made of polycrystalline silicon, and a third layer made of silicon dioxide. In a transistor formed in the device formation region, PN junction ends of source and drain regions are in contact with the first layer, and a gate electrode and source and drain electrodes are formed within an opening of the device isolation film. The top surfaces of the gate electrode and the source and drain electrodes are substantially flush with the surface of the third layer of the device isolation film. A gate electrode wiring layer and a source/drain electrode wiring layer for one of the source and drain electrodes are formed on the surface of the third layer.