Abstract: A field-effect transistor includes a gate electrode formed on an electron supply layer thereon, a source electrode and a drain electrode thereon; and also the field-effect transistor includes an insulation film for covering the electron supply layer, and an opening portion of the insulation film, having trapezoidal prism's oblique contour faces, being provided in a region to form the gate electrode in the insulation film. It is so arranged that the gate electrode is made to have a Schottky junction with respect to a region where the electron supply layer is exposed through the opening portion, and also that the trapezoidal prism's oblique contour faces each formed by the opening portion have inclination angles in a range from 25 degrees to 75 degrees with respect to a surface of the electron supply layer.

Abstract: Provided is a mask blank, including a phase shift film. The phase shift film has a structure where a first layer and a second layer are stacked in this order from a side of the transparent substrate. The first layer is provided in contact with a surface of the transparent substrate. Refractive indexes n1 and n2 of the first layer and the second layer, respectively, at a wavelength of an exposure light of an ArF excimer laser satisfy the relation n1<n2. Extinction coefficients k1 and k2 of the first layer and the second layer, respectively, at a wavelength of the exposure light satisfy the relation k1<k2. Film thicknesses d1 and d2 of the first layer and the second layer, respectively, satisfy the relation d1<d2.

Abstract: There is provided a technique that includes: forming a film containing Si, O and N or a film containing Si and O on a substrate by performing a cycle a predetermined number of times under a condition where SiCl4 is not gas-phase decomposed, the cycle including non-simultaneously performing: (a) forming NH termination on a surface of the substrate by supplying a first reactant containing N and H to the substrate; (b) forming a SiN layer having SiCl termination formed on its surface by supplying the SiCl4 as a precursor to the substrate to react the NH termination formed on the surface of the substrate with the SiCl4; and (c) reacting the SiN layer having the SiCl termination with a second reactant containing O by supplying the second reactant to the substrate.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a base layer and an etch stop layer having a plurality of elements and in physical contact with the base layer. The etch stop layer have a Boron (B) element configured to improve the etch profile of the etch stop layer.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: The temperature of a susceptor made of quartz is increased by heat transfer and heat radiation from a heated semiconductor wafer. When the treated semiconductor wafer is transported outwardly, the susceptor has a non-uniform temperature distribution in which a central portion thereof is higher in temperature than an edge portion thereof. In an early stage of preheating in which a new semiconductor wafer is held by the susceptor and starts being irradiated with light emanating from halogen lamps, an intensity ratio that is the ratio of the intensity of light emanating from a central portion of a light irradiator including an array of the halogen lamps to the intensity of light emanating from an edge portion thereof is less than 100%. Thereafter, the ratio of the intensity of light emanating from the central portion of the light irradiator to the intensity of light emanating from the edge portion thereof is increased.

Abstract: A method for forming a semiconductor device includes steps of: forming at least one gate structure comprising a gate electrode over a substrate, and forming a first dielectric layer of a first dielectric material along a side wall of the at least one gate structure. The first dielectric layer of the first dielectric material includes fluorine doped silicon oxycarbonitride with a doping concentration of fluorine. The dielectric constant of the first dielectric layer is adjusted through the doping concentration of fluorine.

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may further include depositing a first silicon nitride layer on the first silicon layer. Depositing the first silicon nitride layer or a stress layer may include reducing stress in at least one of the first silicon layer, the first silicon oxide layer, or the substrate. In addition, the method may include depositing a second silicon layer on the first silicon nitride layer. The operations may form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer.

Abstract: According to one embodiment, a display device includes a first substrate including a pixel circuit, a second substrate disposed opposite to the first substrate, an optical element layer disposed between the first substrate and the second substrate, and a polarizer disposed between the second substrate and the optical element layer, wherein the second substrate has strength greater than that of the first substrate, and the second substrate constitutes the outermost substrate.

Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein the stack structure includes a mask and a conductor; providing an etch stop layer, wherein a portion of the etch stop layer directly contacts both the mask and a portion of the spacer structure; providing a dielectric material member on the etch stop layer; partially removing the first dielectric material member to expose the portion of the etch stop layer; removing the portion of the etch stop layer to expose the portion of the spacer structure; removing the portion of the spacer structure to expose a side of the mask and to form a first spacer; and providing a second spacer, which directly contacts both the first spacer and the side of the mask.

Abstract: There is provided a method of forming a sealing film to seal a device formed on a substrate, including: supplying a mixture gas including a silicon-containing gas and a halogen element-containing gas or a mixture gas including a silicon-containing gas and a gas containing a functional group having an electronegative property stronger than that of nitrogen, as a first mixture gas, into a processing container; generating plasma of the first mixture gas within the processing container; and forming a first sealing film to cover the device using the first mixture gas activated by the plasma.

Abstract: A method of making a magnetic random access memory device comprises forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; and depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction at a temperature of 40 to 60° C. using remote microwave plasma deposition wherein the encapsulation layer comprises silicon and nitrogen. An MRAM device made by the aforementioned method is also disclosed.

Abstract: A sensing element that may include (a) a PIN diode that may include an anode that is coupled to an anode contact; a cathode that is coupled to a cathode contact; a semiconductor portion that has a sensing region; and an insulator that is positioned between the cathode contact and the anode contact; and (b) a shielding element. The insulator, the cathode contact and the anode contact are positioned between the shielding element and the semiconductor portion. The shielding element is shaped and positioned to facilitate radiation to impinge onto the sensing region of the semiconductor portion while at least partially shielding the insulator from electrons that are emitted from the sensing region.

Abstract: A semiconductor manufacturing method includes forming an oxide film on a substrate by performing a first cycle a predetermined number of times, including supplying a first source gas, an oxidizing gas and a reducing gas to the substrate heated to a first temperature in a process container under a sub-atmospheric pressure; forming a seed layer on a surface of the oxide film by supplying a nitriding gas to the substrate in the process container, the substrate being heated to a temperature equal to or higher than the first temperature and equal to or lower than a second temperature; and forming a nitride film on the seed layer formed on the surface of the oxide film by performing a second cycle a predetermined number of times, including supplying a second source gas and the nitriding gas to the substrate heated to the second temperature in the process container.

Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close of the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor including a gate insulator and a gate electrode on a substrate. The method further includes forming an interconnect structure including one or more interconnect layers on the substrate by performing first and second processes one or more times, the first process forming an interconnect layer on the substrate, and the second process processing the interconnect layer into an interconnect pattern. The method further includes annealing the substrate by irradiating the substrate with a microwave, after at least one interconnect layer included in the one or more interconnect layers is processed into an interconnect pattern on the substrate.

Abstract: An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.

Abstract: An organic light emitting device comprises a first substrate; a thin film transistor layer provided on the first substrate; a light emitting diode layer provided on the thin film transistor layer; and a passivation layer provided on the light emitting diode layer, the passivation layer including a first inorganic insulating film and a second inorganic insulating film, wherein a content of H contained in the first inorganic insulating film is smaller than that of H contained in the second inorganic insulating film.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.

Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.

Abstract: The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, in one particularly advantageous embodiment, includes a multi layer etch stop located over a substrate, wherein the multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer. Located over the multi layer etch stop is a dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop. A conductive plug is typically located within the opening, wherein an insulative spacer is located between the conductive plug and the second silicon-rich nitride layer.

Abstract: Provided are a hole-injecting material for an organic electroluminescent device (organic EL device) exhibiting high luminous efficiency at a low voltage and having greatly improved driving stability, and an organic EL device using the material. The hole-injecting material for an organic EL device is selected from benzenehexacarboxylic acid anhydrides, benzenehexacarboxylic acid imides, or N-substituted benzenehexacarboxylic acid imides. Further, the organic EL device has at least one light-emitting layer and at least one hole-injecting layer between an anode and a cathode arranged opposite to each other, and includes the above-mentioned hole-injecting material for an organic EL device in the hole-injecting layer. The organic EL device may contain a hole-transporting material having an ionization potential (IP) of 6.0 eV or less in the hole-injecting layer or a layer adjacent to the hole-injecting layer.

Abstract: A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed.

Abstract: Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.

Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.

Abstract: A semiconductor structure comprises a dielectric layer, a conduction piece, a first metal piece, a first protecting layer, and a second protecting layer. The conduction piece is surrounded by electrical materials of the dielectric layer. The first metal piece is over the dielectric layer and is in contact with the conduction piece. The first protecting layer covers dielectric materials of the dielectric layer that are not covered by the first metal piece. The second protecting layer is over the first protecting layer.

Abstract: The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.

Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.

Abstract: The invention provides a method for manufacturing a barrier layer on a substrate, the method comprising: —providing a substrate with an inorganic oxide layer having a pore volume between 0.3 and 10 vol. %; —treating said substrate with an inorganic oxide layer in a glow discharge plasma, said plasma being generated by at least two electrodes in a treatment space formed between said two electrodes, said treatment space also being provided with a gas comprising Nitrogen compounds; and —the treating of the substrate in said treatment space is done at a temperature below 150° C., e.g. below 100° C. The invention further provides a device for manufacturing a barrier layer on a substrate.

Abstract: Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described.

Abstract: A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.

Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.

Abstract: To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be manufactured with improved efficiency. In specific, a series of processes is performed using a tray with which a plurality of semiconductor substrates can be concurrently processed. Here, the tray is provided with at least one depression for holding single crystal semiconductor substrates.

Abstract: A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract: An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.

Abstract: A method of producing a layer of cavities in a structure comprises at least one substrate formed from a material that can be oxidized or nitrided, the method comprising the following steps: implanting ions into the substrate in order to form an implanted ion concentration zone at a predetermined mean depth; heat treating the implanted substrate to form a layer of cavities at the implanted ion concentration zone; and forming an insulating layer in the substrate by thermochemical treatment from one surface of the substrate, the insulating layer that is formed extending at least partially into the layer of cavities.

Abstract: A method for fabricating a semiconductor device including performing oxygen plasma treatment to a surface of a nitride semiconductor layer, a power density of the oxygen plasma treatment being 0.2 to 0.3 W/cm2.

Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

Abstract: A semiconductor product has different active thicknesses of silicon on a single semiconductor substrate. The thickness of the silicon layer is changed either by selectively adding silicon or subtracting silicon from an original layer of silicon. The different active thicknesses are suitable for use in different types of devices, such as diodes and transistors.

Abstract: Provided are silicon-containing films with a refractive index suitable for antireflection, articles having a surface comprising the films, and atmospheric-pressure plasma-enhanced chemical vapor deposition (AE-PECVD) processes for the formation of surface films and coatings. The processes generally include providing a substrate, providing a precursor comprising silicon, and reacting the precursor with a gas comprising nitrogen (N2) in a low-temperature plasma at atmospheric pressure, wherein the products of the reacting form a film on the substrate. An antireflection coating made by the process can have a refractive index of about 1.5 to about 2.2. Articles are provided having a surface that includes the antireflection coating.

Abstract: A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.

Abstract: An insulating material interposed between two conductive materials can experience plasma process induced damage (PPID) when a plasma process is used to deposit a dielectric onto one of the conductive materials. This PPID can be reduced by reducing electric charge accumulation on the one conductive material during the plasma process dielectric deposition.

Abstract: A method of manufacturing a thin film electronic device comprises applying a first plastic coating (PI-1) directly to a rigid carrier substrate (40) and forming thin film electronic elements (44) over the first plastic coating. A second plastic coating (46) is applied over the thin film electronic elements with electrodes (47) on top, with a portion lying directly over the associated electronic element, spaced by the second plastic coating. The rigid carrier substrate (40) is released from the first plastic coating, by a laser release process. This method enables traditional materials to be used as the base for the electronic element manufacture, for example thin film transistors. The second plastic coating can form part of the known field shielded pixel (FSP) technology.

Abstract: This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.