With High Resistivity (e.g., "intrinsic") Layer Between P And N Layers (e.g., Pin Diode) Patents (Class 257/656)
  • Patent number: 8274136
    Abstract: A semiconductor patch antenna for microwave radiation having a wide pin-junction or pn-junction with the depletion region or embodiments having a separating buried oxide (SiO2) layer between p- and n-doped regions as the natural resonator volume. Embodiments that do not include a metal ground plane and/or a metal patch are disclosed.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: September 25, 2012
    Assignee: Worcester Polytechnic Institute
    Inventors: Sergey N. Makarov, Reinhold Ludwig, Francesca Scire-Scappuzzo, John McNeill
  • Patent number: 8270131
    Abstract: An electrostatic discharge (ESD) protection element is described, the ESD protection element including a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: September 18, 2012
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Klein, Hans Taddiken, Winfried Bakalski
  • Publication number: 20120193756
    Abstract: In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.
    Type: Application
    Filed: February 2, 2011
    Publication date: August 2, 2012
    Inventors: Steven Maxwell, Abhijit Bandyopadhyay, Kun Hou, Er-Xuan Ping, Yung-Tin Chen, Li Xiao
  • Patent number: 8232617
    Abstract: Flexible lateral p-i-n (“PIN”) diodes, arrays of flexible PIN diodes and imaging devices incorporating arrays of PIN diodes are provided. The flexible lateral PIN diodes are fabricated from thin, flexible layers of single-crystalline semiconductor. A plurality of the PIN diodes can be patterned into a single semiconductor layer to provide a flexible photodetector array that can be formed into a three-dimensional imaging device.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: July 31, 2012
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Max G. Lagally, Hao-Chih Yuan
  • Patent number: 8227855
    Abstract: Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: July 24, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph Yedinak, Mark Rinehimer, Thomas E. Grebs, John Benjamin
  • Patent number: 8222075
    Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: July 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Ito
  • Publication number: 20120161298
    Abstract: A diode includes a first region having a first conductive type impurity and formed in a first well having the first conductive type impurity, a second region formed in the first well and having a second conductive type impurity, and a semiconductor pattern disposed above the first well and including a first portion having the first conductive type impurity and a second portion having the second conductive type impurity. The first region and the first portion are coupled with an anode, and the second region and the second portion are coupled with a cathode.
    Type: Application
    Filed: September 23, 2011
    Publication date: June 28, 2012
    Inventors: Jaehyok Ko, Hangu Kim, ChangSu Kim, Dongryul Chang, Minchang Ko
  • Patent number: 8207591
    Abstract: A photoelectric conversion device includes a first electrode; and, over the first electrode, photoelectric conversion layer that includes a first semiconductor layer having one conductivity, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer having a conductivity opposite to the one conductivity of the second semiconductor layer. An insulating layer is over the third semiconductor layer, and a second electrode is over the insulating layer and is electrically connected to the third semiconductor layer through the insulating layer. The third semiconductor layer and a part of the second semiconductor layer are removed in a region of the photoelectric conversion layer that does not overlap the insulating layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: June 26, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuusuke Sugawara, Kazuo Nishi, Tatsuya Arao, Daiki Yamada, Hidekazu Takahashi, Naoto Kusumoto
  • Publication number: 20120126377
    Abstract: A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions.
    Type: Application
    Filed: May 14, 2010
    Publication date: May 24, 2012
    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Alexander Dietrich Holke, Deb Kumar Pal, Kia Yaw Kee, Hao Yang
  • Patent number: 8174089
    Abstract: The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: May 8, 2012
    Assignee: Cree, Inc.
    Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
  • Patent number: 8138583
    Abstract: A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and cathode of the device are located on the same side of the bottom semiconductor layer, providing lateral conduction across the diode body. The anode is positioned on a semiconductor mesa, and the sides of the mesa are covered with a nonconductive spacer extending from the anode to the bottom layer. An ohmic contact, preferably a metal silicide, covers the surface of the bottom layer between the spacer material and the cathode. The conductive path extends from anode to cathode through the body of the mesa and across the bottom semiconductor layer, including the ohmic contact. The method of forming the diode includes reacting layers of silicon and metal on the appropriate regions of the diode to form an ohmic contact of metal silicide.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: March 20, 2012
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Thomas J. Smith, Jr., Helmut Hagleitner
  • Patent number: 8110887
    Abstract: Provided are a photodetector capable of suppressing variations in the output characteristics among photodiodes, and a display device provided with the photodetector. A display device in use has an active matrix substrate (20) including a transparency base substrate (2), a plurality of active elements and a photodetector. The photodetector includes a light-shielding layer (3) provided on the base substrate (2), and a photodiode (1) arranged on an upper layer of the light-shielding layer (3). The light-shielding layer (3) is overlapped with the photodiode (1) in the thickness direction of the base substrate (2). The photodiode (1) includes a silicon layer (11) insulated electrically from the light-shielding layer (3). The silicon layer (11) includes a p-layer (11c), an i-layer (11b) and an n-layer (11a) that are provided adjacent to each other in the planar direction. The p-layer (11c) is formed so that its area (length Lp) will be larger than the area (length Ln) of the n-layer (11a).
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: February 7, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Christopher Brown, Hiromi Katoh
  • Publication number: 20120007222
    Abstract: The present specification provides a method of efficiently manufacturing diodes in which recovery surge voltage is hardly generated. The method manufactures a diode including a high concentration n-type semiconductor layer, a medium concentration n-type semiconductor layer formed on the high concentration n-type semiconductor layer, a low concentration n-type semiconductor layer formed on the medium concentration n-type semiconductor layer, and a p-type semiconductor layer formed on the low concentration n-type semiconductor layer. This manufacturing method includes growing the low concentration n-type semiconductor layer on an n-type semiconductor substrate by epitaxial growth, wherein a concentration of n-type impurities in the low concentration n-type semiconductor layer is lower than that in the n-type semiconductor substrate, and forming the high concentration n-type semiconductor layer by injecting n-type impurities to a lower surface of the n-type semiconductor substrate.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 12, 2012
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tadashi MISUMI, Kimimori HAMADA
  • Publication number: 20120001305
    Abstract: The invention concerns a method of manufacturing a vertical PIN diode comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer, intrinsic layer and P-type layer; forming an anode contact of the vertical PIN diode by forming an anode metallization on a first portion of the P-type layer defining an anode region; forming an electrically insulating layer around the anode region such that a first portion of the intrinsic layer extends vertically between the N-type layer and the anode region and second portions of the intrinsic layer extend vertically between the N-type layer and the electrically insulating layer; forming a trench in the electrically insulating layer and in the second portions of the intrinsic layer so as to expose a portion of the N-type layer defining a cathode region and to define a sacrificial side-guard ring consisting of a portion of the electrically insulating layer that extends laterally between the trench and the anode region and laterally surrounds said anode
    Type: Application
    Filed: June 28, 2011
    Publication date: January 5, 2012
    Applicant: Selex Sistemi Integrati S.p.A.
    Inventors: Marco Peroni, Alessio Pantellini
  • Publication number: 20110316071
    Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.
    Type: Application
    Filed: March 8, 2011
    Publication date: December 29, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kenji HATORI
  • Patent number: 8084838
    Abstract: The invention provides a design of PIN diode having a low capacitance and a large area of effective collection of photo-generated charge. The low capacitance is obtained by replacing a continuous collector layer in the diode by a sparse array of collector disks interconnected by narrow metallic runners at a different structural level separated from the collector discs by an interlevel dielectric.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: December 27, 2011
    Assignee: Research Foundation of State University of New York
    Inventor: Serge Luryi
  • Publication number: 20110309479
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming islands by forming deep trenches within scribe lines of a substrate. The islands have a first notch disposed on sidewalls of the islands. A first electrode stack is formed over a top surface of the islands. The back surface of the substrate is thinned to separate the islands. A second electrode stack is formed over a back surface of the islands.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 22, 2011
    Inventor: Manfred Engelhardt
  • Patent number: 8080840
    Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor can include a readout circuitry on a first substrate; an interlayer dielectric layer including at least one metal and contact plug electrically connected to the readout circuitry; and an image sensing device formed on a second substrate, bonded to the interlayer dielectric layer, and provided with a first conductive type conduction layer and a second conductive type conduction layer. An uppermost contact plug in the interlayer dielectric layer has a wall structure extending from an uppermost metal in the interlayer dielectric layer. The top surface of the uppermost contact plug makes contact with the image sensing device and is connected to an image sensing device and an uppermost metal of an adjacent pixel.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: December 20, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Jong Man Kim
  • Patent number: 8058086
    Abstract: By means of an RIE etch process for silicon (3), a pin-type structure (4,4a) without crystal defects is formed with high aspect ratio and with nano dimensions on the surface of silicon wafers without any additional patterning measures (e-beam, interference lithography, and the like) by selecting the gas components of the etch plasma in self-organization wherein, among others, a broadband antireflective behavior is obtained that may be applicable in many fields.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: November 15, 2011
    Assignees: X-FAB Semiconductor Foundries AG, Technische Universitaet Ilmenau
    Inventors: Konrad Bach, Daniel Gaebler, Michael Fischer, Mike Stubenrauch
  • Publication number: 20110253968
    Abstract: An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device—P-I-N diode structures.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 20, 2011
    Inventors: Seungmoo CHOI, Sameer HADDAD
  • Patent number: 8035131
    Abstract: A method for forming a nitride semiconductor laminated structure includes forming a first layer that is an n-type or i-type first layer composed of a group III nitride semiconductor using an H2 carrier gas; forming a second layer by laminating a p-type second layer composed of a group III nitride semiconductor and containing Mg on the first layer using an H2 carrier gas; and forming a third layer that is an n-type or i-type third layer composed of a group III nitride semiconductor on the second layer using an H2 carrier gas after forming the second layer. A method for manufacturing a nitride semiconductor device includes the method steps for forming the nitride semiconductor laminated structure.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: October 11, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Otake, Hiroaki Ohta, Shin Egami
  • Publication number: 20110227025
    Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.
    Type: Application
    Filed: August 31, 2010
    Publication date: September 22, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jun HIROTA, Yoko Iwakaji, Moto Yabuki
  • Publication number: 20110186972
    Abstract: A protective structure is produced by providing a semiconductor substrate with a doping of a first conductivity type. A semiconductor layer with a doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, wherein the buried layer is produced at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone with a doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone with a doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first region and the second region of the semiconductor layer. A common connection device is formed for the first dopant zone and the second dopant zone.
    Type: Application
    Filed: April 12, 2011
    Publication date: August 4, 2011
    Inventors: Andre Schmenn, Damian Sojka, Carsten Ahrens
  • Patent number: 7989328
    Abstract: An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device-P-I-N diode structures.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: August 2, 2011
    Assignee: Spansion LLC
    Inventors: Seungmoo Choi, Sameer Haddad
  • Patent number: 7982209
    Abstract: A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: July 19, 2011
    Assignee: SanDisk 3D LLC
    Inventors: S. Brad Herner, Roy E. Scheuerlein
  • Patent number: 7968973
    Abstract: A semiconductor element for macro and micro frequency tuning, and an antenna and a frequency tuning circuit having the semiconductor element, are provided. The semiconductor element includes first and second semiconductors which have a same polarity, a third semiconductor which has a polarity opposite to the polarity of the first and second semiconductors and is interposed between the first and the second semiconductors, a first intrinsic semiconductor which is interposed between the first and the third semiconductors, and a second intrinsic semiconductor which is interposed between the third and the second semiconductors.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-won Jung, Jung-han Choi, In-sang Song, Young-eil Kim
  • Patent number: 7948006
    Abstract: A photodetector with an improved electrostatic discharge damage threshold is disclosed, suitable for applications in telecommunication systems operating at elevated data rates. The photodetector may be a PIN or an APD fabricated in the InP compound semiconductor system. The increased ESD damage threshold is achieved by reducing the ESD induced current density in the photodetector by a suitable widening of the contact at a critical location, increasing the series resistance and promoting lateral current spreading by means of a current spreading layer.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: May 24, 2011
    Assignee: JDS Uniphase Corporation
    Inventors: Zhong Pan, David Venables
  • Patent number: 7939900
    Abstract: Polymerizable anions and/or cations can be used as the ionically conductive species for the formation of a p-i-n junction in conjugated polymer thin films. After the junction is formed, the ions are polymerized in situ, and the junction is locked thereafter. The resulting polymer p-i-n junction diodes could have a high current rectification ratio. Electroluminescence with high quantum efficiency and low operating voltage may be produced from this locked junction. The diodes may also be used for photovoltaic energy conversion. In a photovoltaic cell, the built-in potential helps separate electron-hole pairs and increases the open-circuit voltage.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: May 10, 2011
    Assignee: The Regents of the University of California
    Inventor: Qibing Pei
  • Publication number: 20110101298
    Abstract: Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 7919347
    Abstract: Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Carl John Radens, William Robert Tonti
  • Patent number: 7902620
    Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, Jack O. Chu, Martin M. Frank, William M. Green, Young-hee Kim, George G. Totir, Joris Van Campenhout, Yurii A. Vlasov, Ying Zhang
  • Patent number: 7902540
    Abstract: A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Guy M. Cohen
  • Patent number: 7897453
    Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: March 1, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Xiying Chen, Deepak Chandra Sekar, Mark Clark, Dat Nguyen, Tanmay Kumar
  • Patent number: 7868428
    Abstract: A PIN diode comprising an N-type substrate comprising a cathode of the PIN diode and having an intrinsic layer disposed upon the N-type substrate and having a top surface a P-type material disposed upon the top surface of the intrinsic layer comprising an anode of the PIN diode and a N-type material disposed over the sidewall of the cathode and over the sidewall and a portion of the top surface of the intrinsic material that is not occupied by the anode, wherein a horizontal gap is defined between the anode and the cathode through the intrinsic material, the gap being variable in width and/or the horizontal gap is less than the thickness of the intrinsic layer.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: January 11, 2011
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: Joel Lee Goodrich, James Joseph Brogle
  • Patent number: 7863704
    Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: January 4, 2011
    Assignee: Xerox Corporation
    Inventors: JengPing Lu, James B. Boyce, Kathleen Dore Boyce, legal representative
  • Patent number: 7863703
    Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: January 4, 2011
    Assignee: Xerox Corporation
    Inventors: JengPing Lu, James B. Boyce, Kathleen Dore Boyce, legal representative
  • Publication number: 20100320477
    Abstract: A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration.
    Type: Application
    Filed: August 30, 2010
    Publication date: December 23, 2010
    Applicant: CREE, INC.
    Inventors: Calvin H. Carter, JR., Jason R. Jenny, David P. Malta, Hudson M. Hobgood, Valeri F. Tsvetkov, Mrinal K. Das
  • Publication number: 20100258919
    Abstract: A semiconductor patch antenna for microwave radiation having a wide pin-junction or pn-junction with the depletion region or embodiments having a separating buried oxide (SiO2) layer between p- and n-doped regions as the natural resonator volume. Embodiments that do not include a metal ground plane and/or a metal patch are disclosed.
    Type: Application
    Filed: April 9, 2010
    Publication date: October 14, 2010
    Applicant: Worcester Polytechnic Institute
    Inventors: Sergey N. Makarov, Reinhold Ludwig, Francesca Scire-Scappuzzo, John McNeill
  • Patent number: 7812420
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: October 12, 2010
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • Patent number: 7807484
    Abstract: A light-emitting diode (LED) device is disclosed. The LED device includes a semiconductor substrate with a light-emitting diode chip disposed thereon. At least two isolated outer wiring layers are disposed on the bottom surface of the semiconductor substrate and are electrically connected to the light-emitting diode chip, serving as input terminals. A lens module is adhered to the top surface of the semiconductor substrate to cap the light-emitting diode chip. In one embodiment, the lens module comprises a glass substrate having a first cavity formed at a first surface thereof, a fluorescent layer formed over a portion of a first surface exposed by the first cavity, facing the light-emitting diode chip, and a molded lens formed over a second surface of the glass carrier opposing to the first surface.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: October 5, 2010
    Assignee: VisEra Technologies Company Limited
    Inventors: Wei-Ko Wang, Tzu-Han Lin
  • Patent number: 7800204
    Abstract: A semiconductor device includes a stepwise impurity layer provided at one of an anode portion and an cathode portion of the semiconductor device by introducing an impurity of a predetermined conduction type from a major surface of the semiconductor substrate through to a first depth to provide a first region of the semiconductor substrate having the impurity of the predetermined conduction type introduced therein. The predetermined conduction type is a same conduction type as a conduction type of the one of the anode portion and the cathode portion. The stepwise impurity layer is further provided by melting a second, predetermined region of the semiconductor substrate having a second depth deeper than the first depth and including the first region to make uniform the impurity of the predetermined conduction type in a concentration from the major surface through to the second depth to provide a uniform stepwise impurity concentration profile.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: September 21, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hidenori Fujii
  • Patent number: 7795707
    Abstract: The present invention relates to various switching device structures including Schottky diode (10), P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers (16) of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer (14). The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: September 14, 2010
    Assignee: Cree, Inc.
    Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
  • Patent number: 7781869
    Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: August 24, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoki Inoue, Koichi Sugiyama, Hideaki Ninomiya, Tsuneo Ogura
  • Publication number: 20100208517
    Abstract: A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 19, 2010
    Applicant: Spansion LLC
    Inventors: Wai Lo, Christie Marrian, Tzu-Ning Fang, Sameer Haddad
  • Patent number: 7777290
    Abstract: The present invention provides high-speed, high-efficiency PIN diodes for use in photodetector and CMOS imagers. The PIN diodes include a layer of intrinsic semiconducting material, such as intrinsic Ge or intrinsic GeSi, disposed between two tunneling barrier layers of silicon oxide. The two tunneling barrier layers are themselves disposed between a layer of n-type silicon and a layer of p-type silicon.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: August 17, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Max G. Lagally, Zhenqiang Ma
  • Patent number: 7772667
    Abstract: The present invention provides a photoelectric conversion device in which a leakage current is suppressed. A photoelectric conversion device of the present invention comprises: a first electrode over a substrate; a photoelectric conversion layer including a first conductive layer having one conductivity, a second semiconductor layer, and a third semiconductor layer having a conductivity opposite to the one conductivity of the second semiconductor layer over the first electrode, wherein an end portion of the first electrode is covered with the first semiconductor layer; an insulating film, and a second electrode electrically connected to the third semiconductor film with the insulating film therebetween, over the insulating film, are formed over the third semiconductor film, and wherein a part of the second semiconductor layer and a part of the third semiconductor layer is removed in a region of the photoelectric conversion layer, which is not covered with the insulating film.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: August 10, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuusuke Sugawara, Kazuo Nishi, Tatsuya Arao, Daiki Yamada, Hidekazu Takahashi, Naoto Kusumoto
  • Publication number: 20100187662
    Abstract: A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon.
    Type: Application
    Filed: July 20, 2009
    Publication date: July 29, 2010
    Inventors: Junhee Choi, Andrei Zoulkarneev
  • Patent number: 7763947
    Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-SiGe, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: July 27, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Changqing Zhan, Paul J. Schuele, John F. Conley, Jr., John W. Hartzell
  • Publication number: 20100181657
    Abstract: A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.
    Type: Application
    Filed: June 10, 2009
    Publication date: July 22, 2010
    Applicant: SanDisk 3D LLC
    Inventors: S. Brad Herner, Steven J. Radigan
  • Publication number: 20100176375
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 15, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld