With High Resistivity (e.g., "intrinsic") Layer Between P And N Layers (e.g., Pin Diode) Patents (Class 257/656)
  • Patent number: 6531711
    Abstract: The productivity of a photoelectric conversion device is increased by separately conducting a step of forming a microcrystalline semiconductor film and an amorphous semiconductor film without adding an impurity gas.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: March 11, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yasuyuki Arai, Shunpei Yamazaki
  • Publication number: 20030015771
    Abstract: A semiconductor device has a first-conductivity-type semiconductor region, second-conductivity-type semiconductor region, and a high-resistance region. The first-conductivity-type semiconductor region is formed on a first-conductivity-type semiconductor body and has an electric resistance higher than that of the first-conductivity-type semiconductor body. The second-conductivity-type semiconductor region is formed on the first-conductivity-type semiconductor region. The high-resistance region is in contact with the first-conductivity-type and second-conductivity-type semiconductor regions and extends from the upper surface of the second-conductivity-type semiconductor region in the direction of the first-conductivity-type semiconductor body.
    Type: Application
    Filed: July 16, 2002
    Publication date: January 23, 2003
    Inventors: Akio Nakagawa, Yusuke Kawaguchi
  • Patent number: 6504178
    Abstract: A semiconductor imaging device is disclosed. The device includes a substrate having at least first and second surfaces opposing each other, and a circuit layer. The substrate is doped to exhibit a first conductivity type. The substrate includes a conducting layer, a region, and a plurality of doped regions. The conducting layer includes a first type dopants incorporated near the first surface. The region includes a heavily doped area within the substrate near the second surface. The plurality of doped regions includes a second type dopants formed on the second surface. The circuit layer is formed over the second surface to provide gate contacts to and readout circuits for the plurality of doped regions. The readout circuit provides readout of optical signals from pixels.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: January 7, 2003
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, Richard Wilson
  • Patent number: 6492704
    Abstract: The present invention provides photodiodes exhibiting photoconductive gain. It is shown that photodiodes may exhibit photoconductive gain under certain conditions, and traditional photoconductive gain theory has been extended to describe these cases. Particularly, there is introduced the basic principles of photoconductive gain in p-i-n diodes, and there is described several approaches to designing photodiodes with photoconductive gain. In one approach, photogenerated carrier delay is used to obtain photoconductive gain in a photodiode. Delay structures inserted into the intrinsic region preferentially impede the flow of one of the carriers relative to the other to obtain the gain. Another method of obtaining photoconductive gain in a photodiode is to increase the rate at which electron-hole pairs are generated in the p-region or n-region, so as to decrease the times &tgr;p or &tgr;n.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: December 10, 2002
    Inventor: Trenton G. Coroy
  • Patent number: 6469368
    Abstract: In a method for producing a high-speed power diode with soft recovery, in which method the carrier life within the associated semiconductor substrate (10) is governed by first, unmasked bombardment (14) with an axial profile and by subsequent, second, masked bombardment (15) with a lateral profile, improved reverse characteristics are achieved in that the first, unmasked bombardment is ion bombardment (14) which governs the switching response of the power diode and in that the second, masked bombardment is electron bombardment (15), which reduces the active area of the power diode. In a power diode equipped with such a semiconductor substrate (10), the thermal resistance Rth is reduced in relation to the active area of the power diode.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: October 22, 2002
    Assignee: ABB Schweiz AG
    Inventor: Norbert Galster
  • Publication number: 20020121678
    Abstract: A bipolar p-i-n diode has a first (1) and second (5) region of opposite conductivity type and an intermediate drift region (3) between the first and second regions. Trenched field relief regions (14) are arranged to deplete the intermediate drift region (3) when the diode is reverse biased, so permitting a higher doping (12) to be used for the intermediate drift region (3) for a given breakdown voltage. This improves both the turn-on and turn-off characteristics of the diode.
    Type: Application
    Filed: January 31, 2002
    Publication date: September 5, 2002
    Inventor: Eddie Huang
  • Patent number: 6429498
    Abstract: The invention relates to a sensor for measuring a magnetic field. The inventive sensor has a high level of measuring sensitivity compared to a Hall probe, comprising several electrically semiconductive layers. The layers are arranged in the form of a power diode connected in the reverse direction, consisting of an anodelayer, a cathode layer and an intrinsically conductive layer enclosed between the two. The anode layer is subdivided by insulation sections into several anode layer areas, these areas being insulated from each other. The cathode layer has an injector area on the areas opposite the insulation sections which is oppositely doped. An electron beam is formed between the injector area and the anode by applying an injection voltage to the injector area. The electron beam is distributed across the areas of the earthed anode layer areas in the form of uniform partial currents.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 6, 2002
    Assignee: Forschungszentrum J├╝lich GmbH
    Inventors: Jakob Schelten, Ralf Lehmann
  • Patent number: 6426547
    Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: July 30, 2002
    Assignee: Information Business Machines Corporation
    Inventors: David R. Greenberg, Dale K. Jadus, Seshadri Subbanna, Keith M. Walter
  • Patent number: 6396118
    Abstract: An array of active pixel sensors includes a substrate. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes a plurality of conductive vias. A plurality of photo sensors are formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode. Each pixel electrode is electrically connected to the substrate through a corresponding conductive yet. A I-layer is formed over each of the pixel electrodes. The array of active pixel sensors further includes a conductive mesh formed adjacent to the photo sensors. An inner surface of the conductive mesh is electrically and physically connected to the photo sensors, and electrically connected to the substrate through a conductive via. The conductive mesh providing light shielding between photo sensors thereby reducing cross-talk between the photo sensors. The conductive mesh includes apertures that align with at least one of the pixel electrodes of the photo sensors.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: May 28, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Jeremy A. Theil, Jane Mei-Jech Lin, Min Cao, Gary W. Ray, Shawming Ma, Xin Sun
  • Patent number: 6388306
    Abstract: An object is to obtain a semiconductor device having a PN junction which can suppress voltage oscillation without exerting any adverse effects. The film thickness of the N− layer (101) is set to satisfy both of a first condition that the depletion layer extending in the N− layer (101) from the PN junction between the N− layer (101) and the P layer (102) does not reach the N+ layer (103) when a reverse voltage of about ½ to ⅔ of the voltage blocking capability of the diode is applied and a second condition that the depletion layer reaches the N+ layer (103) when a reverse voltage exceeding about ⅔ of the voltage blocking capability is applied. Further, the impurity concentration (specific resistance) of the N− layer (101) is set so that the electric field which acts on the depletion layer when the reverse bias voltage is set equivalent to the voltage blocking capability does not exceed the maximum field strength of silicon.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: May 14, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noritoshi Hirano, Katsumi Satoh
  • Patent number: 6351024
    Abstract: A semiconductor body including a first surface, a second surface, and a base doping for electrical conductivity. A first doped region is on the first surface and a second doped is on the second surface. The two doped regions are doped with opposites signs for electrical conductivity. A contact is positioned on each of the two doped regions. Another region is within the semiconductor body and has an outer section in which the charge carrier concentration in the outer section is lower due to the reduction of the concentration of dopant in the first doped region and/or the increase of concentration of recombination centers in the outer section.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: February 26, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Martin Ruff, Hans-Joachim Schulze
  • Patent number: 6303979
    Abstract: A face down bonding PIN diode having a semiconductor main body; a first region of a conductivity type, a surface of the first region being exposed at a first surface of a semiconductor main body; a third region of a conductivity type opposite that of the first region, the third region being positioned under the first region; a fifth region of substantially intrinsic semiconductor, the fifth region being positioned between the first region and the third region; a fourth region of the same conductivity type, the fourth region being extended vertically from the first surface to the third surface; a first electrode provided on a predetermined surface of the semiconductor main body connected to the first region; and a second electrode provided on the predetermined surface of the semiconductor main body, the second electrode being connected to the fourth region and connected to the third region through the fourth region.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: October 16, 2001
    Assignee: Toko Kabushiki Kaisha
    Inventor: Takeshi Kasahara
  • Patent number: 6300648
    Abstract: A method and apparatus for reducing vertical leakage current in a high fill factor sensor array is described. Reduction of vertical leakage current is achieved by eliminating Schottky junction interfaces that occur between metal back contacts and intrinsic amorphous silicon layers. One method of eliminating the Schottky junction uses an extra wide region of N doped amorphous silicon to serve as a buffer between the metal back contact and the intrinsic amorphous silicon layer. Another method of eliminating the Schottky junction completely replaces the metal back contact and the N doped amorphous silicon layer with a substitute material such as N doped poly-silicon.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: October 9, 2001
    Assignee: Xerox Corporation
    Inventors: Ping Mei, Jeng Ping Lu, Francesco Lemmi, Robert A. Street, James B. Boyce
  • Publication number: 20010020704
    Abstract: Disclosed is an inventive diode which can reduce a stray capacity to improve various characteristics thereof, in which a dielectric layer, a conductive layer and a second dielectric layer are respectively formed by deposition in this order on an upper face of a semiconductor substrate excluding a central portion of an exposed surface of a P-type region. Then, an anode side electrode is formed extending from the exposed surface of the P-type region to the upper face of the second dielectric layer, and is electrically connected with the P-type region. Herein, the conductive layer is formed such that it is isolated from the electrode by the second dielectric layer, is connected with the semiconductor substrate upper face in a location where the dielectric layer has not been formed, and partially resides in a location sandwiched between the electrode and the semiconductor substrate.
    Type: Application
    Filed: March 7, 2001
    Publication date: September 13, 2001
    Inventors: Takeshi Kasahara, Shinichi Shigematsu
  • Patent number: 6288435
    Abstract: A method and apparatus for reducing vertical leakage current in a high fill factor sensor array is described. Reduction of vertical leakage current is achieved by eliminating Schottky junction interfaces that occur between metal back contacts and intrinsic amorphous silicon layers. One method of eliminating the Schottky junction uses an extra wide region of N doped amorphous silicon to serve as a buffer between the metal back contact and the intrinsic amorphous silicon layer. Another method of eliminating the Schottky junction completely replaces the metal back contact and the N doped amorphous silicon layer with a substitute material such as N doped poly-silicon.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: September 11, 2001
    Assignee: Xerox Corporation
    Inventors: Ping Mei, Jeng Ping Lu, Francesco Lemmi, Robert A. Street, James B. Boyce
  • Patent number: 6261874
    Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: July 17, 2001
    Assignee: International Rectifier Corp.
    Inventors: Richard Francis, Chiu Ng
  • Patent number: 6153921
    Abstract: Disclosed is a diode device in which two electrodes of regions forming both terminals are provided on the same face, thereby enabling the device to be connected to a circuit substrate by face-down bonding. Since a region is located within the semiconductor base, an electrode cannot be connected at the top face thereof; to overcome this, a groove is provided extending in a perpendicular direction from the top face of the semiconductor base to the region, and an electrode is provided in the groove. Then, the electrode in the groove is exposed at the top face, enabling the electrodes of both regions to be connected at the top face.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: November 28, 2000
    Assignee: Toko Kabushiki Kaisha
    Inventors: Yutaka Aoki, Takashi Ishikawa, Haruhiko Taguchi, Takeshi Kasahara
  • Patent number: 6111305
    Abstract: A semiconductor photodetector includes a SOI substrate; a p-i-n photodiode provided on the SOI substrate, the p-i-n photodiode having an i-type semiconductor region; an insulator film provided on the i-type semiconductor region; and a depleting electrode provided on the insulator film. The semiconductor photodetector exhibits its function well with or without a power source for applying a voltage to the depleting electrode for depleting it. When the power source for depletion is used, the function of the device is realized at a voltage for depletion applied from the power source for depletion lower than a biasing voltage applied from a biasing power source.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: August 29, 2000
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takeshi Yoshida, Yusuke Otomo
  • Patent number: 6111300
    Abstract: A color detection active pixel sensor. The color detection active pixel sensor includes a substrate. A diode is electrically connected to a first doped region of the substrate. The diode conducts charge when the diode receives photons having a first range of wavelengths. The substrate includes a second doped region. The second doped region conducts charge when receiving photons having a second range of wavelengths. The photons having the second range of wavelengths passing through the diode substantially undetected by the diode. The substrate can include a doped well within the substrate. The doped well conducts charge when receiving photons having a third range of wavelengths. The photons having the third range of wavelengths pass through the diode substantially undetected by the diode.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: August 29, 2000
    Assignee: Agilent Technologies
    Inventors: Min Cao, Paul J. Vande Voorde, Frederick A. Perner, Dietrich W. Vook
  • Patent number: 6081019
    Abstract: A multi-layer Auger suppressed diode having at least two exclusion interfaces and at least two extraction interfaces. A specific embodiment has two composite contacts, each consisting of a heavily doped layer (3, 4) and a buffer layer (8, 9) of lower doped, high bandgap material sandwiched between the heavily doped layer and the active region (2) of the device.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: June 27, 2000
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventor: Anthony M White
  • Patent number: 6081020
    Abstract: An improved PIN photodiode provides enhanced linearity by confining the light absorption region of the diode wholly within the depletion region. The photodiode exhibits improved linearity over prior art designs because the thickness of the absorption region is no longer a function of changes in the size of the depletion region during device operation. Keeping the absorption region wholly within the depletion region ensures that the charge carriers generated by incident illumination will increase the conductivity of the semiconductor material.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: June 27, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Robert Eugene Frahm, Keon M. Lee, Orval George Lorimor, Dennis Ronald Zolnowski
  • Patent number: 6060704
    Abstract: For a multiple transmission communication system, how to individually isolate the transmitted lights and then to distribute to the terminals has been primary concerns to be solved. In the photodetector structure, an absorption layer may be configured as either multiple quantum well structures corresponding to operational wavelengths, or filter-based structure, allowing to select wavelengths in a 1:2:4:8 ratio as an absorptance for each wavelength. In case of using such four-fold lights, the determination as to which wavelength among four-fold wavelengths can be made based upon the total amounts of the current flow in such a photodetector. The photodetector employing such schemes is provided from the present invention.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: May 9, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyung-Sook Hyun, O-Kyun Kwon, Kwang-Joon Kim, El-Hang Lee
  • Patent number: 6049109
    Abstract: A power semiconductor device according to the present invention has an SOI substrate formed of a buried silicon oxide film having an uneven surface portion on the surface thereof and an n-type silicon active layer of low impurity concentration formed on the buried silicon oxide film. An n-type emitter layer and a p-type emitter layer are selectively formed in the surface area of the n-type silicon active layer. A cathode electrode and an anode electrode are respectively formed on the n-type emitter layer and p-type emitter layer. With the above structure, a power semiconductor device of high withstand voltage can be realized.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: April 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Akio Nakagawa
  • Patent number: 6018187
    Abstract: An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. Each photo sensor includes an individual pixel electrode. An I-layer is formed over all of the pixel electrodes. A transparent electrode is formed over the I-layer. An inner surface of the transparent electrode is electrically connected to the I-layer and the interconnect structure.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: January 25, 2000
    Assignee: Hewlett-Packard Cmpany
    Inventors: Jeremy A. Theil, Min Cao, Dietrich W. Vook, Frederick A. Perner, Xin Sun, Shawming Ma, Gary W. Ray
  • Patent number: 6008527
    Abstract: A diode device for face down bonding use comprising: a semiconductor main body; a first region for forming an electrode, the region being exposed at a first surface of the semiconductor main body; a first electrode provided in the first region; a second region for forming another electrode, the second region being provided within the semiconductor main body; a third region conducting the second region to the first surface through the semiconductor main body; and a second electrode provided in the third region on the first surface.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: December 28, 1999
    Assignee: Toko Kabushiki Kaisha
    Inventor: Takeshi Kasahara
  • Patent number: 5977611
    Abstract: A Read diode includes an inner zone, a cathode zone, an anode zone and a first coupling zone disposed between the inner zone and the anode zone. A second coupling zone is disposed between the first coupling zone and the inner zone. Both coupling zones are used in the reverse mode for dividing an electric field into a high-field zone and a low-field zone and, consequently, permit greatly localized charge carrier generation by impact ionization in the voltage breakdown. The use of the two coupling zones ensures "punch-through" coupling between the high-field and low-field zones which, in contrast to the space charge coupling of Read diodes, permits a largely temperature-independent "soft-recovery" behavior. Hybrid diodes having optimized forward and commutation behaviors can be produced from the FCI-PT diodes. FCI-PT diodes are preferably employed in conjunction with switching power semiconductor components as voltage limiters or freewheeling diodes.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: November 2, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Roland Sittig, Karim-Thomas Taghizadeh-Kaschani
  • Patent number: 5917227
    Abstract: A light-emitting-diode array includes a non-doped compound semiconductor layer between a substrate and a first compound semiconductor layer. A plurality of isolation regions extend from the first compound semiconductor layer to the surface of the non-doped compound semiconductor layer, and provide separation into isolated block regions each containing an equal number of diffusion regions. A plurality of shared electrode lines are connected to the diffusion regions in a plurality of the block regions, in such a relationship that diffusion regions selected from each of the block regions are connected to a common shared electrode. At least a surface portion of the substrate is formed of silicon. The density of the diffusion regions can be increased without increasing the number of the electrode pads. Moreover, the substrate is free from breakage or cracks.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: June 29, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Mitsuhiko Ogihara, Yukio Nakamura, Masumi Taninaka, Hiroshi Hamano
  • Patent number: 5874768
    Abstract: A high breakdown voltage semiconductor device formed in an SOI structure is disclosed. An MOS transistor composed of a drift layer, p well, a source, a gate, and a drain is formed in an island region surrounded by insulators on a semiconductor substrate. Furthermore, an electricfield-alleviating layer is formed in a bottom portion of the Si island region. The electric-field-alleviating layer is a semiconductor layer of exceeding low concentration, e.g., intrinsic, and therefore a virtual PIN structure is structured among the p well and the drift layer. Because the electric-field-alleviating layer corresponds to an I layer of the PIN structure, a depletion layer is created within the electric-field-alleviating layer when high voltage is applied to the MOS transistor, the high voltage is distributed throughout this depletion layer, and high breakdown voltage can be obtained.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: February 23, 1999
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hitoshi Yamaguchi, Hiroaki Himi, Seiji Fujino
  • Patent number: 5851310
    Abstract: An indium phosphide photovoltaic cell is provided where one or more quantum wells are introduced between the conventional p-conductivity and n-conductivity indium phosphide layer. The approach allows the cell to convert the light over a wider range of wavelengths than a conventional single junction cell and in particular convert efficiently transparency losses of the indium phosphide conventional cell. The approach hence may be used to increase the cell current output.A method of fabrication of photovoltaic devices is provided where ternary InAsP and InGaAs alloys are used as well material in the quantum well region and results in an increase of the cell current output.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: December 22, 1998
    Assignee: University of Houston
    Inventors: Alexandre Freundlich, Philippe Renaud, Mauro Francisco Vilela, Abdelhak Bensaoula
  • Patent number: 5821597
    Abstract: A photoelectric conversion device taking the form of a thin film and having a substrate exhibiting poor thermal resistance. The device prevents thermal deformation which would normally be caused by local application of excessive heat to the substrate. The device has output terminals permitting the output from the device to be taken out. The output terminals are formed on the surface of the substrate opposite to the photoelectric conversion device. The device further includes electrical connector portions for electrically connecting the electrodes of the device with the output terminals. The present invention also provides a method of treating a substrate having poor thermal resistance with a plasma with a high throughput. The substrate is continuously supplied into a reaction chamber and treated with a plasma. This supply operation is carried out in such a way that the total length of the substrate existing in a plasma processing region formed by electrodes is longer than the length of the electrodes.
    Type: Grant
    Filed: November 8, 1995
    Date of Patent: October 13, 1998
    Assignees: Semiconductor Energy Laboratory Co., Ltd., TDK Corporation
    Inventors: Setsuo Nakajima, Yasuyuki Arai, Hisato Shinohara, Masayoshi Abe
  • Patent number: 5747872
    Abstract: A fast power diode with a soft switching-time response for use in a commutating branch containing a switchable semiconductor component is formed by at least three successive diffusions with p and n dopants and the heavy metal platinum, and for final incorporation of the parameters necessary for operation, the diode is irradiated with electrons.
    Type: Grant
    Filed: June 20, 1995
    Date of Patent: May 5, 1998
    Assignee: Semikron Elektronic GmbH
    Inventors: Josef Lutz, Marianne Kinne, Heinz-Juergen Mueller
  • Patent number: 5717244
    Abstract: An N.sup.- layer (11) of a low impurity concentration is formed on an upper major surface of an N.sup.+ layer (13) of a high impurity concentration in a diode (10). A P layer (12) is further formed on its upper major surface. The N.sup.- layer (11) is in a multilayer structure of first to third regions (11a to 11c) having carrier lifetimes .tau..sub.1, .tau..sub.2 and .tau..sub.3 respectively. These lifetimes are in relation .tau..sub.2 <.tau..sub.1 <.tau..sub.3. Due to the large lifetime .tau..sub.3 of the third region (11c), soft recovery can be implemented. The fact that the lifetime .tau..sub.3 of the third region (11c) is large serves as a factor reducing a forward voltage V.sub.f. It is possible to attain soft recovery without increasing the forward voltage V.sub.F by properly designing these lifetimes and thicknesses.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: February 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Noriyuki Soejima
  • Patent number: 5648675
    Abstract: In the present invention, atoms are implanted into the surface of at least a crystalline silicon semiconductor of one conductivity type in forming a heterojunction, thereby to bring the surface of the crystalline silicon semiconductor into amorphous to form a substantially intrinsic amorphous silicon layer. An amorphous silicon layer or a microcrystalline silicon layer of an opposite conductivity type is deposited on the amorphous silicon layer, whereby a heterojunction interface is formed in a region deeper than a deposition interface.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: July 15, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Norihiro Terada, Yasuki Harada
  • Patent number: 5637883
    Abstract: An optically addressed spatial light modulator includes top and bottom conductive layers sandwiching an intrinsic semiconductor multilayer structure. A cladding layer having a high trapping density is sandwiched between at least one of the electrodes and the intrinsic semiconductor layer structure. Typically, one cladding layer will be sandwiched between the top conductive layer and the intrinsic semiconductor multilayer structure and another cladding layer will be sandwiched between the bottom conductive layer and the intrinsic semiconductor structure. The cladding layer or layers laterally confine the photocarriers generated within the intrinsic semiconductor multilayer structure.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: June 10, 1997
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Steven R. Bowman, William S. Rabinovich, Douglas S. Katzer, Harry B. Dietrich
  • Patent number: 5616944
    Abstract: A diode is provided comprising first and second semiconductor regions. The first semiconductor region is of one conductivity type and the second is of the opposite conductivity type. A third region is provided which is either an intrinsic semiconductor region or a low concentration region. The low concentration region has an impurity concentration lower than that of the first and second semiconductor layers. The third region is arranged to separate the first and second semiconductor regions. A control electrode region is provided over the third region through an insulative film.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: April 1, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hidemasa Mizutani, Toru Koizumi
  • Patent number: 5600156
    Abstract: A diamond semiconductor device of the present invention comprises an n-type diamond layer to which an n-type dopant is doped at high concentration so that metal conduction dominates, a p-type diamond layer to which a p-type dopant is doped at high concentration so that metal conduction dominates, and a high resistance diamond layer formed between the n-type diamond layer and the p-type diamond layer. Here, the thickness and the doping concentration of the high resistance diamond layer are values at which semiconductor conduction dominates. Then, in a case that an applied voltage is forward bias, electrons are injected from the n-type region to the p-type region through the conduction band of the high resistance region, and holes are injected from the p-type region to the n-type region through the valance band of the high resistance region, so that a current flows.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: February 4, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Nishibayashi, Tadashi Tomikawa, Shin-ichi Shikata
  • Patent number: 5563425
    Abstract: An object of the present invention is to provide a photoelectrical conversion device in which recombination of carriers excited by light is prevented and the open voltage and the carrier range of positive holes are improved and to provide a generating system using the photoelectrical conversion device. The photoelectrical conversion device includes a p-layer, an i-layer, and an n-layer, wherein the photoelectrical conversion device being formed by stacking the p-layer, the i-layer and the n-layer each of which is made of non-single-crystal silicon semiconductor, the i-layer contains germanium atoms, the band gap of the i-layer is smoothly changed in a direction of the thickness of the i-layer, the minimum value of the band gap is positioned adjacent to the p-layer from the central position of the i-layer and both of a valence control agent to serve as a donor and another valence control agent to serve as an acceptor are doped into the i-layer.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: October 8, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keishi Saito, Tatsuyuki Aoike, Masafumi Sano, Mitsuyuki Niwa, Ryo Hayashi, Masahiko Tonogaki
  • Patent number: 5557131
    Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: September 17, 1996
    Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.
    Inventor: Steven Lee
  • Patent number: 5554882
    Abstract: An avalanche semiconductor switch device utilizes trigger input. The integrated trigger input is a charge carrier injector which injects charge carriers directly into the avalanche semiconductor switch device. The avalanche semiconductor switch device includes: an active, semi-insulating layer; an anode; a cathode; and an injector disposed on the anode contact. The injector serves to switch the device into a state of very high conductance when a positive bias is applied to the injector. The integrated trigger input allows low power optical sources to be used with the avalanche semiconductor switch device further back in the trigger chain. The injector may inject holes or electrons. The injector may be integrated on one side of the substrate.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: September 10, 1996
    Assignee: The Boeing Company
    Inventor: R. Aaron Falk
  • Patent number: 5550670
    Abstract: An optoelectronic semiconductor component (1) for modulating a supplied light beam is described, where the optoelectronic semiconductor component has a pin-structure (2, 3, 4). The invention provides that M semiconductor structures with carriers localized in at least one dimension (Q1-Q20; CB1-CB10) are arranged in at least two groups (G1-G10), where the semiconductor structures with carriers localized in at least one dimension belonging to one group (G1-G10), are separated by barriers (CB1-CB10), which essentially allow Starkladder transitions between the individual semiconductor structures (Q1-Q20; CB1-CB10) of each group (G1-G10), and the individual groups (G1-G10) of such coupled semiconductor structures (Q1-Q20; CB1-CB10) are separated by other barriers (B1-B11), which essentially prevent Stark-ladder transitions between the active layers (Q1-Q20) of the semiconductor structures (Q1-Q20; CB1-CB10) of a group (G1-G10) and an active layer (Q1-Q20) of another group.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: August 27, 1996
    Assignee: Alcatel N.V.
    Inventors: Erich Zielinski, Gerhard Weiser
  • Patent number: 5479043
    Abstract: Component comprising a stack of at least two associated elementary cells (1, 2) with different spectral response features, characterized in that at least one of the elementary cells is capable of being mechanically deformed. The flexibility of this cell is sufficiently high that it can adhere directly to the other cell simply by van der Waals' interaction between the two surfaces opposite the elementary cells. The interface (20) separating the two opposite surfaces can be either sufficiently thin to form a tunnel junction electrically coupling both elementary cells to one another, the opposite layers of the elementary cells then being layers of degenerated semiconductor material p.sup.+ and n.sup.+, sufficiently high to prevent any coupling between the two elementary cells, said cells then each having its own pairs of electrodes leading to separate terminals of the component.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: December 26, 1995
    Assignee: Picogiga Societe Anonyme
    Inventor: Linh T. Nuyen
  • Patent number: 5436756
    Abstract: Photocurrent suppression is achieved without deleteriously affecting modulation performance in a surface normal, electro-absorption, quantum well modulator by introducing a sufficient number of non-radiative recombination centers in the quantum well region of the modulator. The presence of the non-radiative recombination centers significantly shortens the lifetime of photogenerated carriers and, thereby, suppresses the photocurrent. Modulation performance characteristics such as contrast ratio are maintained at acceptable levels even though exciton broadening occurs in the quantum wells. The present modulator exhibits a careful balance between defect density in the quantum wells and the acceptable degree of exciton broadening necessary to preserve quantum effects.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: July 25, 1995
    Assignee: AT&T Bell Laboratories
    Inventors: Wayne H. Knox, Jason B. Stark, Benjamin Tell, Ted K. Woodward
  • Patent number: 5424565
    Abstract: A position-sensitive semiconductor detector is provided having a completely depleted primary area of a first conductivity and insulation layers on the two main surfaces as well as conductive electrodes on the insulation layers (MIS structure).
    Type: Grant
    Filed: November 4, 1993
    Date of Patent: June 13, 1995
    Assignee: Josef Kemmer
    Inventor: Josef Kemmer
  • Patent number: 5412499
    Abstract: A spatial light modulator includes a multiple quantum well (MQW) device. Unlike MQWs of the prior art, this MQW is made semi-insulating. As a result, individual picture elements can be defined entirely by the placement of electrodes in an array on a surface of the device. Them is no need to etch trenches for electrical isolation of the picture elements.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: May 2, 1995
    Assignee: AT&T Corp.
    Inventors: Tien-Heng Chiu, Alastair M. Glass, Afshin Partovi
  • Patent number: 5391910
    Abstract: A light absorbing layer, and a window layer formed thereon constitutes a first conduction-type semiconductor layer. In a part of this first conduction-type semiconductor layer there is provided a second conduction-type region extending to the light absorbing layer through the window layer. A part of the window layer around the second conduction region is selectively removed. Consequently even when light intended to enter a light detecting region is incident outside of the light detecting region, most of the carriers generated there are recombined at a surface level of the light absorbing layer before diffusing in a depletion layer. This light detecting device therefor does not substantially detect sensitivity to light incident outside the light detecting region.
    Type: Grant
    Filed: December 16, 1991
    Date of Patent: February 21, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yasushi Fujimura, Ichiro Tonai, Hiroshi Okuda
  • Patent number: 5373186
    Abstract: A semiconductor device consisting of epitaxial material is provided with at least one monoatomic layer of doping atoms, i.e. with a layer which is just one atom thick. A preferred device is a bipolar transistor in which case the Dirac-delta doped p-type layer 38 is directly between n-type collector and emitter layers (32, 33). The bipolar transistor described herein has an extremely low base width and is capable of operating at high frequencies.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: December 13, 1994
    Assignee: Max-Planck Gesellschaft zur Foerderung der Wissenschaften e.V.
    Inventors: Erdmann Schubert, Klaus Ploog, Albrecht Fischer
  • Patent number: 5360990
    Abstract: In a semiconductor P/N junction device, a porous emitter is provided which has high saturation current to limit injected charge when the device is conducting. The porous emitter includes a lightly doped region abutting a contact on the surface of the device to regulate minority carrier injection under forward bias and shield the contact from stand-off field when the device is not conducting. One or more heavily doped regions are provided in the first region to provide low contact resistance for the flow of majority carriers into the emitter.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: November 1, 1994
    Assignee: Sunpower Corporation
    Inventor: Richard M. Swanson
  • Patent number: 5350940
    Abstract: This invention relates to a process for fabricating a metal-oxide-semiconductor device and to the semiconductor device which has enhanced charge mobility due to the inclusion of a thin layer of intrinsic semiconductor which provides a "fast track" charge channel directly at the accumulated inversion layer. The particular semiconductor device described is the enhanced mobility metal-oxide-semiconductor field effect transistor EMMOSFET having the intrinsic layer from about 100 .ANG. to about 1000 .ANG. thick. The intrinsic layer provides a low resistivity channel between the source and drain of the EMMOSFET resulting in an increase in device speed and a decrease in device heat generation.
    Type: Grant
    Filed: December 6, 1991
    Date of Patent: September 27, 1994
    Assignee: Fastran, Inc.
    Inventor: Mehmet Rona
  • Patent number: 5343070
    Abstract: A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: August 30, 1994
    Assignee: M/A-COM, Inc.
    Inventors: Joel L. Goodrich, Christopher C. Souchuns
  • Patent number: 5329141
    Abstract: A light emitting diode of silicon carbide having a p-n junction comprising an n-type layer doped with donor impurities, a first p-type layer doped with acceptor impurities, and a second p-type layer doped with acceptor impurities and donor impurities. The first p-type layer has a thickness less than the diffusion length of electrons having flowed from the n-type layer. In this way, the first p-type layer effects light emission related to the acceptor impurities which recombine with the electrons having flowed from the n-type layer, and the second p-type layer effects light emission by donor-acceptor pairs which recombine with the electrons having flowed from the n-type layer.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: July 12, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akira Suzuki, Yoshihisa Fujii, Hajime Saito, Katsuki Furukawa, Yoshimitsu Tajima