Lead Frame Patents (Class 257/666)
  • Patent number: 10978381
    Abstract: A semiconductor device includes: a first semiconductor element including a first signal electrode; a second semiconductor element, laminated on the first semiconductor element, including a second signal electrode; a sealing body; a first signal terminal connected to the first signal electrode; and a second signal terminal connected to the second signal electrode, wherein: the first signal terminal and the second signal terminal project from the sealing body and extend in a first direction; the first signal terminal and the second signal terminal are distanced from each other in a second direction; the first signal electrode and the second signal electrode are placed at different positions in the second direction; the first signal electrode is provided closer to the first signal terminal than to the second signal terminal; and the second signal electrode is provided closer to the second signal terminal than to the first signal terminal.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: April 13, 2021
    Assignee: Denso Corporation
    Inventor: Takanori Kawashima
  • Patent number: 10971429
    Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: April 6, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Soon Wei Wang, Hoe Kit Liew How Kiat Ley
  • Patent number: 10964630
    Abstract: A semiconductor device may include a first conductor plate on which a first semiconductor element, a second semiconductor element and a first circuit board are disposed, and a plurality of first signal terminals. A size of the second semiconductor is smaller than a size of the first semiconductor element. In a plan view along a direction perpendicular to the first conductor plate, the plurality of first signal terminals is located in a first direction with respect to the first semiconductor element. The second semiconductor element and the first circuit board are located between the plurality of first signal terminals and the first semiconductor element and are arranged along a second direction that is perpendicular to the first direction. A signal pad of the first semiconductor element is connected to a corresponding one of the plurality of first signal terminals via a signal transmission path of the first circuit board.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 30, 2021
    Assignee: DENSO CORPORATION
    Inventors: Takanori Kawashima, Makoto Imai, Masaki Aoshima
  • Patent number: 10965046
    Abstract: A terminal 20 includes a terminal connection portion 21 connected to a counterpart terminal and a board connection portion 24 connected to a conductive path 13 of a board 11. The board connection portion 24 has a plate shape portion 25 that is a plate shape. The plate shape portion is disposed behind the terminal connection portion 21 and is soldered to the conductive path 13 of the board 11. The board connection portion has a plate-shape first projection walls 28A to 28D that are bent from edge portions of a lateral direction side of the plate shape portion 25 and that project to an opposite side to the board 11 side. The plate shape portion 25 and the first projection walls 28A to 28D have a plating layer 37 that is formed on a plate surface of the plate shape portion and the first projection walls.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 30, 2021
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd., Sumitomo Electric Printed Circuits, Inc.
    Inventors: Takanobu Shimada, Hiroki Hirai, Jyunichi Ono, Yoshio Oka, Yoshifumi Uchita, Yoshiro Adachi
  • Patent number: 10957631
    Abstract: A leadframe comprising a plurality of leads, each of the plurality of leads having a proximal end and a distal end opposite the proximal end, the distal ends positioned along a linear axis. The leadframe further comprises a die pad closer to the proximal ends than the distal ends of the plurality of leads and including an edge positioned along a plane that intersects the linear axis at an angle less than 90 degrees.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Chung-Ming Cheng, Yuh-Harng Chien, Fu-Kang Lee, Chia-Yu Chang
  • Patent number: 10957635
    Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: March 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Nazila Dadvand, Sreenivasan Koduri, Benjamin Stassen Cook
  • Patent number: 10950558
    Abstract: An object is to provide a technique for reducing process steps, and a stress generated at the peripheral portion of the joint portion between an electrode of a semiconductor element and a lead frame. A semiconductor device includes the following: a semiconductor element disposed on a heat spreader; a lead frame joined to an emitter electrode of the semiconductor element via solder, which is a joining material; a metal film disposed on a surface of the emitter electrode; and an anti-oxidation film disposed on a surface of the metal film. The metal film has a peripheral portion that is entirely exposed from the anti-oxidation film.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuyoshi Kimoto, Mitsunori Aiko, Takaaki Shirasawa
  • Patent number: 10943844
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Masatoshi Kawato, Masayuki Miura, Masatoshi Fukuda, Soichi Homma
  • Patent number: 10943871
    Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 9, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jun Ho Jeon, Kyeong Sool Seong, Seok Ho Na, Jeong Il Kim, Young Kyu Kim, Sung Ho Jeon, Deok In Lim, Sung Moo Hong, Sung Jung Kim, Sung Han Ryu, Kyung Nam Kang, Seong Hak Yoo
  • Patent number: 10935419
    Abstract: A light detection device includes: a package including an opening configured to allow light to enter therefrom; a light transmitting unit arranged on an inner surface of the package so as to close the opening; a Fabry-Perot interference filter arranged in the package and configured to transmit light transmitted by the light transmitting unit; and a light detector arranged in the package and configured to detect the light transmitted by the Fabry-Perot interference filter. The light transmitting unit is integrally configured by including: a band pass filter arranged in the package and configured to transmit the light to be incident on the Fabry-Perot interference filter; and at least one lens unit configured to condense the light to be incident on the Fabry-Perot interference filter.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 2, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Masaki Hirose, Katsumi Shibayama, Takashi Kasahara, Toshimitsu Kawai, Hiroki Oyama, Yumi Kuramoto
  • Patent number: 10930581
    Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10910325
    Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Seok Ling Lim, Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong
  • Patent number: 10912189
    Abstract: A circuit board is provided. The circuit board includes a first pin row, a second pin row and a plurality of signal vias. The first pin row includes a first side and a second side, wherein the first side of the first pin row and the second side of the first pin row are opposite to each other. The second pin row includes a first side and a second side, wherein the first side of the second pin row and the second side of the second pin row are opposite to each other. A plurality of traces of the circuit board are electrically connected to a plurality of pins of the first pin row and a plurality of pins of the second pin row respectively through the signal vias. Three consecutive signal vias of the signal vias are sequentially disposed at the first side of the first pin row, the first side of the second pin row, and the second side of the first pin row.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: February 2, 2021
    Assignee: PEGATRON CORPORATION
    Inventor: Te-Yu Liao
  • Patent number: 10903171
    Abstract: A semiconductor device including a base, a buffer member, a frame, a lid, and a semiconductor element, is disclosed. The ceramic frame is mounted on the copper base with the molybdenum buffer member interposed therebetween. The semiconductor element is sealed in a space within the frame defined by the lid. The frame includes a top portion, a lower stage portion that is disposed below the top portion and is provided with an input electrode and an output electrode, and an upper stage portion. The upper stage portion is formed in an arrangement direction of the input electrode and the output electrode, and is formed below the top portion and above the lower stage portion. The upper stage portion includes an upper stage connection portion formed on the periphery of the lower stage portion in a direction intersecting the arrangement direction of the input electrode and the output electrode.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 26, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tuneyuki Tanaka
  • Patent number: 10903133
    Abstract: A package encloses a power semiconductor die and has a package body with a top side, footprint side and sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; and a top layer arranged at the package top side and electrically connected with the second load terminal. A heat spreader is mounted onto the top layer with a bottom surface facing the top layer. The area of the top surface of the heat spreader is greater than the area of the bottom surface.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
  • Patent number: 10903150
    Abstract: A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering top faces and faces that form concavities or a through hole between the top faces and bottom faces of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: January 26, 2021
    Assignee: OHKUCHI MATERIALS CO., LTD.
    Inventors: Kaoru Hishiki, Keiichi Otaki, Hidehiko Sasaki, Kotaro Tomeoka
  • Patent number: 10895682
    Abstract: Photonic circuits are disclosed having an efficient optical power distribution network. Laser chips (InP) having different wavelengths are flip-chip assembled near the center of a silicon photonic chip. Each InP die has multiple optical lanes, but a given die has only one wavelength. Waveguides formed in the photonic chip are optically connected to the lanes, and fan out to form multiple waveguide sets, where each waveguide set has one of the waveguides from each of the different wavelengths, i.e., one waveguide from each InP die. The waveguide network is optimized to minimize the number of crossings that any given waveguide may have, and no waveguide having a particular wavelength crosses another waveguide of the same wavelength. The unique arrangements of light sources and waveguides allows the use of a smaller number of more intense laser sources, particularly in applications such as performance-optimized datacenters where liquid cooling systems may be leveraged.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Douglas M. Gill, William M. Green, Jason S. Orcutt, Jessie C. Rosenberg, Eugen Schenfeld, Chi Xiong
  • Patent number: 10896889
    Abstract: Disclosed is technology in that a clip structure formed of an inexpensive and light metallic material to easily performing soldering on a corresponding metal and to reduce costs of a semiconductor package and to reduce the weight of the semiconductor package. The composite clip structure bent at a predetermined angle and being in charge of electrical connection between components in a semiconductor package includes a main metal layer formed of a conductive material with a predetermined thickness, and a lower functional layer formed below the main metal layer and formed of a different type of metal from a metallic component of the main metal layer, wherein the lower functional layer is attached to the main metal layer to be integrated thereinto, and wherein the main metal layer is formed of a single metal containing a largest amount of aluminum (Al) or a metal mixture containing a largest amount of Al.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: January 19, 2021
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, Young hun Kim, Tae Heon Lee, Jeong Hun Cho
  • Patent number: 10886862
    Abstract: A third upper MOS and a third motor relay are disposed on a front surface of a substrate. A third shunt resistor and a third lower MOS are disposed on a back surface of the substrate. The substrate has a via electrically connecting interconnects. Thus, a source electrode of the third upper MOS and a drain electrode of the third motor relay are electrically connected to a source electrode of the third lower MOS by the via.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 5, 2021
    Assignee: JTEKT CORPORATION
    Inventor: Nobutaka Okumura
  • Patent number: 10886145
    Abstract: A method of producing a surface-mountable multi-chip component includes providing a chip arrangement including a metallic conductor structure exposed at a rear side, a plurality of semiconductor chips and an housing material; and forming a solder stop coating on a rear side of the chip arrangement, wherein the solder stop coating separates connection regions of the conductor structure.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 5, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Michael Zitzlsperger, Tobias Gebuhr, Stephan Eicher
  • Patent number: 10879121
    Abstract: A method of forming a leadless packaged semiconductor device. First partial sawing leads is performed on a bottom side of an in-process leadless semiconductor package having a leadframe including die pad with a semiconductor chip thereon, and leads defining top and bottom surfaces and having an inner end and an outer end having a bottom corner region. Conductive bond wires connect to and extending between bond pads on the chip and respective leads, a mold compound is around the die pad, leads, chip, and conductive bond wires while exposing the bottom surface and outer end. The first sawing completely severs the leads while forming only a partial cut in the mold compound. A de-flash process is applied to the bottom side. The second sawing aligned to the partial cuts reaches the partial cuts to complete singulation of the package, wherein the second sawing does not touch the leads.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mohamad Ashraf Bin Mohd Arshad, Soo Wai Kong
  • Patent number: 10867894
    Abstract: To achieve the miniaturization of and the enhancement of the strength of a semiconductor element.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 15, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Toshiaki Fukunaka
  • Patent number: 10861777
    Abstract: Aspects of the disclosure relate generally to semiconductor packaging, and specifically to semiconductor device having a lead frame having a semiconductor supporting die pad that is capable of engaging with a wire bonding clamp.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuh-Harng Chien, Hung-Yu Chou, Fu-Kang Lee
  • Patent number: 10854788
    Abstract: An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment a method includes attaching a plurality of optoelectronic semiconductor chips on predetermined locations of an intermediate film, providing a cavity film with a plurality of separated openings, attaching the cavity film to the intermediate film such that each optoelectronic semiconductor chip is associated with a respective opening, wherein the cavity film is thicker than the optoelectronic semiconductor chips such that the cavity film exceeds the optoelectronic semiconductor chips in a direction away from the intermediate film, filling a casting material in each of the openings such that the optoelectronic semiconductor chips are casted with the casting material and removing the intermediate film.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 1, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Choo Kean Lim, Choon Keat Or, Choon Kim Lim, Ai Cheng Chan
  • Patent number: 10852259
    Abstract: An apparatus for X-ray inspection is provided. The apparatus includes: a stage on which an inspection target is loaded, the stage including a first surface and an opposite second surface; an X-ray generator disposed on or over the first surface of the inspection target and configured to irradiate the inspection target with incident X-rays; and a detection system disposed on or under the second surface of the inspection target and configured to detect first transmitted X-rays transmitted through the inspection target. The detection unit includes a first lens system and a second lens system. The first transmitted X-rays pass through one of the first lens system and the second lens system. The second lens system includes a micro zone plate.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 1, 2020
    Inventors: Kyoung Hwan Lee, Sang Min Kim, Young Hoon Sohn, Yu Sin Yang, Chi Hoon Lee
  • Patent number: 10854538
    Abstract: A microelectronic device has a first die attached to a first die pad, and a second die attached to a second die pad. A magnetically permeable member is attached to a first coupler pad and a second coupler pad. A coupler component is attached to the magnetically permeable member. The first die pad, the second die pad, the first coupler pad, the second coupler pad, and the magnetically permeable member are electrically conductive. The first coupler pad is electrically isolated from the first die, from the second coupler pad, and from external leads of the microelectronic device. The second coupler pad is electrically isolated from the first die and from the external leads. The first die and the second die are electrically coupled to the coupler component. A package structure contains at least portions of the components of the microelectronic device and extends to the external leads.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, JK Ho
  • Patent number: 10840169
    Abstract: In one example, a semiconductor device comprises a substrate having a top surface and a bottom surface, an electronic device on the bottom surface of the substrate, a leadframe on the bottom surface of the substrate, the leadframe comprising a paddle, wherein the paddle is coupled to the electronic device, and a lead electrically coupled to the electronic device. The semiconductor device further comprises a first protective material contacting the bottom surface of the substrate and a side surface of the electronic device.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: November 17, 2020
    Assignee: Amkor Technology Singapore Holding PTE. LTD.
    Inventors: Hyung Jun Cho, Kyoung Yeon Lee, Tae Yong Lee, Jae Min Bae
  • Patent number: 10840818
    Abstract: A power conversion apparatus includes N semiconductor modules respectively including a switch part including first and second semiconductor switches coupled in series, and an output terminal coupled to a node that connects the first and second semiconductor switches, where N is an integer greater than or equal to 3, wherein the N semiconductor modules are arranged so that the output terminals thereof are adjacent to each other. The power conversion apparatus further includes an output bar to couple the output terminals of the N semiconductor modules so that a parasitic inductance of a current path coupling the output terminals of first and second semiconductor modules among the N semiconductor modules, and a parasitic inductance of a current path coupling the output terminals of the first and third semiconductor modules among the N semiconductor modules, are approximately balanced.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hong-Fei Lu
  • Patent number: 10840171
    Abstract: A packaged semiconductor device includes a semiconductor die mounted on a leadframe, a housing for the semiconductor die defining a horizontal plane and a horizontal direction. The leadframe includes leads each having an inner lead portion inside the housing and an outer lead portion that includes a first portion that extends out in the horizontal direction from one of the sidewalls of the housing, a transition portion that includes a vertical direction component, and a distal end portion, wherein the distal end portion of the leads are all on the horizontal plane. The outer lead portions alternate between a gull wing lead shape having the distal end portions extending in the horizontal direction outward from the housing and inward extending leads that have their distal end portions extending in the horizontal direction inward toward the housing. The leadframe consists of a single leadframe.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael L. Meyers, Scott F. Eisenhart, Richard J. Saye, Sreenivasan K. Koduri
  • Patent number: 10833008
    Abstract: A packaged semiconductor device has a die attach pad and leads disposed proximate to the die attach pad. Each lead has a lead bottom surface and a lead end surface. A semiconductor device attached adjacent to a top surface of the die attach pad, and a conductive clip is attached to the semiconductor device and at least one of the leads. The conductive clip comprises a first tie bar extending from a first side surface of the conductive clip. A package body encapsulates the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad. Each lead end surface is exposed in a side surface of the package body, and an end surface of the first tie bar is exposed in a first side surface of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the first tie bar.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Siang Miang Yeo, Mohd Hasrul Bin Zulkifli
  • Patent number: 10832942
    Abstract: A semiconductor structure includes a free-floating silicon-bridge chip electrically joined on a top portion to two or more semiconductor chips and electrically joined on a bottom portion to a substrate structure that includes a plurality of metal interconnect structures and a plurality of metal layers disposed on an interlevel dielectric. The silicon bridge chip is aligned with and extends into a recess located in a region of the substrate structure away from the plurality of metal interconnect structures and the plurality of metal layers such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10825778
    Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other, and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a wiring structure connected to the first redistribution layer and extending in a thickness direction of the encapsulant; a second redistribution layer disposed on the encapsulant and connected to the wiring structure; and a mark disposed on the encapsulant and including a plurality of metal patterns providing identification information and a circuit line connected to the second redistribution layer.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Hawn Bae, Pyung Hwa Han, Jung Soo Kim
  • Patent number: 10811346
    Abstract: A lead frame includes a lead frame substrate made of a copper-based material, plating layers composed of nickel, palladium and gold layers laminated in this order on top faces and bottom faces of the lead frame substrate, and a roughened silver plating layer having acicular projections, provided as an outermost plating layer and covering faces of the lead frame substrate that form concavities or a through hole between the top faces and the bottom faces of the lead frame substrate. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 20, 2020
    Assignee: OHKUCHI MATERIALS CO., LTD.
    Inventors: Kaoru Hishiki, Keiichi Otaki, Hidehiko Sasaki, Kotaro Tomeoka
  • Patent number: 10811278
    Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chia Y. Poo, Low Siu Waf, Boon Suan Jeung, Eng M. Koon, Chua Swee Kwang
  • Patent number: 10804114
    Abstract: A method for forming a multilevel leadframe for an integrated circuit is provided. A conductive sheet is etched from one side to form a thinner region within a frame region for leads lines and bond pads. The conductive sheet is etched to form a plurality of bond pads in a first level of the thinner region arranged in at least a first row and a second row. Each bond pad has a pad width and is separated from an adjacent bond pad by a bond pad clearance distance. The conductive sheet is etched from an opposite side to form a plurality of lead lines in a second level of the thinner region having a line width and is separated from an adjacent lead line by at least a lead line clearance distance. Each bond pad of the second plurality of bond pads is connected to one of the plurality of lead lines on the second level that is routed between adjacent bond pads in the first row, so that the lead lines are routed on a different level from the bond pads.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 13, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng@ Eugene Lee, You Chye How
  • Patent number: 10795079
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 6, 2020
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Loy Yee Lam
  • Patent number: 10797004
    Abstract: A semiconductor device package includes: (1) a lead frame including a connection element and multiple leads; (2) a package body encapsulating the lead frame, wherein the package body includes a lower surface and an upper surface opposite to the lower surface, the package body includes a cavity exposing at least one of the leads; (3) at least one conductive via disposed in the cavity of the package body, electrically connected to the connection element, and exposed from the upper surface of the package body; and (4) a conductive layer disposed on the upper surface of the package body and the conductive via.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-Lun Yang, Yu-Shun Hsieh, Chia Yi Cheng, Hong Jie Chen, Shih Yu Huang
  • Patent number: 10790258
    Abstract: An electronic device includes an electronic element, a plurality of first sub-electrodes arrayed in a first direction, a plurality of second sub-electrodes arrayed in a second direction that is orthogonal to the first direction, a dummy electrode, and a sealing resin. The sealing resin has a resin back surface from which the plurality of first sub-electrodes, the plurality of second sub-electrodes and the dummy electrode are exposed. The plurality of second sub-electrodes are located further in the first direction than any of the plurality of first sub-electrodes. The plurality of first sub-electrodes are located further in the second direction than any of the plurality of second sub-electrodes. The dummy electrode is located further in the first direction than any of the plurality of first sub-electrodes, and is located further in the second direction than any of the plurality of second sub-electrodes.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 29, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hiroaki Matsubara, Yasumasa Kasuya, Taro Nishioka
  • Patent number: 10790418
    Abstract: A fabrication method for a light emitting diode (LED), including: 1) mounting a LED chip on a substrate; 2) mounting a screen printing template on the LED chip; 3) coating a silicone gel layer over the surface of the screen printing template; 4) printing the phosphor: printing the phosphor over the chip surface via silk screen printing process and recycling the excess phosphor; and 5) removing the screen printing template and baking the phosphor for curing, and coating the cured phosphor over the chip surface. In the packaging method of the present disclosure, the unused phosphor can be recycled because it is not polluted by the screen printing template material.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: September 29, 2020
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yi-Jui Huang, Kechuang Lin, Suhui Lin, Jiali Zhuo
  • Patent number: 10784209
    Abstract: The present invention relates to an electrical component. The present invention further relates to an electrical device comprising such an electrical component and to a flat no-lead package. According to the invention, the flat no-lead package comprises a semiconductor die comprising electrical circuitry that has a plurality of terminals for inputting and outputting one or more signals, a thermal pad on which the semiconductor die is mounted, a plurality of leads arranged spaced apart from the thermal pad, and a plurality of further leads that are integrally connected to the thermal pad. One or more terminals among the plurality of terminals are each connected to a respective lead, and one or more terminals among the plurality of terminals are each connected to a respective further lead.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 22, 2020
    Assignee: Ampleon Netherlands B.V.
    Inventor: Mariano Ercoli
  • Patent number: 10777519
    Abstract: Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Fook Hong Lee, Juan Boon Tan, Ee Jan Khor
  • Patent number: 10777520
    Abstract: A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Go-Hyun Lee, Jae-Taek Kim, Jun-Youp Kim, Chang-Man Son
  • Patent number: 10772228
    Abstract: Various embodiments of a sealed package and method of forming such package are disclosed. The package can include a housing having an inner surface and an outer surface, and a substrate having a first major surface and a second major surface. The package can also include an electronic device disposed on the first major surface of the substrate, and a power source disposed at least partially within the housing. The substrate can be sealed to the housing such that a non-bonded electrical connection is formed between a device contact of the electronic device and a power source contact of the power source.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: September 8, 2020
    Assignee: Medtronic, Inc.
    Inventors: John K Day, Michael J Nidelkoff, Kris A Peterson, Andrew J Ries, David A Ruben, Craig L Wiklund
  • Patent number: 10763201
    Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: September 1, 2020
    Assignee: Littelfuse, Inc.
    Inventors: Nathan Zommer, Kang Rim Choi
  • Patent number: 10761387
    Abstract: A liquid crystal display device includes a liquid crystal display element, a wiring substrate having a second terminal, and a light shielding mask. The liquid crystal display element includes a first substrate having a first terminal and a display pixel unit, and a second substrate disposed at a side where illumination light is irradiated to the first substrate. A bonding wire has an arch shape, is formed such that a top of the bonding wire is lower than an upper surface of the second substrate, is joined to the first terminal by first bonding, and is joined to the second terminal by second bonding. The light shielding mask has a light transmitting region corresponding to the display pixel unit and is disposed at a side where the illumination light is irradiated to the liquid crystal display element.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 1, 2020
    Assignee: JVC KENWOOD CORPORATION
    Inventor: Hiroaki Monjuji
  • Patent number: 10763195
    Abstract: The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 1, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Paolo Crema
  • Patent number: 10763196
    Abstract: A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering the entire surface of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: September 1, 2020
    Assignee: OHKUCHI MATERIALS CO., LTD.
    Inventors: Kaoru Hishiki, Keiichi Otaki, Hidehiko Sasaki, Kotaro Tomeoka
  • Patent number: 10739383
    Abstract: A shunt strip that includes a plurality of shunts arranged in a grid with each of the shunts spaced from an adjacent shunt by a shunt-gap. A plurality of tabs connect the plurality of shunts and at least one tab is positioned within each shunt-gap. Also, a shunt with a generally parallelepiped shaped body has severed tab portions extending outwardly and downwardly from the body.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: August 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Fatt Seng Yue, Wan Mohd Misuari Suleiman
  • Patent number: 10734313
    Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Morroni, Rajeev Dinkar Joshi, Sreenivasan K. Koduri, Sujan Kundapur Manohar, Yogesh K. Ramadass, Anindya Poddar
  • Patent number: 10734247
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 4, 2020
    Assignee: UTAC Headquarters PTE. LTD
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee