Lead Frame Patents (Class 257/666)
  • Patent number: 11367698
    Abstract: The present application provides a method of bonding an integrated circuit chip to a display panel. The method includes forming a plurality of first bonding pads in a bonding region on a first side of the display panel; forming a plurality of vias extending through the display panel in the bonding region; subsequent to forming the plurality of vias, disposing an integrated circuit chip having a plurality of second bonding pads on a second side of the display panel substantially opposite to the first side, the plurality of second bonding pads being on a side of the integrated circuit chip proximal to the display panel; and electrically connecting the plurality of first bonding pads respectively with the plurality of second bonding pads by forming a plurality of connectors respectively in the plurality of vias.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 21, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hongwei Ma, Youngyik Ko, Tairong Kim, Xiangdan Dong, Jinsan Park
  • Patent number: 11367820
    Abstract: The light emitting device package disclosed in the embodiment includes first and second frames spaced apart from each other; a body disposed between the first and second frames; a light emitting device including a first bonding portion and a second bonding portion on a lower portion thereof; and a first resin disposed between the body and the light emitting device, wherein the first frame includes a first protruding portion facing the first bonding portion of the light emitting device, and the second frame includes a second protruding portion facing the second bonding portion of the light emitting device, and including a first conductive layer between the first bonding portion and the first protruding portion and a second conductive layer between the second bonding portion and the second protruding portion.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 21, 2022
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Young Shin Kim, June O Song, Chang Man Lim, Won Jung Kim, Ki Seok Kim
  • Patent number: 11359985
    Abstract: The disclosed technology includes an oil-filled pressure transducer assembly and an oil-filled compensating sensing element disposed near one another and attached to a common housing. The oil-filled pressure transducer assembly may receive and measure pressure media via a first oil-filled cavity and a protective diagram in communication with the pressure media. The compensating sensing element may be isolated from the pressure media. In certain example implementations, the compensating sensing element is configured to measure certain common error phenomena that are also measured by the oil-filled pressure transducer assembly, for example, due to acceleration, temperature, and/or vibration. In certain implementations, the signal measured by the compensating sensing element may be subtracted from the signal measured by the oil-filled pressure transducer assembly to provide a compensated output signal.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 14, 2022
    Assignee: KULITE SEMICONDUCTOR PRODUCTS, INC.
    Inventors: Alexander A. Ned, Sorin Stefanescu, Andrew Bemis, Scott Goodman
  • Patent number: 11355896
    Abstract: An optoelectronic component comprising a laser diode is disclosed.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 7, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Andreas Wojcik, Markus Pindl
  • Patent number: 11355423
    Abstract: A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 7, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Frederick Arellano, Ernesto Antilano, Jr.
  • Patent number: 11348869
    Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: May 31, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Chien-Chou Chen, Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Patent number: 11342290
    Abstract: A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: May 24, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Kentaro Chikamatsu, Koshun Saito, Kenichi Yoshimochi
  • Patent number: 11342240
    Abstract: A transistor chip (2) has an active region (7). A first seal material (5) covers a central portion of the active region (7) and does not cover a peripheral portion of the active region (7). A second seal material (6) covers the peripheral portion of the active region (7). Thermal conductivity of the first seal material (5) is higher than thermal conductivity of the second seal material (6). Permittivity of the second seal material (6) is lower than permittivity of the first seal material (5).
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 24, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Okazaki
  • Patent number: 11342251
    Abstract: A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: May 24, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Enis Tuncer
  • Patent number: 11322430
    Abstract: A semiconductor device and a semiconductor module which can be reduced in size while ensuing insulation are provided. In the semiconductor device, a lead frame on which a circuit pattern is formed is provided on an insulation substrate; the circuit pattern of the lead frame is joined to the back-side electrode of a semiconductor chip via a solder layer, and the lead frame is electrically connected with the top-side electrode of the semiconductor chip via a wire; the lead frame 1 includes a terminal inside a mold-sealing resin and a terminal exposed to a space outside the mold-sealing resin, and the terminal is connected to a terminal block via a solder layer; and the lead frame, the insulation substrate, the semiconductor chip and the terminal block are integrally molded and sealed by the mold-sealing resin.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 3, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hodaka Rokubuichi, Kuniyuki Sato, Kiyofumi Kitai, Yasuyuki Sanda
  • Patent number: 11322444
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Patent number: 11315854
    Abstract: A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: April 26, 2022
    Assignees: FUJI ELECTRIC CO., LTD., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Hiromichi Gohara, Yoshinari Ikeda, Yoshikazu Takahashi, Kuniteru Mihara, Isao Takahashi
  • Patent number: 11309237
    Abstract: The present disclosure is directed to a semiconductor package including a substrate having a lower surface with a plurality of slot structures. The plurality of slot structures are multi-layer structures that encourage the formation of solder joints. The semiconductor package is desirable for high reliability applications in which each solder joint termination should be checked by visual systems to ensure a proper electrical connection has been made.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 19, 2022
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (MALTA) LTD
    Inventors: Marco Del Sarto, Alex Gritti, Pierpaolo Recanatini, Michael Borg
  • Patent number: 11309226
    Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Min Lin, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Hsiang Chiu, Sheng-Feng Weng, Yao-Tong Lai
  • Patent number: 11309250
    Abstract: An electronic module has a first substrate 11; an electronic element 13, 23 provided on one side of the first substrate 11; a sealing part 90 that seals at least the electronic element 13, 23; a connection terminal 110 electrically connected to the electronic element 13, 23 and exposed from a side surface of the sealing part 90; and a stress relaxation terminal 150, which is not electrically connected to the electronic element 13, 23, exposed from the side surface of the sealing part 90.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: April 19, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Kosuke Ikeda
  • Patent number: 11309273
    Abstract: An electronic module has a first substrate 11, a first electronic element 13 provided on one side of the first substrate 11, a first connection body 60 provided on one side of the first electronic element 13, a second electronic element 23 provided on one side of the first connection body 60, a second substrate 21 provided on one side of the second electronic element 23, and an abutment body 250 that abuts on a face on one side of the second electronic element 23 and is capable of imparting a force toward one side with respect to the second substrate 21.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 19, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kosuke Ikeda, Osamu Matsuzaki
  • Patent number: 11302661
    Abstract: A package substrate may include an insulation substrate, at least one redistribution layer (RDL) and a redistribution pad. The RDL may be included in the insulation substrate. The redistribution pad may extend from the RDL. The redistribution pad may include at least one segmenting groove in a radial direction of the redistribution pad. Thus, the at least one segmenting groove in the radial direction of the redistribution pad may reduce an area of the redistribution pad. Therefore, application of physical stress to a PID disposed over the redistribution pad may be suppressed, and thus generation of cracks in the PID may be reduced. Further, spreading of the cracks toward the redistribution pad from the PID may also be suppressed, and thus reliability the semiconductor package may be improved.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: April 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngkyu Lim, Gookmi Song, Sunguk Lee
  • Patent number: 11302594
    Abstract: A semiconductor package includes a substrate, an electronic component and a first dilatant layer. The electronic component is disposed on the substrate. The electronic component has a top surface, a bottom surface opposite to the top surface and a lateral surface extending between the top surface and the bottom surface. The first dilatant layer is disposed on the top surface of the electronic component and extends along the lateral surface of the electronic component.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11296000
    Abstract: An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies AG
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Patent number: 11296055
    Abstract: Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Mark Chen
  • Patent number: 11290144
    Abstract: A radio frequency module includes: a module board including first and second principal surfaces on opposite sides of the module board; a semiconductor integrated circuit (IC) including third and fourth principal surfaces on opposite sides of the semiconductor IC; and an external-connection terminal disposed on the second principal surface. The third principal surface faces the second principal surface and is closer to the second principal surface than the fourth principal surface is to the second principal surface, and the semiconductor IC includes: at least one of (i) a power amplifier (PA) control circuit configured to control a radio frequency component using a control signal, (ii) a low noise amplifier configured to amplify a reception signal, or (iii) a switch; and a signal electrode disposed on the fourth principal surface, and via the signal electrode the semiconductor IC is configured to receive or output a radio frequency signal and/or the control signal.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Daisuke Yoshida
  • Patent number: 11291146
    Abstract: The leadframe substrate mainly includes a modulator, a plurality of metal leads, a resin layer and a crack inhibiting structure. The resin layer provides mechanical bonds between the modulator and the metal leads disposed about peripheral sidewalls of the modulator. The crack inhibiting structure includes a continuous interlocking fiber sheet that covers the modulator/resin interfaces, so that the segregation induced along the modulator/resin interfaces or cracks formed within the resin layer can be prevented or restrained from extending to the top surfaces, thereby ensuring the signal integrity of the flip chip assembly.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: March 29, 2022
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 11284524
    Abstract: Embodiments of the present invention provide a method for packaging a printed circuit board assembly (PCBA), a packaged PCBA module, and a motor vehicle. The method includes: providing a printed circuit board assembly comprising a printed circuit board (PCB) and a plurality of elements assembled on the printed circuit board; providing a support constructed to carry the printed circuit board assembly and define a space for accommodating the printed circuit board assembly; placing the printed circuit board assembly in the space of the support to enable the support to carry and position the printed circuit board assembly, and placing the support and the printed circuit board assembly carried thereby in a mould; and filling the mould with a polymer material using a moulding process so as to form a packaging structure encapsulating at least the printed circuit board assembly and fixing the printed circuit board assembly relative to the support.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 22, 2022
    Assignee: VALEO COMFORT AND DRIVING ASSISTANCE
    Inventor: Stephane Schuler
  • Patent number: 11282772
    Abstract: A package structure includes at least one electronic device, a protection layer and an encapsulant. The electronic device has a first surface and includes a plurality of bumps disposed adjacent to the first surface thereof. Each of the bumps has a first surface. The protection layer covers the bumps and the first surface of the electronic device, and has a first surface. The encapsulant covers the protection layer and at least a portion of the electronic device, and has a first surface. The first surfaces of the bumps, the first surface of the protection layer and the first surface of the encapsulant are substantially coplanar with each other.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: March 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11276661
    Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first wiring structure and at least one electronic device. The at least one electronic device is connected to the first wiring structure through at least two joint structures. The at least two joint structures respectively include different materials.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11270954
    Abstract: The present invention relates to an electrical component. The present invention further relates to an electrical device comprising such an electrical component and to a flat no-lead package. According to the invention, the flat no-lead package comprises a semiconductor die comprising electrical circuitry that has a plurality of terminals for inputting and outputting one or more signals, a thermal pad on which the semiconductor die is mounted, a plurality of leads arranged spaced apart from the thermal pad, and a plurality of further leads that are integrally connected to the thermal pad. One or more terminals among the plurality of terminals are each connected to a respective lead, and one or more terminals among the plurality of terminals are each connected to a respective further lead.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 8, 2022
    Assignee: Ampleon Netherlands B.V.
    Inventor: Mariano Ercoli
  • Patent number: 11270984
    Abstract: In a semiconductor module, two switching elements are connected in parallel to each other. Each of the switching elements includes a first main electrode formed on one surface side, and a second main electrode and a gate electrode formed on a rear surface side opposite to the one surface side. A first conductor plate is coupled with two first main terminals at first coupling portions and is electrically connected with the first main electrodes. A second conductor plate is coupled with one second main terminal at a second coupling portion and is electrically connected with the second main electrodes. The second coupling portion is disposed between the switching elements in an alignment direction of the switching elements, and the first coupling portions are provided on both sides of the second coupling portion in the alignment direction.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 8, 2022
    Assignee: DENSO CORPORATION
    Inventors: Shunsuke Arai, Shinji Hiramitsu, Takuo Nagase
  • Patent number: 11264313
    Abstract: A semiconductor device includes a molded body and an interconnection layer. The molded body includes a semiconductor chip, at least one terminal body disposed around the semiconductor chip and a resin member provided between the semiconductor chip and the terminal body. The molded body has a first surface, a second surface opposite to the first surface and a side surface connected to the first and second surfaces. The interconnection layer is provided on the first surface of the molded body. The interconnection layer includes an interconnect electrically connecting the semiconductor chip and the terminal body. The terminal body has first and second contact surfaces. The first contact surface is exposed at the first or second surface of the molded body. The second contact surface is connected to the first contact surface and exposed at the side surface of the molded body.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: March 1, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akito Shimizu, Yasuhisa Shintoku, Yoshihisa Imori, Hiroaki Kishi, Atsushi Hosokawa, Tomohiko Imada, Shinya Shimamura
  • Patent number: 11257786
    Abstract: A semiconductor package including a package substrate; a first semiconductor chip on the package substrate; a second semiconductor chip on an upper surface of the first semiconductor chip; an insulating layer on surfaces of the first semiconductor chip and the second semiconductor chip; a heat dissipation member on the insulating layer such that the heat dissipation member includes a region on an upper surface of the first semiconductor chip on which the second semiconductor chip is not disposed, and a region on an upper surface of the second semiconductor chip; a molding member on the package substrate and encapsulating the first semiconductor chip, the second semiconductor chip, and the heat dissipation member such that the molding member exposes at least a portion of an upper surface of the heat dissipation member; and a reinforcing member on the heat dissipation member and the molding member.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunchul Kim, Kyungsuk Oh, Taehun Kim, Pyoungwan Kim
  • Patent number: 11244890
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun, Yu Zhang
  • Patent number: 11232999
    Abstract: The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability.
    Type: Grant
    Filed: February 16, 2020
    Date of Patent: January 25, 2022
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Jiaming Ye
  • Patent number: 11232342
    Abstract: An RFID tag includes a booster antenna, a feeding loop, an RFID module, and a sheet-like insulating base. The insulating base includes first and second sides that are opposite to each other. The booster antenna is comprised by one metal wire having one end on the first side of the insulating base and the other end on the second side of the insulating base and includes a first curved portion that reverses a direction of the metal wire extending from the one end and a second curved portion that reverses a direction of the metal wire, which is reversed by the first curved portion, to connect to the other end. Moreover, the RFID module is disposed in a region surrounded by the metal wire including the first curved portion and the second curved portion.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: January 25, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Ryohei Omori
  • Patent number: 11227776
    Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 18, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Frederick Ray Gomez
  • Patent number: 11227815
    Abstract: A semiconductor die includes first pads, switches that are electrically connected with the first pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the first pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the first pads based on a result of the operations, and a switch controller that controls the switches so that the first pads communicate with the test signal generator during a test operation and that the first pads communicate with the internal circuits after a completion of the test operation.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyo Kim, Chanho Kim, Daeseok Byeon
  • Patent number: 11229115
    Abstract: In a multilayer wiring board having through holes used in an electronic device, wiring is efficiently performed at high density while preventing crosstalk of differential signals. A wiring board includes: a plurality of pads arranged linearly at a predetermined pitch; a plurality of through holes arranged in parallel along an arrangement direction of the pads; and a wiring pattern connecting the pad to the through hole. Between the through holes connected to the pads which are connected to the ground via the wiring patterns, two through holes through which each of a pair of differential signals constituting a differential signal pair passes are provided such that a direction of a straight line connecting the two through holes is inclined to the arrangement direction of the pads.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 18, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Norio Chujo, Yutaka Uematsu, Masayoshi Yagyu
  • Patent number: 11222832
    Abstract: In a general aspect, an apparatus can include a leadframe. The apparatus can also include a first semiconductor die coupled with a first side of a first portion of the leadframe, and a second semiconductor die coupled with a second side of the first portion of the leadframe. The apparatus can also include a first substrate coupled with a second side of the first semiconductor die. The first substrate can be further coupled with a first side of a second portion of the leadframe and a first side of a third portion of the leadframe. The apparatus can also further include a second substrate coupled with a second side of the second semiconductor die. The second substrate can be further coupled with a second side of the second portion of the leadframe and a second side of the third portion of the leadframe.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: January 11, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tiburcio Maldo, Keunhyuk Lee, Jerome Teysseyre
  • Patent number: 11218651
    Abstract: An image sensor chip includes a substrate; an image sensor chip provided on the substrate; and an adhesive film provided between the image sensor chip and the substrate in a semi-cured state. A first width of the adhesive film is equal to a second width of the image sensor chip.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Sang Song, Hyunsu Jun
  • Patent number: 11217509
    Abstract: Present disclosure provides a lead frame, including a die paddle and a plurality of leads surrounding the die paddle. Each of the leads including a finger portion proximal to the die paddle and a lead portion distal from the die paddle. The finger portion includes a main body and at least one support structure. The respective support structures on adjacent leads are mutually isolated, and a distance between the support structure and the die paddle is smaller than a distance between the lead portion and the die paddle. A semiconductor package structure including the lead frame described herein and a semiconductor package assembly including the semiconductor package structure described herein are also provided.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: January 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jyun-Chi Jhan, Guo-Cheng Liao
  • Patent number: 11217507
    Abstract: The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 4, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11189541
    Abstract: A semiconductor package includes a substrate, an electronic component mounted on an upper surface of the substrate so that a lower surface of the electronic component faces the upper surface of the substrate, a heat slug disposed on an upper surface of the electronic component so that a lower surface of the heat slug faces the upper surface of the electronic component, a bonding material bonding the heat slug to the upper surface of the electronic component, and an encapsulant in which the heat slug and the electronic component are embedded. A side surface of the heat slug extending between an edge of the lower surface of the heat slug and an edge of an upper surface of the heat slug forms a recess with the upper surface of the electronic component.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 30, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung Mok Jang, Han Su Park, Hyun Kook Cho
  • Patent number: 11183436
    Abstract: A power integrated circuit (IC) includes a lead frame comprising a signal lead, a power lead, and a paddle attached to one or more of the signal lead and the power lead, an electrical component supported by the paddle, and a mold material configured to enclose a portion of the lead frame and expose a surface of the paddle, wherein the power lead has a first portion extending from an edge of the mold material outside of the mold material in a first direction and a second portion enclosed by the mold material and extending from the edge of the mold material inside the mold material in a second direction to the paddle, wherein the second direction is substantially opposite to the first direction. In embodiments, the paddle is only attached to the second portion of the power lead.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 23, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Natasha Healey, Rishikesh Nikam
  • Patent number: 11158776
    Abstract: A lead frame includes a plurality of unit structures, an outer frame, a plurality of extending portions, and a plurality of coupling portions. The unit structures each includes a first lead portion and a second lead portion aligned in a first direction, and grouped into first and second groups including a plurality of the unit structures aligned in the first direction. The extending portions each includes a first extending portion extending in the second direction and connecting the first lead portions of the unit structures in the first and second groups a second extending portion connecting the second lead portions of the unit structures in the first and second groups. The coupling portions connect all the first extending portions and the second extending portions. At least one of the extending portions located at one of ends in the first direction is not directly connected to the outer frame.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: October 26, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Kazuya Matsuda, Naofumi Sumitani
  • Patent number: 11152271
    Abstract: According to one aspect of the present disclosure, a semiconductor module includes a semiconductor chip having a first electrode, a second electrode, and a control electrode to receive a control signal that controls a current flowing between the first electrode and the second electrode, a package having an upper surface, a back surface that is an opposite surface of the upper surface, and a plurality of side surfaces provided between the upper surface and the back surface, the package containing the semiconductor chip, a first terminal provided to the package and being electrically connected to the first electrode, a second terminal provided to the package and being electrically connected to the second electrode and a control terminal electrically connected to the control electrode and being provided on all of the plurality of side surfaces of the package so as to surround the package.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: October 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Satoshi Kawabata
  • Patent number: 11152275
    Abstract: A semiconductor device includes a first insulating resin member sealing a mounting surface of a lead frame, and a second insulating resin member sealing a heat dissipating surface. The second insulating resin member contains a filler having a maximum diameter of 0.02 mm to 0.075 mm. The second insulating resin member includes a thin molded portion formed in contact with the heat dissipating surface of the lead frame. The thin molded portion has a thickness 1.1 times to 2 times the maximum diameter of the filler. The semiconductor device includes, at an interface between the first insulating resin member and the second insulating resin member, a mixture layer in which these resins are mixed with each other.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takanobu Kajihara, Katsuhiko Omae, Shunsuke Fushie, Yoshinori Kaneto, Junya Suzuki, Yuki Okabe
  • Patent number: 11152288
    Abstract: A lead frame includes a first die paddle, a second die paddle, a first lead, a second lead, and a third lead. The first lead is coupled to a first side of the first die paddle. The second lead is coupled to a second side of the first die paddle opposite to the first side of the first die paddle. The third lead is coupled to a first side of the second die paddle. At least one of the first lead, the second lead, and the third lead is coupled to the corresponding die paddle via a zigzag shaped tie bar.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: October 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Eric Lopez Bonifacio, Thorsten Hinderer, Fortunato Lopez, Norliza Morban
  • Patent number: 11145584
    Abstract: Provided is a semiconductor device that can improve yield and non-defective rate by obtaining the thickness of a melt-bonding material and suppressing inclination of a circuit board. The semiconductor device includes a circuit board including a circuit pattern layer, a semiconductor element mounted on the circuit board, a melt-bonding portion arranged on an upper surface of the circuit pattern layer, a bonding lead including a bonding portion facing the upper surface of the circuit pattern layer and electrically connected to the circuit pattern layer via the melt-bonding portion, and a pressing portion directly contacted with an upper surface of the circuit board.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: October 12, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Saegusa
  • Patent number: 11145574
    Abstract: Semiconductor device packages may include a die-attach pad and a semiconductor die supported above the die-attach pad. A spacer comprising an electrically conductive material may be supported above the semiconductor die or between the semiconductor die and the die-attach pad. A wire bond may extend from a bond pad on an active surface of the semiconductor die to the spacer. Another wire bond may extend from the spacer to a lead finger or the die-attach pad. An encapsulant material may encapsulate the semiconductor die, the spacer, the wire bond, the other wire bond, the die-attach pad, and a portion of any lead fingers.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 12, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Oliver Mabutas, Ekgachai Kenganantanon, Wichai Kovitsophon, Tarapong Soontornvipart, Peerapat Bunkhem
  • Patent number: 11145629
    Abstract: A semiconductor device, includes: first semiconductor element including first and second electrodes; second semiconductor element including third and fourth electrodes; sealing resin covering the semiconductor elements; first, second, third, and fourth terminal portions respectively connected to the first, second, third, and fourth electrodes and exposed from the sealing resin; first island portion where the first semiconductor element is mounted; and second island portion where the second semiconductor element is mounted, wherein four quadrants divided by first imaginary line extending along second direction orthogonal to first direction and second imaginary line extending along third direction orthogonal to both the first and second directions are defined.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 12, 2021
    Assignee: ROHM Co., Ltd.
    Inventors: Shozo Koyanagi, Seiji Nakashima
  • Patent number: 11142844
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 12, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, HyungMin Lee, ByungChun Kim, Robert J. Falster
  • Patent number: 11145566
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 12, 2021
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Jaspreet Singh Gandhi, Cheang-Whang Chang