Abstract: An electronic component package according to one aspect of the present disclosure includes a metal pattern layer having a first principal surface and a second principal surface, an electronic component disposed on the first principal surface and electrically connected to the metal pattern layer, at least one metal member disposed on the first principal surface and electrically connected to the metal pattern layer, a sealing resin layer disposed on the first principal surface, the electronic component and the at least one metal member, and an insulating layer disposed on the second principal surface. The at least one metal member is thicker than the electronic component. In plan view, the at least one metal member is disposed on an area of the first principal surface, the area including an end of the first principal surface. The at least a part of the metal pattern layer is exposed from the insulating layer.

Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Abstract: An image acquisition system, in particular for automotive applications, includes: a substrate; an image sensor mounted on the substrate and contacted via contact points; an optically transparent sealing compound that covers the image sensor, the contact points, and a portion of the upper substrate side; an optical device being arranged or secured in or on the sealing compound. The optical device can be placed into the sealing compound after shaping of the sealing compound or directly. Furthermore, the optical device can also be arranged directly by shaping the sealing compound. Manufacture of the image acquisition system can be incorporated into a board populating process.

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for vacuum lamination of a depth-sensing camera module PCB to a stiffener using built-in vacuum channels.

Abstract: A laminate includes a core, a buildup layer having a top and a bottom, the bottom contacting the core and a solder mask contacting the top, the solder mask including at least one warpage control region formed on a top surface of the solder mask.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract: An object is to provide a technique in which a cost reduction in a power semiconductor device can be achieved while maintaining heat dissipation performance as much as possible. A power semiconductor device includes a leadframe, a power semiconductor element disposed on an upper surface of the leadframe, and an insulating layer disposed on a lower surface of the leadframe. At least a partial line of a peripheral line of a region where the insulating layer is disposed, on the lower surface, is aligned, in top view, with at least a partial line of an expanded peripheral line obtained by shifting outwardly, by the amount corresponding to the thickness of the leadframe, the peripheral line of the region where the power semiconductor element is disposed, on the upper surface.

Abstract: A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.

Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.

Abstract: In a method of manufacturing a semiconductor device according to an embodiment, a lead frame is provided, the lead frame having a trench part formed thereon so as to communicate bottom surfaces of a first lead and a second lead, which are coupled to each other between device regions adjacent to each other. Then, after a part of a coupling part between the first and second leads is cut by using a first blade, metal wastes formed inside the trench part are removed. Then, after the metal wastes are removed, a metal film is formed on exposed surfaces of the first and second leads by a plating method, and then, a remaining part of the coupling part between the first and second leads is cut by using a second blade. At this time, the cutting is performed so that the second blade does not contact the trench part.

Abstract: A MEMS lead frame package body encloses a MEMS device enclosed in an internal cavity formed by the mold body and cover. To accommodate a MEMS microphone, an acoustic aperture extends through the mold body. In some embodiments, a conductive column extends through the pre-molded body to allow electrical connection from a partially encapsulated lead frame to the conductive cover. Some embodiments may include a multi-tiered cavity within the mold body for mounting an integrated circuit separated by a gap above the MEMS device.

Abstract: A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer and providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer. A through hole is formed to penetrate the upper package, and the upper package and lower package are electrically connected. A thermal interface material is injected into the through hole to form a first heat transmission part between, and in contact with, the upper package and the lower package.

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract: The semiconductor device in accordance with one mode comprises a semiconductor chip; a chip mounting substrate on which the semiconductor chip is mounted; a chip container that is provided on the chip mounting substrate and contains the semiconductor chip; and a seal part that seals the chip container containing the semiconductor chip and the chip mounting substrate. The chip container has a frame part surrounding a periphery of the semiconductor chip. The height of the frame part is greater than that of the semiconductor chip. The inside of the frame part in the chip container is provided with a chip coating material that protects the semiconductor chip.

Abstract: A wiring board unit includes: a polygonal wiring board having three or more sides in top view, a product insulating part comprising a plurality of external terminals, and a dummy insulating part at an outer edge of one of the at least three sides; and a lead frame including a frame having an inner edge defining an opening within which the wiring board is disposed in top view, and a plurality of leads, one end of each of the plurality of leads connected to the inner edge of the frame and the other end of each of the plurality of leads respectively connected to one of the plurality of external terminals of the wiring board, wherein a connection unit for connecting the frame of the lead frame and the dummy insulating part of the wiring board is arranged therebetween.

Abstract: An optical module for an optical unit associated with forming a light curtain for monitoring a protective or surveillance field. The optical module includes at least one radiation emitting and/or radiation receiving element for transmitting and/or receiving a radiation beam associated with forming a light curtain. The optical module includes a module body for mounting a radiation transmitter/receiver carrier that carries the at least one transmitting and/or receiving element associated with the radiation beam. The module body has at least one alignment element for aligning the optical module within a support element that forms an outer housing of the optical unit.

Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle.

Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.

Abstract: Embodiments of the present invention disclose a method for encapsulating a component with plastic and its encapsulation structure, which belong to the plastic encapsulation technology field. The method includes: processing, by using the surface mounting technology, a first surface of a part to be encapsulated with plastic and/or performing die bonding on the first surface; encapsulating, with plastic, the first surface of the part to be encapsulated with plastic a second surface of the part to be encapsulated with plastic the first surface and/or performing die bonding in the second face; and encapsulating, with plastic, the second surface of the part to be encapsulated with plastic. This encapsulation structure includes a substrate, where components are fixed on an upper surface and a lower surface of the substrate, and the components on the upper surface and lower surface are all encapsulated with plastic in seal.

Abstract: Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed.

Abstract: A method for producing a component having a semiconductor substrate with through-hole plating is provided, the through-plating being surrounded by a recess, and the semiconductor substrate having a first layer on one side, which covers the recess on the first side. The semiconductor substrate has a second layer on a second side, which covers the recess on the second side, and the through-hole plating is surrounded by a ring structure which is produced from the semiconductor substrate. The recess surrounding the ring structure is produced in the same process step or at the same time as the recess for the through-hole plating.

Abstract: In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands.

Abstract: A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the length of resin bleed.

Abstract: A surface-mountable electronic device free of leads has a plurality of solderable connection surfaces at its lower side, with at least one of the connection surfaces having a rectangular portion. The outline of this rectangular portion corresponds to a connection surface of the JEDEC Standard MO-236 or of any other standard according to which the respective connection surface should not extend directly up to a side edge of the lower device side. The at least one connection surface furthermore has an extension section which extends, starting from the rectangular portion, in the direction of a side edge of the lower side of the device.

Abstract: A light emitting diode (LED) package is provided. According to an embodiment, a light emitting apparatus includes a substrate; at least two distinct electrodes on the substrate; a light emitting device on one of the at least two distinct electrodes, wherein the at least two distinct electrodes are electrically separated from each other and spaced from each other; a guide unit on the substrate and around the light emitting device, wherein the guide unit includes an inner side surface, an outer side surface, a top surface and a bottom surface; and lenses including a first lens and a second lens on the substrate, wherein at least one of the lenses includes a convex shape and a portion of the at least one of the lenses is located higher than the top surface of the guide unit.

Abstract: A trench portion (trench) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.

Abstract: Semiconductor packages having lead frames include a lead frame, which supports a semiconductor chip and is electrically connected to the semiconductor chip by bonding wires, and a molding layer encapsulating the semiconductor chip. The lead frame includes first lead frames extending in a first direction and second lead frames extending in a second direction. The first lead frames may run across the semiconductor chip and support the semiconductor chip and the second lead frames may run across the bottom surface of the semiconductor chip.

Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.

Abstract: An integrated circuit package system including: providing a die pad with a top, sides, and a bottom, the bottom having a relief with a flat surface and defining a wall and a center pad; mounting a barrier under the bottom of the die pad; mounting an integrated circuit die on the top of the die pad; encapsulating the integrated circuit die and the top and sides of the die pad with the wall preventing encapsulation from flowing along the barrier to reach the center pad; and mounting an external interconnect on the center pad.

Abstract: A light emitting diode (LED) package is provided. The LED package includes a printed circuit board (PCB), an electrode pad, an LED, a wire, and first and second moldings. The electrode pad and the LED are formed on the PCB. The wire electrically connects the LED with the electrode pad. The first molding is formed on the LED and the second molding is formed on the first molding.

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.

Abstract: A MEMS lead frame package body encloses a MEMS device enclosed in an internal cavity formed by the mold body and cover. A conductive internal shell with a connection window sits in the cavity. The MEMS device is mounted in the shell and electrically coupled to the lead frame through wire bonds directed through the connection window. To accommodate a MEMS microphone, an acoustic aperture extends through the mold body aligned with a hole in the internal shell.

Abstract: The present invention has a tray corresponding to a heat sink, a circuit part is accommodated in an accommodating part of the tray, and the circuit part is potting-sealed with a sealing resin such that external electrodes are exposed. The sealing resin covers and seals a top part of the tray.

Abstract: An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (411) to die pads in cavities (41-45, 51-55) of a leadframe, the cavities arranged in a matrix of columns and rows; (b) electrically connecting the dice to a plurality of conducting portions (412-414) of the leadframe; and (c) longitudinally injecting molding material into the cavities along the columns via a plurality of longitudinal gates (46-49, 56-59) of the leadframe to package the dice in the cavities, the longitudinal gates situated between the cavities along the columns.

Abstract: A process for assembly of an integrated device, envisages: providing a first body of semiconductor material integrating at least one electronic circuit and having a top surface; providing a second body of semiconductor material integrating at least one microelectromechanical structure and having a bottom surface; and stacking the second body on the first body with the interposition, between the top surface of the first body and the bottom surface of the second body, of an elastic spacer material. Prior to the stacking step, the step is envisaged of providing, in an integrated manner, at the top surface of the first body a confinement and spacing structure that confines inside it the elastic spacer material and supports the second body at a distance from the first body during the stacking step.

Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.

Abstract: To enhance the reliability of a semiconductor device. The semiconductor device includes die pads, over which a first semiconductor chip and a second semiconductor chip are mounted respectively, a plurality of support pins that support each of the die pads, a plurality of inner leads and outer leads arranged around the die pads, a plurality of wires that electrically couple the semiconductor chips to the inner leads, and a sealing body that seals the semiconductor chips, the inner leads, and the wires. Each of the die pads is supported by three support pins integrally formed together with the die pad, and each of second support pins of each pair of the three support pins is arranged between the inner leads adjacent to each other.

Abstract: A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

Abstract: An integrated circuit package system that includes: providing a support structure including a device and an electrical contact adjacent thereto; providing a mold system having a cavity, a recess channel, a recess integrally connected to the recess channel, and a resilient member that cooperatively engages the recess channel and the recess; engaging the mold system and the support structure with the cavity over the device and the resilient member between the device and the electrical contact; and injecting encapsulation material into the cavity.

Abstract: A light emitting device comprises a substrate including a top surface that is flat, a light emitting diode on the substrate, a lead frame formed on the flat top surface of the substrate. The lead frame includes a circuit with a predetermined pattern to electrically connect to the light emitting diode. A dam part is formed on the substrate and is adjacent to the light emitting diode. A first member is formed on the light emitting diode, the first member including a fluorescent substance to convert a light emission spectrum of light from the light emitting diode. A second member is surrounded by the dam part and is formed on the substrate adjacent to the first member, and a lens covers the first member, the second member and the light emitting diode.

Abstract: A semiconductor package includes a lead frame, a semiconductor die, bond wires providing an electrical connection between the die and the lead frame, and a mold compound that encapsulates the lead frame, the die and the bond wires. The lead frame includes spaced apart first and second frame members each having an inner peripheral edge and an opposing outer peripheral edge, spaced apart lead pads disposed between the inner peripheral edges of the first and second frame members, and conductive leads disposed proximate to the outer peripheral edge of each of the first and second frame members. The die is mounted on the lead pads.

Abstract: A semiconductor package includes a lead frame, a semiconductor die, bond wires providing an electrical connection between the die and the lead frame, and a mold compound that encapsulates the lead frame, the die and the bond wires. The lead frame includes spaced apart first and second frame members each having an inner peripheral edge and an opposing outer peripheral edge, spaced apart lead pads disposed between the inner peripheral edges of the first and second frame members, and conductive leads disposed proximate to the outer peripheral edge of each of the first and second frame members. The die is mounted on the lead pads.

Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.

Abstract: A lead frame having a die support area for supporting a semiconductor die, a plurality of leads surrounding the die support area, and a dam bar connecting adjacent leads. The dam bar has a dummy tab between adjacent ones of the leads that transversely extends towards the die support area. The presence of the dummy tab reduces the volume of mold compound between the lead frame leads and thus, when the lead frame is cut via punching, only the lead frame is cut and not the molding material. This reduces mechanical stress during singulation significantly and as a result, the occurrence of package cracking is reduced. In addition, less mold compound at the dam bar inter-lead reduces debris during cutting, which in turn reduces debris from contaminating the package.

Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.