Abstract: A wiring board of the present disclosure includes a core substrate, insulating layers, signal wiring conductors, ground wiring conductors, power-supply wiring conductors, a first mounting portion on which a first semiconductor device is to be mounted, a second mounting portion on which a second semiconductor device is to be mounted, many first-semiconductor-device connection pads connectable to signal electrodes of the first semiconductor device, many second-semiconductor-device connection pads connectable to signal electrodes of the second semiconductor device, and many signal connection conductors that connect the first-semiconductor-device connection pads to the second-semiconductor-device connection pads.

Abstract: An interdigitated back contact solar cell is provided. The solar cell comprises a solar cell substrate having a light receiving frontside and a backside comprising base and emitter regions. A first level metal (M1) layer is positioned on the substrate backside contacting the base and emitter regions. A second level metal (M2) layer is connected to the first level metal (M1) layer and comprises a base busbar and an emitter busbar. The first level metal comprises substantially orthogonal interdigitated metallization and substantially parallel interdigitated metallization positioned under and corresponding to the base and emitter busbars on the second level metal (M2). The substantially parallel interdigitated metallization of M1 collects carriers of opposite polarity of the corresponding busbar.

Abstract: An electronic component package includes a redistribution layer, an electronic component disposed on the redistribution layer, and an encapsulant encapsulating the electronic component. The electronic component has a trench formed in one side thereof.

Abstract: A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency comprises: a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to the following sub-steps in the following order: A1)) the electronic packages are placed on a first sticky skin, balls side, B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer, C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls, D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls, E1) thinning of the intermediate wafer on the balls side face, F1) formation of a balls side redistribution layer, G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract: The present disclosure provides a liquid crystal display module, which includes a liquid crystal display panel and a driver integrated circuit, wherein the liquid crystal display panel includes a testing pad, a first pad and a second pad, the first pad includes a first sub pad and a second sub pad which are separately disposed, the second sub pad is electrically connected to the testing pad, the driver integrated circuit includes at least two third pads, the third pads are respectively bonded to the first pad and the second pad; the first sub pad and the second sub pad are commonly bonded to one of the third pads, so as to achieve a short circuit between the first sub pad and the second sub pad. In the liquid crystal display module of the present disclosure, the space occupied by the bonding area is small.

Abstract: Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including a wire having a bonding electrode at a distal end portion solder-bonded to the bump, in which the bonding electrode is pressed against the bump by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature.

Abstract: In a display device connected with an IC driver, particularly the reliability of connection between an IC terminal located on the outermost side and the IC driver is improved. IC terminals and flexible wiring board terminals are formed on a terminal region of a TFT substrate. A plurality of the IC terminals are formed at a predetermined pitch. The reliability of an outermost IC terminal is degraded as compared with the reliability of the other IC terminals caused by the loading effect in etching a protection insulating film. In order to prevent this degradation, a dummy terminal is formed on the outer side of the outermost IC terminal, and the loading effect on the outermost IC terminal is made equal to the loading effect on the other IC terminals. Accordingly, degradation in the reliability of the outermost IC terminal is prevented.

Abstract: A mold release film, which is excellent in releasability and capable of suppressing contamination of a mold or a resin-encapsulation portion by the mold release film and forming a resin-encapsulation portion excellent in adhesion to an ink layer, is provided. The mold release film is disposed on a cavity surface of a mold, in which a semiconductor element is disposed and encapsulated with a curable resin to form a resin-encapsulation portion. The mold release film has a first surface in contact with the curable resin when the resin-encapsulation portion is formed, and a second surface in contact with the cavity surface. At least the first surface is made of a fluororesin. The mold release film has an F/Al ratio of from 0.2 to 4, or an F/(C+F+O) ratio of from 0.1 to 0.3. A process for producing a semiconductor package using the mold release film is also provided.

Abstract: The present disclosure provides a lighting module. The lighting module includes a heat sink, a board disposed over the heat sink, and a bonding component that bonds the heat sink and the board together. The bonding component contains a combination of a first metal and a second metal. The lighting module also includes a photonic lighting device disposed over the board.

Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.

Abstract: This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first wiring layer having a first metal wire and a first dielectric material layer surrounding the first metal wire; a conductive pillar layer formed on the first wiring layer and including a first metal pillar connected to the first metal wire and a molding compound layer surrounding the first metal pillar; a flexible material layer formed on the conductive pillar layer and including a first opening formed on the first metal pillar and exposing the first metal pillar; and a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the first metal pillar through the first opening, a second metal pillar formed on the second metal wire, and a protective layer surrounding the second metal wire and the second metal pillar.

Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

Abstract: A disclosed circuit arrangement includes a substrate having first bond pads coupled to a pattern of conductors. The first bond pads and the pattern of conductors are disposed on a first surface of the substrate. A first layer of adhesive is directly disposed on the first surface of the substrate and the pattern of conductors and has openings at the first bond pads. An electronic device has opposing first and second surfaces and is attached to the first surface of the substrate by the first surface of the electronic device in contact with the first layer of adhesive. The second surface of the electronic device has second bond pads. Bond wires are connected at the first bond pads through the openings in the first layer of adhesive and connected at the second bond pads.

Abstract: The present disclosure provides a method of forming a biocompatible structure that includes forming biodissolvable substrate comprising a flexible network of peptides, and a biocompatible structure having a biodissolvable substrate and, optionally, an electronic device on a surface thereof for use in implantable electronics.

Abstract: The invention relates to a method for connecting a power semi-conductor chip having upper-sided potential surfaces to thick wires or strips, consisting of the following steps: Providing a metal molded body corresponding to the shape of the upper-sided potential surfaces, applying a connecting layer to the upper-sided potential surfaces or to the metal molded bodies, and applying the metal molded bodies and adding a material fit, electrically conductive compound to the potential surfaces prior to the joining of the thick wire bonds to the non-added upper side of the molded body.

Abstract: Semiconductor devices and methods are provided. The semiconductor device can include a semiconductor substrate, a plurality of solder pads disposed on the semiconductor substrate, a first insulating layer disposed over the semiconductor substrate, a columnar electrode disposed over the solder pad, and a solder ball disposed on the columnar electrode. The first insulating layer can include a first opening to expose a solder pad of the plurality of solder pads. The columnar electrode can include a bulk material and a through hole in the bulk material. The through hole can expose at least a surface portion of the solder pad. The solder ball can include a convex metal head on a top surface of the bulk material of the columnar electrode, and a filling part filled in the through hole.

Abstract: A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

Abstract: An electronic element surface-mounted on a substrate has a leg part that protrudes from a back surface of the electronic element toward a heat sink along a peripheral portion of a back electrode. As such, if the substrate warps, the protruding leg part abuts a heat reception surface of the heat sink, thereby preserving an insulation gap between the back electrode and the heat sink. As a result, short-circuiting is prevented.

Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

Abstract: Provided is a printed circuit board, including: a support substrate including a first region in which light emitting elements are mount, a second region extending from the first region, and a bending portion between the first region and the second region, an insulating substrate on the support substrate, wiring portions on the insulating substrate, and a protective layer on the wiring portions.

Abstract: An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.

Abstract: The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.

Abstract: A method of making an integrated circuit package that contains a semiconductor die having one or more electrical connections to an electronic circuit within the semiconductor die. The method may include: encapsulating the semiconductor die and its electrical connections in non-electrically conductive, encapsulation material; laser drilling the encapsulation material to expose one of the electrical connections within the integrated circuit package, thereby creating a via opening in an external surface of the encapsulation material to the electrical connection; and electroplating or sputtering over the via opening in the encapsulation material to create a conductive routing layer from the exterior surface of the encapsulation material to the electrical connection.

Abstract: The light emitting device package may include a light emitting device including at least one light emitting diode and a body including at least one lead frame on which a light emitting device is disposed, the body provided a first protrusion formed on a outside of the body, wherein the width of a lower surface of the first protrusion is 0.5 times to 0.9 times the width of a upper surface of the first protrusion.

Abstract: A display for a construction machine includes: a metal case that is detachably supported on a construction machine frame via a universal joint (a joint member); a liquid crystal display (a display unit) that is attached to the metal case; and a control board that is attached to the metal case and is configured to perform a display control on the liquid crystal display.

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

Abstract: A light emitting device with a heat sink composed of two materials is provided. The device comprises: a light emitting material; and, a heat sink comprising: a first material configured to cool the light emitting material, the first material comprising a first coefficient of thermal expansion (CTE); and, a second material bonded to the first material at an interface there between, the second material comprising a second CTE lower than the first CTE, the light emitting material bonded to the first material but not the second material.

Abstract: An assembly method of direct-docking probing device is provided. First, a space transforming plate made by back-end-of-line semiconductor manufacturing process is provided, so the thickness of the space transforming plate is predetermined by the client of probe card manufacturer. Then a reinforcing plate in which a plurality of circuits disposed is provided, which has larger mechanical strength than the space transforming plate. After that the reinforcing plate and the space transforming plate are joined and electrically connected by a plurality of solders so as to form a space transformer. Then, a conductive elastic member and a probe interface board are provided. Thereafter, the space transformer and the conductive elastic member are mounted on the probe interface board. After that, at least one vertical probe assembly having a plurality of vertical probes is mounted on the space transforming plate, and the vertical probes is electrically connected with the space transforming plate.

Abstract: A LED filament and a LED filament bulb using the same are disclosed. The LED filament includes a carrier, a LED chip disposed on the carrier and a conductive lead connected to the carrier. The conductive lead is electrically connected to the LED chip and includes a lead head portion, a lead tail portion and a lead neck portion connecting the lead head portion with the lead tail portion. A solid body width of the lead neck portion is less than a maximum solid body width of the lead head portion. Because the lead neck portion with reduced solid body width can function as a vulnerable position of the conductive lead, when a stress is applied onto the conductive lead, the lead neck portion would first take action and therefore the bonding location between the lead head portion and the carrier or the carrier itself can be protected.

Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing an unplated leadframe having a contact protrusion; forming a contact pad and traces by etching the unplated leadframe; applying a trace protection layer on the contact pad and the traces; forming a recess in the trace protection layer by etching a top surface of the contact pad to a recess distance below a top surface of the trace protection layer; and depositing an external connector directly on the top surface of the contact pad.

Abstract: A lithium ion battery includes a first substrate having a first main surface, and a lid including a conductive cover element, the lid being attached to the first main surface. A cavity is formed between the first substrate and the lid. The battery further includes an electrolyte disposed in the cavity. An anode of the battery includes a component made of a semiconductor material and is formed at the first substrate, and a cathode of the battery is formed at the lid.

Abstract: A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.

Abstract: A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second conductive pillar layer, a first molding compound layer and a second conductive wiring layer. The first conductive pillar layer is disposed on the first conductive wiring layer. The first conductive glue layer is disposed on the first conductive wiring layer. The internal component has a first electrode layer and a second electrode layer, wherein the first electrode layer is disposed and electrical connected to the first conductive glue layer. The second conductive pillar layer is disposed on the second electrode layer. Wherein the first conductive wiring layer, the first conductive pillar layer, the first conductive glue layer, the internal component and the second conductive pillar layer are disposed inside the first molding compound layer.

Abstract: An LED lamp includes: a plurality of light source units, each of which includes one or more LED chips and an emission surface through which light from the LED chips is emitted; and a lens unit having a plurality of lenses, each of which is located in front of the emission surface of each of the plurality of light source units.

Abstract: A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having terminals for connection with a circuit panel or other external component. A second microelectronic element overlies a rear surface of the first microelectronic element and has contacts electrically coupled with the substrate through electrically conductive interconnects extending through a region of the first microelectronic element. A heat spreader is thermally coupled with the rear surface of the substrate, either directly or through an additional element overlying the rear surface. Additional contacts of the second microelectronic element may be coupled with contacts of the substrate through electrically conductive structure disposed beyond an edge surface of the first microelectronic element.

Abstract: A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Abstract: A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.

Abstract: A semiconductor device includes a center semiconductor chip with a plurality of die pads, a plurality of lead frames, and a plurality of connecting components. The lead frame encapsulates the center semiconductor chip. Each connecting components establishes an electrical connection between the center semiconductor chip and the lead frame. At least one of the center semiconductor chip, the lead frame, and the connecting component forms an indicator.

Abstract: Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

Abstract: According to one embodiment, a radiation detection device includes a chassis, a radiation detection panel, a support plate and a circuit board. The chassis includes an incident face cover and a side face portion covering a side face perpendicular to the incident face cover. The radiation detection panel is housed inside the chassis and is configured to detect radiation incident through the incident face cover. The support plate is housed inside the chassis and is fixed to the side face portion to support the radiation detection panel on a rear face on an opposite side to an incident face of the radiation. The circuit board is housed inside the chassis and is disposed on an opposite side to the radiation detection panel of the support plate. At least a part of a drive circuit configured to drive the radiation detection panel is mounted on the circuit board.

Abstract: A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad is formed on a principal surface of the first semiconductor chip, and a first bump is formed on the first electrode pad. A second bump is formed on the principal surface of the second semiconductor chip such that the second bump is bonded to the first bump. The first electrode pad has an opening, and the opening and an entire peripheral portion of the opening form a stepped shape form a stepped shape. The first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape.

Abstract: An ultrasonic measuring apparatus includes an ultrasonic transducer device having a substrate and an ultrasonic transducer element array that is arranged on the substrate, a first channel terminal group arranged at one edge portion of the ultrasonic transducer element array in a first direction, a second channel terminal group arranged at the other edge portion of the ultrasonic transducer element array in the first direction, a first flexible substrate provided on the one edge portion side and having arranged thereon a first wiring group that is connected to the first channel terminal group, a first integrated circuit apparatus that is mounted on the first flexible substrate and performs at least one of signal transmission to the first channel terminal group and signal reception from the first channel terminal group, a second flexible substrate provided on the other edge portion side and having arranged thereon a second wiring group that is connected to the second channel terminal group, and a second integra

Abstract: To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window.

Abstract: The method comprises providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.