Abstract: A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.

Abstract: A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion.

Abstract: A semiconductor package has multiple dies and an interior power bar that extends within an interior space formed within the die flag between the dies. The bond pads located on the interior side of each die are wire-bonded to the interior power bar. Some embodiments may have more than two dies and/or more than one interior power bar between each pair of adjacent dies.

Abstract: A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group.

Abstract: The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar.

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via.

Abstract: A semiconductor device includes: a die pad comprised of a metal, and having at least one cutout portion in its peripheral edge portion, and a protruding portion formed by the cutout portion so as to protrude laterally from the peripheral edge portion; an inner lead having at its end a bonding pad that is placed in the cutout portion with an interval between the bonding pad and the die pad; a semiconductor chip held on the die pad so that a center position of the semiconductor chip is located on the protruding portion side with respect to a center position of the die pad; and a wire configured to electrically connect the semiconductor chip to the bonding pad.

Abstract: A light-emitting diode device includes a base substrate including a plurality of quantum well layers, a first electrode on one side of the plurality of quantum well layers, and a second electrode on an opposite side of the plurality of quantum well layers. The device includes a tensile-stressing layer formed on the base substrate and having a thickness and chemical composition configured to generate a first tensile stress in the base substrate, the first compressive stress selected to cause the base substrate to have a predetermined band-gap.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Abstract: In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands.

Abstract: A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group.

Abstract: A surface mount semiconductor device is assembled by positioning an array of semiconductor dies with an array of metallic ground plane members between and beside the semiconductor dies. The arrays of dies and ground plane members are encapsulated in a molding compound. A redistribution layer is formed on the arrays of dies and ground plane members. The redistribution layer has an array of sets of redistribution conductors within a layer of insulating material. The redistribution conductors interconnect electrical contacts of the dies with external electrical contact elements of the device. As multiple devices are formed at the same time, adjacent devices are separated (singulated) by cutting along saw streets between the dies. The molding compound is interposed between tie bars of the ground plane members and the insulating material of the redistribution layer in the saw streets, and at the side surfaces of the singulated devices.

Abstract: A microelectronic device package including a package substrate, microelectronic component disposed on a first surface of a first portion of the substrate, and encapsulant material surrounding the microelectronic electronic component. An exposed surface of the first portion of the substrate is exposed through an opening in a first major surface of the encapsulant material. The exposed surface of the first portion has an edge. Encapsulant material is adjacent to the edge at the first major surface. The exposed surface is opposite the first surface. A stress relief feature located in one of the first major surface or a second major surface of the encapsulant material. The second major surface is opposite the first major surface. The stress relief feature reduces an amount of the encapsulant material and is 1 mm or less of a plane of the edge of the exposed surface. The plane is generally perpendicular to the exposed surface.

Abstract: Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating is generally co-planar with the outer surface of the bond sites carried by the projection.

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

Abstract: A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers.

Abstract: A substrate structure has a first surface and a second surface. A plurality of carrying members are formed on the first surface and a plurality of conductive traces are formed on the second surface. In addition, the substrate structure has a first, a second and a third thermal stress relief structures. The first thermal stress relief structure is that lengths of the substrate structure in different axial directions are substantially equal to each other. The second thermal stress relief structure is that a plurality of separated alignment marks are formed on the substrate structure. The third thermal stress relief structure is that the substrate structure has at least one clearance area extending along one of the axial directions of the substrate structure and the clearance area has no carrying members and no conductive traces formed thereon.

Abstract: A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.

Abstract: The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe.

Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Abstract: Methods of and devices for providing escaping routes for the flux and gases generated to move away from the solder joint in the process of solder joint formation.

Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing 98 wt % or more of one metallic element such as silver having a melting point of 400° C. or higher, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.

Abstract: A flexible printed circuit board, in particular for the spatial connection of electronic components, includes a carrier foil (1), several bonding surfaces (10) arranged on a solder side (4) of the carrier foil (1), and several soldering surfaces (2) arranged on a bonding side (12) of the carrier foil (1) opposite the solder side. The soldering surfaces (2) are connected to the bonding surfaces (10) via electrical strip conductors, and a stiffening plate (3) is inseparably connected to the carrier foil (1) on the solder side thereof.

Abstract: Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.

Abstract: Various stress relief structures are provided for effectively reducing thermal stress on a semiconductor chip in a chip package. Trenches on a metal substrate are created in groups in two-dimension, where each trench is opened from top or bottom surface of the metal substrate and in various shapes. The metal substrate is partitioned into many smaller substrates depending on the number of trench groups and partitions, and is attached to a semiconductor chip for stress relief. In an alternative embodiment, a plurality of cylindrical metal structures are used together with a metal substrate in a chip package for the purpose of heat removal and thermal stress relief on a semiconductor chip. In another alternative embodiment, a metal foam is used together with a semiconductor chip to create a chip package. In another alternative embodiment, a semiconductor chip is sandwiched between a heat sink and a circuit board by solder bumps directly with underfill on the circuit board.

Abstract: An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer.

Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.

Abstract: A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 ?m or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.

Abstract: A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup layer laminated on first surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on second surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost interlayer resin insulation layer of the first buildup layer has thermal expansion coefficient which is set lower than thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.

Abstract: An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips.

Abstract: A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.

Abstract: A semiconductor structure having a first corner includes a carrier, a first protective layer, a second protective layer, and a third protective layer. The carrier comprises a carrier surface having a protection-layered disposing zone. The first protective layer comprises a first surface having a first disposing zone, a first anti-stress zone and a first exposing zone, the first anti-stress zone is located at a corner of the first disposing zone, the second protective layer is disposed at the first disposing zone. The second protective layer comprises a second surface having a second disposing zone, a second anti-stress zone and a second exposing zone, the second anti-stress zone is located at a corner of the second disposing zone. The first anti-stress zone and the second anti-stress zone are located at the first corner. An area of the first anti-stress zone is not smaller than that of the second anti-stress zone.

Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

Abstract: A method of manufacturing a lead frame, includes forming a rectangular first dimple includes, first inclined side surfaces inclined to a depth direction, and arranged in two opposing sides in one direction, and standing side surfaces standing upright to a depth direction, and arranged in two opposing sides in other direction, on a backside of a die pad by a first stamping, and forming a second dimple having second inclined side surfaces inclined on the backside of the die pad by a second stamping, such that a second inclined side surfaces of the second dimple are arranged in side areas of the standing side surfaces of the first dimple, wherein the standing side surfaces are transformed into reversed inclined side surfaces inclined to a reversed direction to the first inclined side surfaces, and a front side of the die pad is semiconductor element mounting surface.

Abstract: A low-k chip packaging structure comprising chip body I (2-1), a chip electrode (2-2), and a chip surface passivation layer (2-3). Chip body I (2-1) has coated thereon thin film layer I (2-3). Thin film layer I (2-3) has arranged on a rear face thereof a support wafer (2-5). A chip electrode (2-2) is transferred to thin film layer I (2-4) around the exterior of the chip via a rewired metal wiring (2-6). The rewired metal wiring (2-6) has arranged at an end thereof a metal column (2-7). The metal column (2-7) has coated thereon thin film layer II (2-8). The top of the metal column protrudes thin film layer II (2-8). The protruding top of the metal column (2-7) has arranged thereon a metal layer (2-9). The metal layer (2-9) has arranged thereon soldering balls (2-10). The low-k chip packaging structure solves the problem of invalid low-k chip due to concentration of stress during chip packaging process and allows for reduced packaging costs and great product reliability.

Abstract: A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.

Abstract: A semiconductor module has a metallic base plate; an insulated circuit board fixed on the metallic base plate; a semiconductor element mounted on the insulated circuit board; a resin case to house the semiconductor element, and having an upper surface with an opening; a terminal exposed from the opening of the resin case to an outer portion in a vertical direction; and an insulating holding piece having a triangular or a rectangular cross-section and one surface contacting the terminal. The terminal has a projecting portion disposed inside the resin case to restrict a movement of the terminal in the vertical direction. The resin case has a first recess portion to fit the projecting portion and a second recess portion disposed on the upper surface of the resin case so that the holding piece pushes the projecting portion on the terminal toward the first recess portion for insertion.

Abstract: In one embodiment, the present invention includes a lead frame for accommodating a semiconductor die. The lead frame includes a die attach pad, a first plurality of conductive finger ends, and a second plurality of conductive finger ends. The first plurality of conductive finger ends are arranged within a first elongated region. This first elongated region is located along the first edge of the die attach pad. The second plurality of conductive finger ends is arranged within a second elongated region. The second elongated region has an end adjacent to an end of the first elongated region. The second elongated region is positioned at an angle that is greater than ninety degrees from the first elongated region.

Abstract: A method for mounting and embedding a thinned integrated circuit within a substrate is provided. In one embodiment, the thinned integrated circuit can receive one or more biasing substrate layers on a first surface of the thinned integrated circuit. When the thinned integrated circuit is embedded within a supporting substrate, such as a printed circuit board, the biasing substrate layers can position the thinned integrated circuit toward a centerline of the printed circuit board. Positioning the thinned integrated circuit toward the centerline can increase the resistance to breakage.

Abstract: A wiring board includes a wiring forming region in which a plurality of wiring layers are stacked while sandwiching insulating layers, an outer periphery region which is arranged around the wiring forming region and in which a reinforcing pattern is formed in the same layer as each of the wiring layers. An area ratio of the reinforcing pattern to the outer periphery region and an area ratio of the wiring layer to the wiring forming region are substantially the same in each of the layers, and the reinforcing patterns exist without a gap in the outer periphery region when the wiring board is viewed in planar perspective.

Abstract: A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.

Abstract: A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion.

Abstract: A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding.

Abstract: A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.

Abstract: A lead frame strip includes an array of sites arranged in at least one row connected to two exterior side rails which traverse the lead frame strip on two opposite sides. Each of the sites is further connected to the two exterior side rails by subrails which extend between the two exterior side rails. Interior side rails extend between the subrails having a length dimension oriented along a first direction. The interior side rails include at least one punch degating aperture having an aperture length oriented along the first direction, wherein a total of the aperture length along the interior side rails is greater than or equal to the die pad length.

Abstract: A light-emitting device having at least one spacer located at a bottom surface is disclosed. In two other embodiments, an electronic display system and an electronic system having such light-emitting device are disclosed. The light-emitting device comprises a plurality of leads, a light source die, and a body. The body encapsulates a portion of the plurality of leads and the light source die. The body has a least one side surface and a bottom surface. The at least one spacer is located at the bottom surface. In use, the light-emitting device is attached to a top surface of a substrate. The spacer is configured to create an air vent between the bottom surface and the top surface of the substrate when the light-emitting device is attached to, and the spacer is in contact with the substrate.

Abstract: A semiconductor unit includes a base, an insulating substrate bonded to the base, a conductive plate made of a metal of poor solderability, a semiconductor device mounted to the insulating substrate through the conductive plate, and a metal plate interposed between the conductive plate and the semiconductor device and made of a metal of good solderability as compared to the metal used for the conductive plate. The base, the insulating substrate, the conductive plate and the metal plate are brazed together, and the semiconductor device is soldered to the metal plate.

Abstract: It is possible to realize the following package structure. That is, a structure for applying a stress to a channel region is provided for a semiconductor chip itself. In a package manufacturing process, a low thermal expansion coefficient film is formed on a circuit face of an Si chip. Thus, distribution and magnitude of a desired stress can be secured for a channel region of a MOSFET in a mounted chip even after performance of the package manufacturing process. As a result, a mobility is increased and current driving power is enhanced.