Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method comprises forming a MEMS layer, wherein the forming comprises fusion bonding a handle layer with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.

Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming an isolation structure surrounding the fin structure. The method also includes cleaning sidewalls of the fin structure. The method also includes depositing a silicon cap layer over the fin structure. The method also includes growing an oxide layer over the silicon cap layer. The silicon cap layer is thinned after growing an oxide layer over the silicon cap layer. The method also includes forming a gate structure over the oxide layer across the fin structure. The method also includes growing a source/drain epitaxial structure beside the gate structure. The method also includes forming a contact structure electrically connected to the gate structure.

Abstract: Provided are a thin film transistor including: a base cushion layer having a recessed portion, base insulating layer, source-drain layer and active layer. The base insulating layer is located on a side of the base cushion layer where the recessed portion is located, and has a first and second partition walls that are spaced apart, and an orthographic projection region of a gap region between the first and second partition walls onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first and second partition walls onto the base cushion layer partially overlap with the recessed portion region; and both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer.

Abstract: A shift register circuit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit. The input sub-circuit is connected to an input signal terminal, a first power source terminal and a pull-down node, and configured to, under the control of an input signal, output a first power source terminal signal to the pull-down node. In the shift register circuit, the discharge sub-circuit may control the potential of the pull-down node to be an ineffective potential at the input stage, thereby preventing the noise reduction sub-circuit from affecting the potentials of the pull-up node and the output terminal under the control of the pull-down node, and ensuring normal output of the shift register circuit.

Abstract: A semiconductor apparatus has a silicon carbide substrate heavily doped with the first conductivity type and a lightly doped silicon carbide drift region of the first conductivity type over the silicon carbide substrate. A first body region in the drift region is doped with second conductivity type opposite the first. A first source region in the first body region is heavily doped with the first conductivity type. A gate trench is formed in the first source region and first body region. At least one sidewall of the gate trench is parallel to a crystal plane of the silicon carbide structure having greater carrier mobility than a C-face thereof. The gate trench extends a length of the first body region and the source region to a separation region laterally adjacent to the first region wherein the separation region is in the drift region.

Abstract: Glass articles and methods for modifying a composition of a surface portion of the glass article are disclosed. The method includes heating the surface portion of the glass article with a laser beam to a temperature within a range of about 1100?C to about 2200?C such that the heating evaporates one or more metalloids and/or one or more alkali metals present at the surface portion, and modifies the composition of the surface portion such that the surface portion has a lower alkali metals concentration and/or a lower metalloids concentration as compared to a portion of the glass article that is not heated by the laser beam.

Abstract: A semiconductor device includes an insulating substrate, a polysilicon layer formed on the insulating substrate, a first-gate-insulating layer formed on the polysilicon layer, a first metal layer formed on the first-gate-insulating layer, an oxide-semiconductor layer formed on the first-gate-insulating layer, a second-gate-insulating layer formed on the oxide-semiconductor layer, a second metal layer formed on the second-gate-insulating layer, a first insulating interlayer formed on the second metal layer, a third metal layer formed on the first insulating interlayer, a first top gate planar type thin film transistor in which the polysilicon layer serves as a channel and which has a source, a drain and a gate, and a second top gate planar self-aligned type thin film transistor in which the oxide-semiconductor layer serves as a channel and which has a source, a drain and a gate, wherein the gate of the first top gate planar type thin film transistor is made of a first metal layer, the gate of the second top ga

Abstract: Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

Abstract: A composite power element and a method for manufacturing the same are provided. The power element includes a substrate structure, an insulation layer, a dielectric layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The zener diode is formed in a circuit element formation region of the substrate structure, and includes a zener diode doped structure formed on the insulation layer and covered by the dielectric layer. The zener diode doped structure includes a P-type doped region and an N-type doped region. The zener diode includes a zener diode metal structure formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region. The zener diode is configured to receive a reverse bias voltage when the power element is energized.

Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers that are alternately stacked with each other, a first channel layer passing through the stack structure and including a metal oxide-based semiconductor, and a second channel layer adjacent to the first channel layer and including the metal oxide-based semiconductor, wherein the first channel layer has a higher oxygen content than the second channel layer and has a different thickness from the second channel layer.

Abstract: A thin film transistor includes an active layer on a substrate, a gate electrode configured to be spaced from the active layer and partially overlapped with the active layer, and a gate insulating layer, at least a part of the gate insulating layer being disposed between the active layer and the gate electrode, wherein the gate insulating layer includes a first gate insulating layer between the active layer and the gate electrode, and a second gate insulating layer configured to have a dielectric constant (k) which is different from a dielectric constant of the first gate insulating layer, and disposed in a same layer as the first gate insulating layer, and wherein at least a part of the second gate insulating layer is disposed between the active layer and the gate electrode.

Abstract: In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.

Abstract: An OLED display according to an exemplary embodiment includes: a substrate; a gate insulation layer that is disposed on the substrate; and a gate wire that is disposed on the gate insulation layer, and includes a gate electrode, wherein the gate wire includes a single layer of aluminum or an aluminum alloy, and an angle formed by side surfaces of the gate wire and the gate insulation layer is less than 65°.

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Abstract: A display device includes: a substrate; a buffer layer on the substrate; a first active pattern and a second active pattern on the buffer layer and spaced apart from each other; a first gate insulation layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulation layer, the first gate electrode and the second gate electrode respectively overlapping the first active pattern and the second active pattern; a second gate insulation layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulation layer, the capacitor electrode overlapping the first gate electrode, wherein a permittivity of the first gate insulation layer is greater than a permittivity of the buffer layer.

Abstract: A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.

Abstract: An apparatus includes a substrate, a nested enclosure assembly including an outer enclosure and an inner enclosure, wherein the outer enclosure encloses the inner enclosure and the inner enclosure encloses at least the electronic assembly. An insulating medium is disposed within a cavity between the outer surface of the inner enclosure and the inner surface of the outer enclosure and the system includes a sensor assembly communicatively coupled to the electronic assembly. The sensor assembly includes one or more sensors that are configured to acquire one or more measurement parameters at one or more locations of the substrate. The electronic assembly is configured to receive the one or more measurement parameters from the one or more sensors.

Abstract: A stretchable display according to one embodiment of the present invention comprises: a hybrid stretchable substrate divided into a low stretchable region and a high stretchable region having a modulus lower than that of the low stretchable region; a driving element layer including a driving element on the low stretchable region so as to control a light emitting layer, and wiring on the high stretchable region so as to be electrically connected to a part of the driving element to apply an electrical signal; and the light emitting layer provided on the driving element layer, and electrically connected to the driving element layer to emit light, wherein, between the driving element and the wiring, the wiring can overlap a stretchable mask pattern having a shape corresponding to either the low stretchable region or high stretchable region.

Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

Abstract: The present disclosure is in the field of display technologies, and provides an array substrate including an IGZO film layer, a gate layer, and a gate insulating layer. The gate layer is provided with broken lines at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line. The gate insulating layer is disposed between the IGZO film layer and the gate layer, and is provided with at least two through holes thereon, in which the first gate line is connected with the IGZO film layer through one of the through holes, and the second gate line is connected with the IGZO film layer through another through hole, thus, connecting the IGZO film layer in series into the gate layer.

Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

Abstract: Optoelectronic devices that include a composite film in a multilayered encapsulation stack are provided. Also provided are methods of forming the light reflection-modifying structures, as well as other polymeric device layers, using inkjet printing. The composite films include a first, lower refractive index domain and a second, higher refractive index domain.

Abstract: Embodiments herein describe a photonic platform where an AR coating is disposed between an optical grating and a semiconductor substrate. In one embodiment, the optical grating is disposed within an insulative layer. A first side of the insulative layer provides an optical interface where an external optical source can transmit an optical signal into, or a receive an optical signal from, the grating. A second, opposite side of the insulative layer contacts the AR coating. When the external optical source transmits light through the first side of the insulative layer, some of the light passes through the grating and reaches the AR coating. The AR coating prevents this light from being reflected back to the grating by the semiconductor layer which can cause interference that varies the coupling efficiency of the grating.

Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.

Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor layer; a source electrode, a drain electrode and a gate electrode located between the source electrode and the drain electrode disposed on a side of the semiconductor layer; at least two dielectrics located between the gate electrode and the drain electrode, wherein a dielectric coefficient of a dielectric adjacent to the gate electrode is greater than that of a dielectric away from the gate electrode and adjacent to the drain electrode.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.

Abstract: The present disclosure provides a shift register, a driving method thereof, a scan driving circuit and a display device. The shift register includes: a first node control module configured to control level at the first node based on an input signal and a second clock signal; a second node control module configured to control level at a second node based on the input signal, the first clock signal, the second clock signal, a low level signal and a high level signal; and an output control module configured to control the output terminal to output high level or low level based on level at the first node, level at the second node and the second clock signal. The second node can be provided with a relatively low level, which is conductive to maintaining a normal output of the shift register.

Abstract: A display device includes a display panel including a flexible region and a low flexibility region, wherein the flexible region may include a first transistor including a first semiconductor layer and a first gate electrode, a first conductor connected to the first semiconductor layer, and a first interlayer insulating layer between the first transistor and the first conductor. The low flexibility region may include a second transistor including a second semiconductor layer and a second gate electrode, a second conductor connected to the second semiconductor layer, and a second interlayer insulating layer between the second transistor and the second conductor. The first interlayer insulating layer may include an organic insulating material, the second interlayer insulating layer includes an inorganic insulating material, and a ratio of channel width to channel length of the first transistor may be different from that of the second transistor.

Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate, and a display panel. The array substrate includes a flexible substrate; an active layer disposed on the flexible substrate; a first gate insulating layer disposed on the active layer; a first gate layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the first gate insulating layer and the first gate layer; and a second gate layer disposed on the second gate insulating layer. The array substrate of the present disclosure replaces molybdenum wires of a gate layer and a second gate layer with a multi-layered composite metal layer. The bending tolerance of gate wires in the display panel is enhanced and increase of impedance of the first gate layer is prevented.

Abstract: The present disclosure provides a thin film transistor and a manufacturing method thereof, a display substrate and a manufacturing method thereof, and a display device. The thin film transistor of the embodiments of the present disclosure comprises an active layer pattern disposed on a base substrate, a gate electrode insulating pattern disposed on the active layer pattern, and a gate electrode disposed on the gate electrode insulating pattern, wherein a conductive pattern is disposed between the gate electrode and the gate electrode insulating pattern, the conductive pattern being electrically connected to the gate electrode, and an orthographic projection of the conductive pattern on the base substrate being overlapped with an orthographic projection of the gate electrode insulating pattern on the base substrate.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: A display apparatus includes a display panel, a display panel driver and a first connection wire. The display panel includes a substrate and a display layer disposed on a first surface of the substrate. The display panel driver applies a driving signal to the display panel. The display panel driver is disposed on a second surface opposite to the first surface of the substrate. The first connection wire is disposed at a first side surface connecting the first and second surfaces of the substrate. The first connection wire connects electrically the display panel with the display panel driver.

Abstract: One embodiment of the invention is characterized as follows. A display device comprising: a display area including a plurality of pixels, each of the pixels has a first TFT and a second TFT, the first TFT and the second TFT comprise an oxide semiconductor, the first TFT and the second TFT are covered by an interlayer insulating film, a first through hole is formed in the in the interlayer insulating film to connect a drain of the first TFT, wherein a distance d1 between a center of the first through hole and an edge of a channel of the first TFT is shorter than a distance d2 between a center of the first through hole and an edge of a channel of the second TFT, a channel length of the first TFT is shorter than a channel length of the second TFT.

Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

Abstract: A semiconductor device includes a substrate having a cell region and an extension region, channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, gate electrode layers surrounding the channel structures and stacked to be spaced apart from each other in the first direction and to extend in a second direction substantially perpendicular to the first direction, and word line cuts cutting the gate electrode layers in the first direction and continuously extending in the second direction. At least one of the word line cuts is an extension word line cut with an extension portion having an area that is different from those of the remaining word line cuts located at the same level as the at least one word line cut in a predetermined region extending in the second direction.

Abstract: A novel semiconductor device with high convenience or high reliability is provided. The semiconductor device includes an arithmetic logic unit and an amplifier. The arithmetic logic unit is configured to generate second data on the basis of an offset adjustment signal or offset data and first data. The amplifier includes an operational amplifier and an offset adjustment circuit including a register. The operational amplifier supplies a predetermined voltage to a node on the basis of a voltage between a first terminal and a second terminal. The register is configured to retain, as the offset data, the offset adjustment signal on the basis of a latch signal. The register is configured to allow the supplied offset adjustment signal to pass therethrough in a passage state and supply the offset adjustment signal. The register is configured to supply the offset data in a non-passage state.

Abstract: An array substrate including a plurality of terminals, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer include an insulating layer therebetween, wherein a plurality of first electrode plates and a plurality of second electrode plates are formed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates are opposite to each other to constitute a capacitor structure, the terminals are provided in the same layer as the first conductive layer or the second conductive layer, or the terminals are provided in the same layer as a third conductive layer between the first conductive layer and the second conductive layer. A method of manufacturing an array substrate and a display device is provided.

Abstract: A semiconductor memory device comprises: a substrate; gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer including a first portion extending in the first direction and facing the plurality of gate electrodes, and, a second portion nearer to the substrate than the first portion; a gate insulating film provided between the gate electrode and the first portion of the first semiconductor layer, and, including a memory portion; and, a wiring portion provided between the substrate and the plurality of gate electrodes, connected to the second portion of the first semiconductor layer, and, extending in a second direction crossing the first direction. The wiring portion comprises a second semiconductor layer connected to the second portion of the first semiconductor layer. The second semiconductor layer includes a first crystal grain larger than a thickness in the first direction of the second semiconductor layer.

Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.