Abstract: A semiconductor device includes a lead frame including inner lead portion having inner leads connected to outer leads and relay inner leads not connected to the outer leads. A semiconductor element is mounted on a lower surface of the lead frame. Electrode pads of the semiconductor element are connected to the inner lead portion via metal wire. One end of the relay inner lead is connected to the electrode pad via the metal wire, and the other end is connected to the outer lead via a relay metal wire disposed to step over the inner lead.

Abstract: A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed.

Abstract: Methods for die-to-die wire-bonding, and devices and systems formed thereby, are described herein. A die to die wire-bonding method may comprise bonding a first conductive bump having a first bump size to a first die pad; bonding a first wire to a second die pad, the first wire bonded to the second die pad by a second conductive bump having a second bump size, the second bump size being smaller than the first bump size; and bonding the first wire to the first conductive bump.

Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.

Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.

Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. The method further includes attaching a lead frame to the lateral contacts of the stacked first and second dies.

Abstract: A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements.

Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

Abstract: A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation layer is also provided overlying the major surface of the substrate. The passivation layer overlies the contact pad such that it exposes at least a portion of the contact surface. A plurality of metal layers arranged in a stack overlie the contact surface and at least a portion of the passivation layer. The stack includes multiple layers, which can have different thicknesses and different metals, with the lowest layer including titanium (Ti) and nickel (Ni) in contact with the contact surface.

Abstract: An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad; forming an exposed terminal interconnect on the connection pad; and encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation.

Abstract: An integrated circuit package system includes: forming a die-attach paddle, an outer interconnect, and an inner interconnect toward the die-attach paddle beyond the outer interconnect; mounting an integrated circuit device over the die-attach paddle; connecting the integrated circuit device to the inner interconnect and the outer interconnect; encapsulating the integrated circuit device over the die-attach paddle; attaching an external interconnect under the outer interconnect; and attaching a circuit device under the die-attach paddle and extended laterally beyond opposite sides of the die-attach paddle.

Abstract: There is provided a wiring substrate. The wiring substrate includes: a semiconductor substrate having a through hole; an insulating film provided to cover an upper surface, a lower surface and a first surface of the semiconductor substrate, the first surface corresponding to a side surface of the through hole; a through electrode provided in the through hole; a first wiring pattern disposed on an upper surface side of the semiconductor substrate and coupled to the through electrode; and a second wiring pattern disposed on a lower surface side of the semiconductor substrate and coupled to the through electrode. A first air gap is provided between the first wiring pattern and the insulating film formed on the upper surface, and a second air gap is provided between the second wiring pattern and the insulating film formed on the lower surface.

Abstract: An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support.

Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.

Abstract: Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices, and optionally, a substrate. The conductive pathways may include self-supporting conductive leads or conductive traces carried by a substrate. Methods for forming semiconductor device assemblies having more than one semiconductor device include bending or wrapping at least one conductive pathway around a side of at least one semiconductor device and providing electrical communication between semiconductor devices of the assembly through the conductive pathways.

Abstract: A semiconductor device and method. One embodiment provides an integral array of first carriers and an integral array of second carries connected to the integral array of first carriers. First semiconductor chips are arranged on the integral array of first carriers. The integral array of second carriers is arranged over the first semiconductor chips.

Abstract: According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.

Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages.

Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.

Abstract: The invention provides a warpage-proof circuit board structure, including: an inner layer circuit board; at least one dielectric layer formed on at least one surface of the inner layer circuit board; at least one first groove formed in the at least one dielectric layer corresponding in position thereto; a solder mask formed on the surface of the dielectric layer, a second groove formed in the solder mask and corresponding in position to the first groove formed in the dielectric layer; and a metal frame formed in the first and second grooves and protruding from the surface of the solder mask, thereby strengthening the circuit board to prevent it from warping in thermal processing and further using the metal frame as a heat-dissipating means for the package structure.

Abstract: A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.

Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.

Abstract: The present invention provides an integrated circuit package system comprising: attaching a die platform to an integrated circuit die; mounting the integrated circuit die over an external interconnect with a bottom side of the external interconnect partially within the die platform; connecting the integrated circuit die and the external interconnect; and forming an encapsulation over the integrated circuit die with the external interconnect partially exposed.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

Abstract: A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.

Abstract: Two vertical-type power MISFETs are formed over a semiconductor chip, a common drain electrode formed over a back surface of the semiconductor chip is electrically connected with a drain terminal via a conductive bonding material, source electrodes and gate electrodes formed over a surface of the semiconductor chip are respectively electrically connected with source terminals and gate terminals via bump electrodes, and these components are sealed by a resin sealing portion. The exposed portions of the gate terminals are arranged inside the resin sealing portion, and the exposed portions of the source terminals are arranged outside the resin sealing portion. The source terminals extend over the surface of the semiconductor chip and are connected with the source electrodes which are uniformly arranged over regions of the surface of the semiconductor chip except for gate electrode forming regions and the vicinities of these regions via the bump electrodes.

Abstract: A lead frame includes a lead frame main body having a plurality of die pad portions each having a chip mounting surface on which a semiconductor chip is mounted, a plurality of lead portions provided to surround the plurality of die pad portions respectively, and a frame portion for supporting the plurality of die pad portions and the plurality of lead portions, an adhesive film pasted on a lower surface of the lead frame main body by pressing, and a first metal film provided on surfaces of the plurality of lead portions and connected electrically to the semiconductor chip respectively, wherein second metal films whose thickness is substantially equal to a thickness of the first metal film are provided to the chip mounting surface of the plurality of die pad portions respectively.

Abstract: While a semiconductor device is provided with a plurality of element electrodes 5 formed on a semiconductor element 4 and a plurality of lead terminal electrodes 6 formed on a lead frame, the semiconductor device is equipped with a coupling conductor which electrically connects at least one electrode among the above-described element electrodes 5 to at least one electrode among the above-described lead terminal electrodes 6; the above-described coupling conductor is manufactured by a first conductor 1 and a second conductor 2, the major components of which are metals; the first conductor 1 has been electrically connected to the second conductor 2; and the element electrodes 5 and the lead terminal electrodes 6 have been electrically connected to the second conductor 2 respectively.

Abstract: The present invention provides a possibility of mounting conventionally capped components, that saves much space. The component assembly includes at least one component having a cap, a substrate for the component and connecting means for mounting the component on the substrate and for the electrical connection of the component. The substrate has at least one recess. The component is mounted on the substrate in flip-chip technique, so that the cap is inserted into the recess and the component is connected to the substrate via connecting bumps in the edge region of the recess.

Abstract: A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough.

Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.

Abstract: A redistributed lead frame for use in a molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attach sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: A composite interconnect system includes a plurality of carbon nanotubes, a plurality of solder balls and standoff balls disposed on a first device to provide a connection to a second device. A die-attached substrate includes a substrate and one or more die disposed on the substrate by a die-attach composite interconnect. The die-attach composite interconnect includes a plurality of carbon nanotubes, solder bumps, and standoff balls disposed on the die to provide one or more connections to the substrate. A PCB-attached substrate package includes a substrate package and one or more die disposed on the substrate package. The substrate package is disposed on a PCB by a PCB-attach composite interconnect. The PCB-attach composite interconnect includes a plurality of carbon nanotubes, solder balls, and standoff balls disposed on the substrate package to provide one or more connections to the PCB.

Abstract: A quad flat non-lead (QFN) semiconductor package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area of the die attach pad; at least one row of inner terminal leads disposed adjacent to the die attach pad; first wires bonding respective said inner terminal leads to the semiconductor die; at least one row of extended, outer terminal leads disposed along periphery of the QFN semiconductor package; at least one row of intermediary terminals disposed between the inner terminal leads and the extended, outer terminal leads; second wires bonding respective the intermediary terminals to the semiconductor die; and third wires bonding respective the intermediary terminals to the extended, outer terminal leads.

Abstract: A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.

Abstract: A thin, small outline IC leadframe plastic package to be used to assemble high performance, high speed semiconductor memory IC devices such as dynamic random access memories (DRAM) having a high data transfer rate in the range of 1 GigaHertz. The package leadframe is electrically interconnected to the IC device input-output pads by either electrically conductive (e.g. solder) bumps that are flip-chip bonded to the IC device or by of an interposer. The interposer contains integral curled micro-spring contacts at opposite ends of conductive fan out traces. The interposer is attached to the leadframe bonding pads by way of tape automated bonding, soldering, or adhesive bonding. The leadframe that is interconnected to the IC device by the aforementioned flip-chip bumps or the interposer is encapsulated and trimmed to form either gull-wing style perimeter leads as a standard thin small outline package (TSOP) or wrap around leads as a micro-leadframe (MLF) package.

Abstract: A method for packaging an integrated circuit. A barrier metal pattern is disposed on a baseplate. A conductive layer is disposed on the barrier metal pattern. A photoresist having a pattern is applied to the conductive layer. A via is then disposed on the conductive layer. An integrated circuit is coupled to the via and encapsulated. Then, at least a part of the baseplate is removed. An integrated circuit package is produced by the method.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A semiconductor package includes a semiconductor device having a first main surface and a second main surface, a first electrode plate provided on the first main surface, a second electrode plate provided on the second main surface, and a wiring substrate provided between the semiconductor device and the first electrode plate, in which a plurality of opening portions in the side surface of a protruding portion provided on the first electrode plate are engaged respectively with a plurality of engaging portions which face the opening portions and which are provided on the inner side surface of an intrusion opening portion in the wiring substrate into which the protruding portion is intruded.

Abstract: Provided is a printed circuit board having a structure that can prevent the generation of cracks around a rectangular hole and a method of manufacturing a printed circuit board for a semiconductor package. The printed circuit board includes a base substrate in which at least one window slit is formed, a plurality of circuit patterns formed at least on a side surface of the base substrate, a protective layer formed on the base substrate and the circuit patterns, and a crack preventive layer that is formed along at least a portion of edges of the window slit and is not formed at least on the circuit patterns.

Abstract: A semiconductor device includes a semiconductor substrate having an internal circuit; an electrode pad electrically connected to the internal circuit; an insulating film having a through hole exposing the electrode pad; and a re-distribution wiring pattern formed on the insulating film and electrically connected to the electrode pad. The semiconductor device further includes a recess groove formed in the insulating film around and adjacent to the re-distribution wiring pattern.

Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Abstract: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads.

Abstract: A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.

Abstract: A semiconductor device in accordance with the present invention includes IC chips (semiconductor elements) (2, 3, 4) having solder bumps (24) (projecting electrodes) formed on electrode pads, and a first wiring board (1) having connection terminals (7) to which the respective solder bumps (24) of the IC chips (2, 3, 4) are connected, external connection terminals (8) for connection to an external apparatus, and conductor wires (9) provided in respective groove portions formed in a board surface and connected to the respective connection terminals (7). In spite of the reduced pitch of the conductor wires (9), the presence of the groove portions enables an increase in cross section, allowing a reduction in wiring resistance.

Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.