With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) Patents (Class 257/676)
  • Patent number: 9807517
    Abstract: The MEMS microphone includes a first circuit board; a second circuit board keeping a distance from the first circuit board; a frame located between the first circuit board and the second circuit board for forming a cavity cooperatively with the first circuit board and the second circuit board, the frame including a plated-through-hole; an ASIC chip located in the cavity; and an MEMS chip having a back cavity. The first circuit board is electrically connected with the second circuit board by the plated-through-hole. The frame includes a conductive layer and an insulating layer, and the conductive layer is located between an inner surface of the frame and the insulating layer.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: October 31, 2017
    Assignee: AAC TECHNOLOGIES PTE. LTD.
    Inventors: Hu Chen, Kai Wang
  • Patent number: 9799613
    Abstract: A lead frame device includes a metallic outer frame member, a lead frame package preform, and an encapsulant. The metallic outer frame member includes a pair of spaced apart longitudinal and transverse sections. The lead frame package preform includes at least one die pad surrounded by the metallic outer frame member such that a gap is formed around the die pad within the metallic, and a plurality of spaced apart leads. Each of the spaced apart leads has a first portion connected to the metallic outer frame member, a second portion proximal to and spaced apart from the die pad, a top surface, and a recess indented from the top surface. The encapsulant is filled in the recess. The disclosure also provides a lead frame device assembly.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: October 24, 2017
    Assignee: CHANG WAH TECHNOLOGY CO., LTD.
    Inventor: Chia-Neng Huang
  • Patent number: 9786585
    Abstract: One example discloses a lead-frame, comprising: a die-pad having a die coupling surface; a set of terminals each having an outer terminal edge and an inner terminal edge; wherein the outer terminal edge faces away from the die-pad and the inner terminal edge faces toward the die-pad; and a terminal connector having a first side coupled to the inner terminal edge and a second side coupled to the die-pad.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 10, 2017
    Assignee: NXP B.V.
    Inventor: Pieter Offeringa
  • Patent number: 9786519
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9780017
    Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 3, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Juan Alejandro Herbsommer, Yong Lin, Rongwei Zhang, Abram Castro, Matthew David Romig
  • Patent number: 9780060
    Abstract: A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 3, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yong Lin, Vikas Gupta, Rongwei Zhang
  • Patent number: 9780019
    Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: October 3, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chun-Li Liu, Ali Salih, Balaji Padmanabhan, Mingjiao Liu
  • Patent number: 9768146
    Abstract: The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 19, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Zhiqiang Niu, Yan Xun Xue, Man Sheng Hu, Jun Lu, Yueh-Se Ho, Hamza Yilmaz
  • Patent number: 9768087
    Abstract: There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Chuan Cheah
  • Patent number: 9768091
    Abstract: In one embodiment, an electronic package structure includes multiple rows of I/O pads and is formed without a flag portion. An electronic device may be attached to a pair of adjacent inner rows of I/O pads. The pair of adjacent inner rows of I/O pads is configured to support, at least in part, the electronic device, and to receive connective structures, such as wire bonds. Connective structures may electrically connect the electronic device to the multiple rows of I/O pads, and an encapsulating layer covers portions of the I/O pads, the electronic device and the connective structures.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: September 19, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Azhar Aripin
  • Patent number: 9768101
    Abstract: The present invention relates to the technical field of integrated circuit package, and more specifically, this invention relates to a high density integrated circuit package structure and an integrated circuit with this package structure. A high density integrated circuit package structure according to this invention comprises a sealed metal lead frame, a chip, and a cuboid plastic package structure with micron connecting wires. The length (A1) of the plastic package structure meets the relationship 1.20 mm+(B?8)×0.3 mm/2?A1?4.50 mm+(B?8)×1.00 mm/2, the width (A2) of the plastic package structure meets the relationship 1.20 mm?A2?3.50 mm, the thickness (A3) of the plastic package structure meets the relationship A3?0.35 mm, and B is the number of the outer leads and is an integer number meeting the relationship 4?B?68. A package structure according to this invention may meet the demands generated when chip manufacturing technology progresses from micron scale to sub-micron scale, or even nanometer scale.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 19, 2017
    Assignee: China Chippacking Technology Co. Ltd.
    Inventor: Dazhong Liang
  • Patent number: 9768360
    Abstract: An optoelectronic component includes at least one inorganic optoelectronically active semiconductor component having an active region that emits or receives light during operation, and a sealing material directly applied by atomic layer deposition, wherein the semiconductor component is applied on a carrier, the carrier includes electrical connection layers, the semiconductor component electrically connects to one of the electrical connection layers via an electrical contact element, and the sealing material completely covers in a hermetically impermeable manner and directly contacts all exposed surfaces including sidewall and bottom surfaces of the semiconductor component and the electrical contact element and all exposed surfaces of the carrier apart from an electrical connection region of the carrier.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 19, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Michael Fehrer, Alfred Lell, Martin Müller, Tilman Schlenker, Sönke Tautz, Uwe Strauβ
  • Patent number: 9761512
    Abstract: A leadframe assembly is formed from an electrically conductive material. The leadframe assembly includes a first longitudinal element, at least one second longitudinal element, a plurality of first leadframe sections and a plurality of second leadframe sections.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: September 12, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Stephan Preuss, Michael Zitzlsperger
  • Patent number: 9754924
    Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: September 5, 2017
    Assignee: Apple Inc.
    Inventor: Chih-Ming Chung
  • Patent number: 9754825
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Patent number: 9748205
    Abstract: A molding type power module includes: a leadframe including a first step and a second step; a first planar power device including a first surface having electrodes and a second surface opposite to the first surface, the electrodes being correspondingly bond to the first step respectively; and a second planar power device including a first surface having electrodes and a second surface opposite to the first surface, the electrodes being correspondingly bond to the second step respectively, wherein, the first surface of the first planar power device and the first surface of the second planar power device face each other, the projected areas thereof on a vertical direction at least partially overlap, and the first planar power device at least has one electrode electronically connected with the electrodes of the second planar power device.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 29, 2017
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kai Lu, Zhenqing Zhao, Tao Wang, Le Liang
  • Patent number: 9741587
    Abstract: Provided are a semiconductor device manufacturing method and semiconductor device such that manufacturing can be simplified and the thickness of the semiconductor device can be reduced. The semiconductor device includes an insulated circuit substrate having on one main surface thereof a first metal layer and a second metal layer, a metal plate conductively connected to the first metal layer, a first semiconductor element including on front and rear surfaces thereof a plurality of metal electrodes, a first insulating member disposed on a side surface of the first semiconductor element, a second insulating member disposed on the first insulating member and on the first semiconductor element, and a third metal layer, in which at least one portion thereof is disposed on the second insulating member and which conductively connects the metal electrode of the first semiconductor element and the second metal layer on the insulated circuit substrate.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 22, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsunehiro Nakajima, Yoshikazu Takahashi, Norihiro Nashida
  • Patent number: 9741641
    Abstract: A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.
    Type: Grant
    Filed: January 16, 2016
    Date of Patent: August 22, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
  • Patent number: 9735078
    Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: August 15, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Haeberlen, Matteo-Alessandro Kutschak
  • Patent number: 9716072
    Abstract: A power semiconductor element is fixed on a die pad of the lead frame. A metal plate is bonded to a lower surface of the die pad via an insulating film. The inner lead etc. are disposed in a cavity between a lower mold and an upper mold and are encapsulated with an encapsulation resin. The lower mold has a stepped portion provided in a bottom surface of the cavity below the inner lead. A height of an upper surface of the stepped portion is larger than a height of an upper surface of the power semiconductor element disposed in the cavity. When an encapsulation resin is injected into the cavity, a lower surface of the metal plate is in contact with the bottom surface of the cavity, and the encapsulation resin flows downward from above the stepped portion toward the upper surface of the power semiconductor element.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: July 25, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Kawashima, Ken Sakamoto, Taketoshi Shikano
  • Patent number: 9711435
    Abstract: A semiconductor device is provided. The semiconductor device may include a frame portion on which at least one semiconductor chip is arranged; a plurality of leads electrically connected to the semiconductor chip; and a mold portion formed on the frame portion to surround a part of the frame portion on which the semiconductor chip and the plurality of leads are arranged, wherein a gap between closest portions of the respective leads is at least 2.9 mm.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: July 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn-seung Lee, Jin-hyung Lee, Gil-yong Chang
  • Patent number: 9711689
    Abstract: A purpose of the present invention is to provide an optical unit that is capable of effectively sealing one or a plurality of optical devices even without a special material, a special structure, etc. In an optical unit of the present invention, the sealing section (50) includes: a circular seal section (51) surrounding one or a plurality of optical devices (40) on a wiring substrate from an in-plane direction of the wiring substrate; and an inside filling section (52) with which inside of the seal section (51) is filled and that seals the one or plurality of optical devices (40). The optical devices (40) are each a light emitting unit, a light receiving device, an image sensor, an X-ray sensor, or a power generating device. The seal section (51) and the inside filling section (52) are each configured of a cured thermosetting resin. The inside filling section (52) has light transmittance that is higher than light transmittance of the seal section (51).
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: July 18, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Akiyoshi Aoyagi, Gyongsok Song
  • Patent number: 9704831
    Abstract: A transistor chip formed from a wide band gap semiconductor, on which transistor elements for an upper arm are formed is mounted on a front surface of an insulating substrate. A transistor chip formed from a wide band gap semiconductor, on which transistor elements for a lower arm are formed is mounted on a rear surface of the insulating substrate.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: July 11, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akira Hatai, Shizuri Tamura
  • Patent number: 9704979
    Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: July 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
  • Patent number: 9685424
    Abstract: A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: June 20, 2017
    Assignees: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 9685430
    Abstract: A method of manufacturing an embedded package comprises attaching a plurality of chips on a pre-mold lead frame; forming a first lamination layer on the plurality of chips, the pre-mold lead frame and a plurality of pins; forming a first plurality of vias and a second plurality of vias through the first lamination layer; forming a respective conductive plug of a plurality of conductive plugs by depositing a respective conductive material in each of the first plurality of vias and each of the second plurality of vias; and electrically connecting the plurality of conductive plugs on the electrodes of the plurality of chips to the plurality of conductive plugs on the plurality of pins.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 20, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Zhiqiang Niu, Hua Pan, Ming-Chen Lu, Yueh-Se Ho, Jun Lu
  • Patent number: 9685351
    Abstract: A method and apparatus are described for fabricating a microchip structure (70) which protects interior electrical integrated circuits and components (120) attached to a lead frame die flag (104) using a molding compound (124) that mechanically interlocks with one or more positive mold lock structures formed as dummy wire loops (114) or stud bumps (214) that are attached to the lead frame (100) and/or die flag (104).
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: June 20, 2017
    Assignee: NXP USA, INC.
    Inventor: Leo M. Higgins, III
  • Patent number: 9679833
    Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 13, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ming-Chen Lu, Hongtao Gao
  • Patent number: 9673109
    Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: June 6, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9666512
    Abstract: A semiconductor package with a leadframe to mount a transistor device prevents malfunction. The semiconductor package includes a leadframe including at least one or more transistor die attach pads where a first transistor device and a second transistor device are arranged, a driver die attach pad where a driver semiconductor chip is arranged, a first driver lead electrically connected to the driver semiconductor chip, and a second driver lead arranged between the first driver lead and the at least one or more transistor die attach pads, a chip bonding wire electrically connecting the first transistor device with the driver semiconductor chip, a first transistor bonding wire electrically connecting the first driver lead with the second transistor device, and a first insulator arranged on the second driver lead to insulate the second driver lead and the first transistor bonding wire from each other.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: May 30, 2017
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Seung-won Im, O-seob Jeon, Joon-seo Son
  • Patent number: 9668351
    Abstract: A manufacturing method of a package carrier is provided. A carrier having a connecting surface is provided. A releasable solder resist layer is formed on the connecting surface of the carrier and completely covers the connecting surface. A substrate having an upper surface and a lower surface opposite to each other is provided. A first patterned solder resist layer is formed on the lower surfaces of the substrate and exposes a portion of the lower surface. The carrier and the substrate are laminated, the releasable solder resist layer directly contacts the first patterned solder resist layer, and the carrier is temporarily bonded to the first patterned solder resist layer through the releasable solder resist layer.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: May 30, 2017
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Chao-Min Wang
  • Patent number: 9659846
    Abstract: A process for manufacturing at least one 3D electronic module each comprises a stack of electronic packages and/or printed wiring boards, wherein a stack is placed on an electrically interconnecting system comprising metal leads each having two ends.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: May 23, 2017
    Assignee: 3D PLUS
    Inventors: Alexandre Val, Fabrice Soufflet
  • Patent number: 9653419
    Abstract: A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventor: Yikang Deng
  • Patent number: 9653405
    Abstract: In various embodiments, a chip arrangement may be provided. The chip arrangement may include a metallic carrier. The chip arrangement may also include at least one chip arranged on the metallic carrier, wherein the at least one chip includes a chip contact, wherein the chip contact is electrically coupled to the metallic carrier. The chip arrangement may also include encapsulation material at least partially encapsulating the at least one chip. The chip arrangement may also include an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: May 16, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Horst Theuss, Beng Keh See
  • Patent number: 9640468
    Abstract: A surface-mount electronic device includes a body of semiconductor material, and a lead frame that includes a plurality of contact terminals. The plurality of contact terminals is electrically connected to the semiconductor body. The contact terminals are formed of sintered material.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Fulvio Vittorio Fontana
  • Patent number: 9640471
    Abstract: Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal conductivity and a large separation between external connections for use in high voltage power conversion circuits. Some electronic packages employ “L” shaped power paths and internal low impedance die to die connections. Further embodiments employ an insulative substrate disposed within the electronic package for efficient power path routing and increased packaging density.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: May 2, 2017
    Assignee: NAVITAS SEMICONDUCTOR INC.
    Inventor: Daniel M. Kinzer
  • Patent number: 9634212
    Abstract: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: April 25, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Masahiko Kobayakawa, Kazuhiro Mireba, Shintaro Yasuda, Junichi Itai, Taisuke Okada
  • Patent number: 9627297
    Abstract: Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 18, 2017
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde Milton Carpenter, Jr.
  • Patent number: 9627296
    Abstract: A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: April 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jeffrey Gail Holloway
  • Patent number: 9627435
    Abstract: A light emitting device includes a substrate and a plurality of light emitting cells disposed on the substrate. Each light emitting cell includes a first semiconductor layer and a second semiconductor layer, an active layer between the first and the second semiconductors, a conductive material on the second semiconductor layer, an inclined surface, a first insulation layer overlaps each light emitting cell, an electrically conductive material overlaps the first insulation layer to couple two of the plurality of light emitting cells, and a second insulation layer overlaps the electrically conductive material. A light-transmitting material is used in both the first insulation layer and the second insulation layer. The inclined surface is continuous and has a slope of approximately 20° to approximately 80° from a horizontal plane based on the substrate.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 18, 2017
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Lam Lee, Jae Ho Lee, Yeo Jin Yoon, Eu Jin Hwang, Dae Won Kim
  • Patent number: 9613918
    Abstract: High power multi-chip module packages for packaging semiconductor dice are disclosed. The disclosed packages have an output power of at least 1 kilowatt (kW) and can have an operating signal frequency in a range of hundreds of MHz. The high power multi-chip module packages have base plates with multiple planes or layers that can be conductive and may be thin metal layers in some examples. The multiple planes are formed and overlaid in such a way that they help reduce stray inductance values caused by the packaging itself, which improves overall device operation and efficiency. Current loops created when one of the multi-chip modules is in a turn-on condition are balanced and opposed and generate a minimized B-Field that is restricted by the manner in which the multiples planes of the base plate are overlaid, thus reducing the stray inductance values and improving device operation.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: April 4, 2017
    Assignee: MICROSEMI CORPORATION
    Inventors: George J. Krausse, III, Wang-Chang Albert Gu
  • Patent number: 9613251
    Abstract: A method of matching a reference fingerprint image and an input fingerprint image, represented by a first set of minutiae and a second set of minutiae, including: determining a first local neighborhood for each minutia including at least one minutia neighboring the minutia, comparing the first local neighborhoods in the first set with the first local neighborhoods in the second set to determine matched minutiae, filtering the matched minutiae based on a difference between their positions, determining a second local neighborhood for each unmatched minutia including at least one matched minutia neighboring the unmatched minutia, comparing the second local neighborhoods in the first set with the second local neighborhoods in the second set to determine further matched minutiae, filtering the matched minutiae and the further matched minutiae based on a difference between their positions, and determining whether the first and second fingerprint images are the same.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: April 4, 2017
    Assignee: Zwipe AS
    Inventors: Milan Neskovic, Marko Nikolic
  • Patent number: 9606308
    Abstract: Techniques are provided for flip-chip assembly and packaging of microelectronic, photonics and optoelectronic devices in which three-dimensional alignment of package components is achieved using solder surface tension during a solder reflow process to move one or more package components and align such components in X, Y and Z directions using mechanical stops and chip butting techniques.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Yves C. Martin, Jae-Woong Nah
  • Patent number: 9609711
    Abstract: A light-emitting diode (LED) tube lamp comprises a lamp tube, a first rectifying circuit, a filtering circuit and an LED driving module. The lamp tube has a first pin and a second pin for receiving an external driving signal. The first rectifying circuit is coupled to the first and second pins, for rectifying the external driving signal to produce a rectified signal. The filtering circuit is coupled to the first rectifying circuit, for filtering the rectified signal to produce a filtered signal. The LED driving module is coupled to the filtering circuit to receive the filtered signal for emitting light. Wherein, the filtering circuit includes a capacitor and an inductor connected in parallel and between one of the first and second pins and the first rectifying circuit, and the parallel-connected capacitor and inductor are configured for presenting a peak equivalent impedance to the external driving signal at a specific frequency.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 28, 2017
    Assignee: Jiaxing Super Lighting Electric Appliance Co., Ltd.
    Inventors: Tao Jiang, Chang Yang, Aiming Xiong, Qifeng Ye, Xintong Liu
  • Patent number: 9601369
    Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed on the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be electrically interconnected through the TSVs.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: March 21, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Reza A. Pagaila
  • Patent number: 9589873
    Abstract: A leadless chip carrier comprises a thermal pad for attaching to a printed circuit board (PCB) and an integrated circuit electrically connected to a plurality of electrical lead frame pads for connection to a plurality of corresponding pads on the PCB. The leadless chip carrier further comprises a non-collapsible conductive shim bonded to a first surface of the thermal pad and each of the plurality of electrical lead frame pads is attached to a volume of solder. The conductive shim provides a stand-off between the thermal pad and the PCB and improves the integrity of a joint between the thermal pad and the PCB.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: March 7, 2017
    Assignee: MICROSS COMPONENTS LIMITED
    Inventor: Peter Julian Tollafield
  • Patent number: 9589875
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: March 7, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
  • Patent number: 9583407
    Abstract: A first conductor layer is provided on a first surface of an insulating plate, and has a first volume. A second conductor layer is provided on a second surface of the insulating plate, and has a second volume. A third conductor layer is provided on a second surface of the insulating plate, and has a second volume. The third conductor layer has a mounting region thicker than the second conductor layer. The sum of the second and third volumes is greater than or equal to 70% and smaller than or equal to 130% of the first volume. A semiconductor chip is provided on the mounting region. A sealing part is formed of an insulator, and seals the semiconductor chip within a case.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 28, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Yoshida, Yoshitaka Otsubo, Hidetoshi Ishibashi, Kenta Nakahara
  • Patent number: 9570379
    Abstract: In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched conductive carrier segment. The power semiconductor package also includes a power electrode heat spreader situated over the second power electrode and configured for attachment to a power electrode conductive carrier segment.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Patent number: 9564406
    Abstract: The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: February 7, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Zhiqiang Niu, Yan Xun Xue, Man Sheng Hu, Jun Lu, Yueh-Se Ho, Hamza Yilmaz