With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) Patents (Class 257/676)
  • Patent number: 9564393
    Abstract: A semiconductor device package includes a substrate and a semiconductor device disposed on a surface of the substrate. The semiconductor device includes a first contact pad and a second contact pad disposed on an upper surface of the semiconductor device. The semiconductor device package further includes a conductive bar disposed on the first contact pad, and a conductive pillar disposed on the second contact pad. A method of making a semiconductor device package includes (a) providing a substrate; (b) mounting a semiconductor device on the substrate, wherein the semiconductor device comprises a first contact pad and a second contact pad on an upper surface of the semiconductor device; (c) forming a dielectric layer on the substrate to cover the semiconductor device; (d) exposing the second contact pad by forming a hole in the dielectric layer; and (e) applying a conductive material over the dielectric layer and filling the hole.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Yi Huang, Kuo-Hua Chen, Chi-Tsung Chiu
  • Patent number: 9564387
    Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: February 7, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Antonio Bambalan Dimaano, Jr., Rui Huang
  • Patent number: 9552999
    Abstract: In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.
    Type: Grant
    Filed: December 12, 2015
    Date of Patent: January 24, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: Tae Ki Kim, Byong Jin Kim, Ji Young Chung, Gi Jeong Kim, Won Bae Bang
  • Patent number: 9543235
    Abstract: In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: January 10, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: Hyung Il Jeon, Ji Young Chung, Byong Jin Kim, In Bae Park, Jae Min Bae, No Sun Park
  • Patent number: 9543479
    Abstract: A semiconductor chip without a substrate is provided on an electrically insulating carrier. The carrier has electrically conductive contact metallizations. Furthermore, an electrically conductive carrier substrate and a covering substrate are provided. The covering substrate has electrically conductive contact structures. The carrier is attached to the carrier substrate. Subsequently, the covering substrate is attached to the semiconductor chip and/or to the carrier. The electrically conductive contact structures are connected in an electrically conductive manner to the electrically conductive contact metallizations and the electrically conductive carrier substrate.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: January 10, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Siegfried Herrmann
  • Patent number: 9545012
    Abstract: A method for manufacturing a printed circuit board of a backlight module is provided. The printed circuit board includes a light bar region and a heat dissipating region. The light bar region used for mounting a light bar of the backlight module and formed with a conductive circuit for supplying power for the light bar. The heat dissipating region is connected with the light bar region. A connection location of the light bar region and the heat dissipating region is subjected to cutting to form a slot located at a side of the printed circuit board in order to prevent short-circuiting between the heat dissipating region and the conductive circuit of the light bar region. The cutting is made to partly penetrate through the thickness of a dielectric layer on which the conductive circuit is formed in order to completely separate the light bar region from the heat dissipating region.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: January 10, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Che-chang Hu, Kuang-Yao Chang, Qian Cao
  • Patent number: 9543270
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a conductive contact. The two device regions are formed from the substrate, and the substrate has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface and electrically connected to the two device regions, and the external chip is disposed on the first redistribution layer. The first connectors are interposed between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip, and the conductive contact is extended from the second surface to the first surface of the substrate to electrically connect the device region.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: January 10, 2017
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Patent number: 9530754
    Abstract: A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: December 27, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Khalil Hosseini, Joachim Mahler, Franz-Peter Kalz, Joachim Voelter, Ralf Wombacher
  • Patent number: 9530721
    Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nishikizawa, Tadatoshi Danno, Hiroyuki Nakamura, Osamu Soma, Akira Uemura
  • Patent number: 9530749
    Abstract: An apparatus relates generally to a microelectromechanical system component. In such an apparatus, the microelectromechanical system component has a lower surface, an upper surface, first side surfaces, and second side surfaces. Surface area of the first side surfaces is greater than surface area of the second side surfaces. The microelectromechanical system component has a plurality of wire bond wires attached to and extending away from a first side surface of the first side surfaces. The wire bond wires are self-supporting and cantilevered with respect to the first side surface of the first side surfaces.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: December 27, 2016
    Assignee: Invensas Corporation
    Inventors: Reynaldo Co, Willmar Subido, Hoang Nguyen, Marjorie Cara, Wael Zohni, Christopher W. Lattin
  • Patent number: 9530722
    Abstract: The present invention relates to a power module obtained by connecting the opposite sides of a chip with solder, and prevents the side surfaces of a base portion from becoming wet with solder, which would otherwise cause connection failures of the solder or chip displacement, and also prevents peeling of molding resin, which would otherwise break the chip or shorten the life of the solder. The base portion is integrally formed with one of lead frames, and the side surfaces of the base portion and the surface of the main body of the lead frame are roughened so as to have reduced solder wettability. Meanwhile, the solder connection surface of the base portion is not roughened so as to ensure the solder wettability. Accordingly, it is possible to reduce failures that may occur during solder connection and obtain a highly reliable power module (FIG. 5).
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 27, 2016
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shiro Yamashita, Hideto Yoshinari, Takashi Kume, Shinichi Fujino, Eiichi Ide
  • Patent number: 9524926
    Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: December 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Juan Alejandro Herbsommer, Yong Lin, Rongwei Zhang, Abram Castro, Matthew David Romig
  • Patent number: 9520341
    Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: December 13, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Chuan Cheah
  • Patent number: 9519097
    Abstract: The lighting device contains a substrate and a plurality of lighting elements arranged in at least two parallel rows on a front side of the substrate. The lighting elements of the two rows neighbor on each other. The front side of the substrate is configured so that an included angle is formed between the lighting elements of the two rows. Their light therefore converges within a Quantum Dots (QD) tube before entering a light guide plate. A backlight module incorporating the lighting device as such not only provides high saturation and high chromaticity, but also achieves greater optical coupling efficiency, thinner light guide plate and QD tube, reduced material cost and dimension.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: December 13, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Shihhsiang Chen, Chengwen Que, Dehua Li
  • Patent number: 9512990
    Abstract: A light emitting device mounting structural body includes a wiring substrate having wirings disposed on a base member and a light emitting device having a resin molded body mounted on the wiring substrate. The wiring substrate has a recess in its periphery. The resin molded body has a lower surface and a side surface. The lower surface has an arrangement portion and a projecting portion, the arrangement portion has an outer lead electrically connected to the wiring portion disposed beneath the arrangement portion, and the projecting portion is projected further downward relative to the arrangement portion. The side surface has an opening with a light emitting element mounted thereon, the opening is expanded in the projecting portion, and at least a portion of the opening is housed in the recess of the wiring substrate.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: December 6, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Ryosuke Wakaki
  • Patent number: 9508690
    Abstract: An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Richard S. Graf, David J. West
  • Patent number: 9508633
    Abstract: A field-effect transistor package includes a leadframe with a first linear thickness (150a) and a leadframe pad (151) of a reduced thickness; a first terminal of a field-effect transistor chip (140) attached to the pad and a second and a third terminal remote from the pad; a metal sheet (110) of a second linear thickness (110a) connecting the second transistor terminal to a package terminal; a metal sheet (112) of a third linear thickness (112a) connecting the third transistor terminal to a package terminal; the sum of the first linear thickness (about 0.125 mm) and the second linear thickness (about 0.125 mm) plus attach material (about 0.05 mm) comprising the package thickness (about 0.3 mm).
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Juan A. Herbsommer, Osvaldo J. Lopez, Jonathan A. Noquil
  • Patent number: 9508703
    Abstract: Semiconductor dies are bonded to each other and electrically connected to each other. An encapsulant is utilized to protect the semiconductor dies and external connections are formed to connect the semiconductor dies within the encapsulant. In an embodiment the external connections may comprise conductive pillars, conductive reflowable material, or combinations of such.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh, Meng-Tse Chen, Hui-Min Huang, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9491539
    Abstract: A Microelectromechanical system (MEMS) assembly includes a substrate, lid, MEMS device, and at least one wall. The substrate has electrical connection pads and the electrical connection pads are coupled to electrical conductors extending through the substrate. The MEMS device is attached to the lid. The at least one wall is coupled to the lid and the substrate and is formed separately from the lid and has an electrical conduit disposed therein. The electrical conduit is electrically coupled to the electrical conductors on the substrate. The electrical conduit and electrical conductors form an electrical path between the MEMS device and the electrical connection pads.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 8, 2016
    Assignee: Knowles Electronics, LLC
    Inventors: Sandra F. Vos, John B. Szczech
  • Patent number: 9491856
    Abstract: A light system including a printed circuit board including a base layer, a first protection layer which is in contact with at least one surface of the base layer, an insulating layer disposed on the base layer, and a conduction layer disposed on the insulating layer, and a light emitting device package mounted on the conduction layer. Further, the base layer includes iron (Fe).
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: November 8, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sangwoo Lee, Jiun Kong, Il Seo, Hongboem Jin, Dongwook Park
  • Patent number: 9484293
    Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 1, 2016
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjörn Ebefors, Daniel Perttu
  • Patent number: 9475691
    Abstract: A semiconductor package includes an electrically conductive lead-frame, including a first die paddle having a first opening, and a plurality of electrically conductive leads, a ridge formed around a perimeter of the first opening, and an electrically insulating molding compound. The electrically insulating molding compound includes an interior cavity being defined by a planar base surface and outer sidewalls, a second opening formed in the base surface, and an interior sidewall within the interior cavity. The molding compound is formed around the lead-frame with the first die paddle in the interior cavity. The first and second openings are aligned with one another so as to form a port that provides access to the interior cavity. The ridge and the interior sidewall form a dam that is configured to collect liquefied sealant and prevent the liquefied sealant from overflowing into the port or into adjacent regions of the interior cavity.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 25, 2016
    Assignee: Infineon Technologies AG
    Inventors: Kok Yau Chua, Sook Woon Chan, Chau Fatt Chiang, Stefan Martens, Matthias Steiert, Kian Hong Yeo, Hock Siang Chua, Mei Chin Ng, Swee Kah Lee
  • Patent number: 9472492
    Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: October 18, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Kazutaka Shibata
  • Patent number: 9472515
    Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: October 18, 2016
    Assignee: INTEL CORPORATION
    Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
  • Patent number: 9455216
    Abstract: A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched recesses (134) in leads. In one embodiment, the structure is a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package (140) that includes a semiconductor device encapsulated in a package body (142) having a plurality of leads (120). Each lead has an exposed portion external to the package. There is recess (134) at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material (300).
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: September 27, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Dwight L. Daniels, Stephen R. Hooper, Alan J. Magnus, Justin E. Poarch
  • Patent number: 9455244
    Abstract: A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a first chip region and first chip pads formed on a top surface of the first chip region. A second semiconductor chip is mounted on the package substrate. The second semiconductor chip includes a second chip region and second chip pads formed on a top surface of the second chip region. A boundary region having a groove divides the first chip region and the second chip region. The first chip region, the second chip region and the boundary region share a semiconductor substrate of a one-body type.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 27, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: MuSeob Shin
  • Patent number: 9449912
    Abstract: An integrated circuit (IC) module for an IC card includes a plurality of IC card contacts in side-by-side relation. A dielectric support layer is above the contact layer and has a plurality of openings and a first coefficient of thermal expansion (CTE). An IC die is above the dielectric support layer and includes a plurality of bond pads. A bond wire extends from a respective bond pad to a corresponding contact through an adjacent opening in the dielectric support layer. A respective body of fill material is within each opening and has a second CTE. A mold compound body is above the dielectric support layer, the bodies of fill material, and surrounding the IC die. The mold compound body has a third CTE. The first CTE is closer to the second CTE than to the third CTE.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 20, 2016
    Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS (MALTA) LTD
    Inventors: Xueren Zhang, Kim-Yong Goh, Roseanne Duca
  • Patent number: 9448216
    Abstract: A gas sensor device may include a gas sensor integrated circuit (IC) having a gas sensing surface, and bond pads adjacent to the gas sensing surface, and a frame having gas passageways extending therethrough adjacent the gas sensing surface. The gas sensor device may include leads, each having a proximal end spaced from the frame and bonded to a respective bond pad, and a distal end extending downwardly from the proximal end, and encapsulation material filling the space between the proximal ends of the leads and the frame.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: September 20, 2016
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yonggang Jin, Ravi Shankar
  • Patent number: 9437580
    Abstract: A semiconductor package includes a flexible package substrate including a first surface and a second surface, a metal post penetrating the flexible package substrate from the first surface toward the second surface and including a first protrusion that protrudes from the first surface and a second protrusion that protrudes from the second surface, a first semiconductor chip connected to the first protrusion, a second semiconductor chip connected to the second protrusion, a first flexible molding member covering the first semiconductor chip and the first surface of the flexible package substrate, a second flexible molding member covering the second semiconductor chip disposed on the second surface of the flexible package substrate, and an external connection terminal disposed on the second surface of the flexible package substrate.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 6, 2016
    Assignee: SK HYNIX INC.
    Inventors: Ga Hyun No, Chan Woo Jeong
  • Patent number: 9437538
    Abstract: A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.
    Type: Grant
    Filed: June 1, 2014
    Date of Patent: September 6, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 9437528
    Abstract: A dual-side exposed semiconductor package with ultra-thin die and a manufacturing method are disclosed. A die having a source electrode and a gate electrode at top surface is flipped and attached to a die paddle of a lead frame and then is encapsulated with a first molding compound. The first molding compound and the die are ground to reduce the thickness. A mask is applied atop the lead frame with the back of the flipped die exposed and a metal layer is deposited on the exposed area at the back of the flipped die. A metal clip is attached to the back of the flipped die. A second molding compound is deposited on the lead frame with the top surface of the metal clip exposed from the top surface of the second molding compound and the bottom surface of the lead frame exposed from the bottom surface of the second plastic molding compound.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 6, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Yuping Gong, Xiaoming Sui, Yan Yun Xue, Jun Lu
  • Patent number: 9437459
    Abstract: An electronic component package that includes a package substrate having an aluminum bond pad formed from an aluminum clad copper structure. The aluminum clad copper structure is attached to a dielectric layer. An electronic component is attached to the substrate and includes a conductive structure electrically coupled to the aluminum bond pad. The aluminum bond pad, the electronic component, and at least a portion of the substrate are encapsulated with an encapsulant.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: September 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Burton J. Carpenter, Chu-Chung Lee, Tu-Anh N. Tran
  • Patent number: 9437530
    Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 6, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yueh-Se Ho, Hamza Yilmaz, Yan Yun Xue, Jun Lu
  • Patent number: 9437527
    Abstract: A resin casing is insert-molded while clamp protrusions of clamp portions formed in bonding portions of lead terminals are put between an upper mold and a lower mold. An insulating substrate which has a wiring pattern mounted with semiconductor elements is fitted into an opening portion of the resin casing and adhesively bonded to the resin casing. Electric connection between the semiconductor elements and the bonding portions of the lead terminals and between the wiring pattern on the insulating substrate and the bonding portions of the lead terminals is made by bonding wires. Thus, it is possible to provide a method for manufacturing a semiconductor device and the semiconductor device, in which stress applied to lead terminals of a lead frame formed by insert molding can be suppressed, and wire bonding properties and reliability can be improved even when the thickness of each of the lead terminals is reduced.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: September 6, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Yokoyama
  • Patent number: 9431578
    Abstract: In one example embodiment, a semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. The second conductivity-type semiconductor layer and the active layer having at least one contact hole exposing a region of the first conductivity-type semiconductor layer. The semiconductor light emitting device further includes at least one columnar structure disposed in the exposed region of the first conductivity-type semiconductor layer within the at least one contact hole. The semiconductor light emitting device further includes a first electrode disposed on the exposed region of the first conductivity-type semiconductor layer in which the at least one columnar structure is disposed, the first electrode being connected to the first conductivity-type semiconductor layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myong Soo Cho, Tae Hun Kim, Young Ho Ryu, Young Chul Shin, Dong Myung Shin
  • Patent number: 9431328
    Abstract: A power semiconductor package and a method of preparation are disclosed. The power semiconductor package includes a pair of first and second die paddles arranged side by side, a first semiconductor chip attached to the first die paddle, a second semiconductor chip attached to the second die paddle, a metal clip electrically connecting a first electrode at the top surface of the first semiconductor chip and a first electrode at the top surface of the second semiconductor chip to a second pin, a first conductive structure connecting a second electrode at the top surface of a first semiconductor chip to a first pin, and a second conductive structure connecting a second electrode at the top surface of the second semiconductor chip to a third pin. In examples of the present disclosure, double-chip common source technique for the source electrodes of two power MOSFETs is achieved by applying a T-shape metal clip.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: August 30, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu
  • Patent number: 9425372
    Abstract: The LED device (27) has a LED bare chip (25) mounted directly on a metal contact (28), and supplies power to the bare chip and conducts heat from the bare chip via the metal contact.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: August 23, 2016
    Assignee: Japan Aviation Electronics Industry, Limited
    Inventor: Hideyuki Kanno
  • Patent number: 9407599
    Abstract: For a network controller for managing managed forwarding elements running in hosts in a network, a method for configuring a host to facilitate migration of a virtual machine (VM) from a first host to a second host is described. The method configure, in the first host, a first managed forwarding element to perform (1) a logical L3 routing processing and (2) a network address translation (NAT) processing for a VM running in the first host. The method configures the first host to automatically send NAT information to the second host when the VM migrates to the second host so that a second managed forwarding element running in the second host can perform a NAT processing for the migrated VM based on the NAT information.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: August 2, 2016
    Assignee: NICIRA, INC.
    Inventors: Teemu Koponen, Pankaj Thakkar, Ronghua Zhang
  • Patent number: 9402311
    Abstract: A semiconductor module includes a copper connector jointing an electrode formed on a top surface of a bare-chip transistor and a wiring pattern out of plural wiring patterns via a solder. The copper connector includes an electrode jointing portion jointed to the electrode of the bare-chip transistor and a substrate jointing portion arranged to face the electrode-jointing portion and jointed to the wiring pattern. The width W1 of the electrode jointing portion in a direction perpendicular to one direction is smaller than the width W2 of the substrate jointing portion in the direction perpendicular to the one direction.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: July 26, 2016
    Assignee: NSK Ltd.
    Inventors: Takashi Sunaga, Noboru Kaneko, Osamu Miyoshi
  • Patent number: 9401336
    Abstract: A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: July 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Sarah H. Knickerbocker, Karen P. McLaughlin, David J. Russell
  • Patent number: 9397028
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: July 19, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger M. Arbuthnot, Stephen St. Germain
  • Patent number: 9391005
    Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 12, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • Patent number: 9385057
    Abstract: A semiconductor flat package has a semiconductor chip, leads connected to the semiconductor chip, and an encapsulation resin covering the semiconductor chip and partially covering the leads. Outer end surfaces of the leads are exposed from the encapsulation resin and covered with a plated layer, and a side end surface of the plated layer and a side end surface of the encapsulation resin are flush with each other. A material with good solder wettability is formed at a lead cut portion of the semiconductor flat package, to thereby improve solder connection strength with a circuit board. A solder fillet is formed from the lead cut portion of the semiconductor package, to thereby enable adaptation of solder automatic visual inspection after mounting.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: July 5, 2016
    Assignee: SII Semiconductor Corporation
    Inventor: Tomoyuki Yoshino
  • Patent number: 9373746
    Abstract: A semiconductor light emitting device includes a substrate, a semiconductor laminate disposed on the substrate and divided to a plurality of light emitting cells with an isolation region, and a wiring unit electrically connecting the plurality of light emitting cells. A region of lateral surfaces of each of the light emitting cells in which the wiring unit is disposed has a slope gentler than slopes of other regions of the lateral surfaces of each of the light emitting cells.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: June 21, 2016
    Inventors: Hae Youn Hwang, Pun Jae Choi, Jung Jae Lee
  • Patent number: 9362240
    Abstract: An electronic device includes multiple semiconductor chips in a single housing. Such semiconductor chips may comprise different semiconductor materials, for example they may comprise GaN. Using bonding clips instead of bonding wires is an efficient way of connecting such semiconductor chips to a substrate.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Khalil Hosseini, Joachim Mahler, Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Patent number: 9362210
    Abstract: Metal leadframes, semiconductor packages made using the leadframes, and methods of making the leadframes and packages are disclosed. In one embodiment, the leadframe includes a rectangular frame. A chip pad and a plurality of leads are within the frame. The lower side of the chip pad and the leads includes one or more vertically recessed horizontal surfaces. The upper side of the chip pad may include a groove around a chip mounting region. In a package, the chip pad supports a semiconductor chip electrically connected to the leads. The lower side of the chip pad and leads are exposed at an exterior surface of the package body. Encapsulant material underfills the recessed lower surfaces of the chip pad and leads, thereby locking them to the encapsulant material. A wire may be reliably bonded to the chip pad within the groove formed in the upper side thereof.
    Type: Grant
    Filed: February 10, 2013
    Date of Patent: June 7, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Byung Hoon Ahn, Jae Hun Ku, Young Suk Chung, Suk Gu Ko, Sung Sik Jang, Young Nam Choi, Won Chul Do
  • Patent number: 9362142
    Abstract: A method for making a set of electronic devices is proposed.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 7, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Agatino Minotti, Maurizio Maria Ferrara
  • Patent number: 9355990
    Abstract: The present invention provides a manufacturing method of a device embedded substrate, including: forming a bonding layer of an insulation material on a metal layer formed on a support plate; and mounting an electric or electronic device on the bonding layer, wherein the device is formed of a device main body and a protruding terminal; the bonding layer includes a first bonding body bonded with the metal layer and a second bonding body bonded with the device; the first bonding body is formed along the outer edge of the device; the second bonding body is formed in an area equal or smaller than the area defined by the outer edge of the terminal; and, in the bonding layer forming step, the second bonding body is formed on the first bonding body after the first bonding body is cured.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 31, 2016
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Tohru Matsumoto, Masaru Ogasawara, Mitsuaki Toda
  • Patent number: 9357634
    Abstract: An improved discrete electronic device and method of making the improved discrete electronic device is described. The discrete electronic device has an electronic passive component with a termination and a lead frame. A compensating compliant component is between the termination and the lead frame. The compensating compliant component has a composite core and a first conductor on the composite core. The first conductor is in electrical contact with the termination. A second conductor is also on the composite core wherein the second conductor is in electrical contact with the lead frame.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: May 31, 2016
    Assignee: Kemet Electronics Corporation
    Inventors: John E. McConnell, Alan P. Webster, John Bultitude, Abhijit Gurav
  • Patent number: 9349628
    Abstract: Methods and apparatus for coupling a stiffener frame to a circuit board are disclosed. In one aspect, a method for engaging a stiffener frame and a circuit board positioned in a fixture is provided. The method includes positioning an alignment plate on the stiffener frame, such that a downwardly facing shoulder of a bottom opening of the alignment plate is seated on a setback of the stiffener frame, wherein the bottom opening of the alignment plate is larger than the a top opening of the alignment plate. The circuit board is positioned on the stiffener frame. The alignment plate restrains movement of the circuit board relative to the stiffener frame with a peripheral wall of a the top opening of the alignment plate.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: May 24, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei-Chin Lau, Hai-Wah Lim