Abstract: The present invention relates to an adhesive film for a semiconductor that can more easily bury unevenness such as through wires of a semiconductor substrate or a wire attached to a semiconductor chip and the like, and yet can be applied to various cutting methods without specific limitations to realize excellent cuttability, thus improving reliability and efficiency of a semiconductor packaging process.

Abstract: The present disclosure relates to a MEMS package having different trench depths, and a method of fabricating the MEMS package. In some embodiments, a cap substrate is bonded to a device substrate. The cap substrate comprises a first trench, a second trench, and an edge trench recessed from at a front-side surface of the cap substrate. A stopper is disposed within the first trench and raised from a bottom surface of the first trench. The stopper has a top surface lower than the front-side surface of the cap substrate.

Abstract: In an electro-optical device, a mirror that is formed on an element substrate is sealed by a frame shaped spacer and a plate-like light-transmitting cover which is adhered to the spacer. An inorganic barrier layer is formed on an outer face of the spacer and a side face of the light-transmitting cover, and the boundary of the spacer and the light-transmitting cover is covered by the inorganic barrier layer.

Abstract: LTCC structure extends between top and bottom surfaces, with at least one cavity being formed within the structure and extending from the top surface inwardly in the direction of the bottom surface. A die is disposed within the cavity a top surface of the die is positioned flush with the top surface of the package, resulted in the shortest length of the wire box connecting the die with the LTCC structure and ultimately reducing the inductance.

Abstract: Provided is a method of evaluating the impurity gettering capability of an epitaxial silicon wafer, which allows for very precise evaluation of the impurity gettering behavior of a modified layer formed immediately under an epitaxial layer, the modified layer containing carbon in solid solution. In this method, a modified layer located immediately under an epitaxial layer, the modified layer containing carbon in solid solution, is analyzed by three-dimensional atom probe microscopy, and the impurity gettering capability of the modified layer is evaluated based on a three-dimensional map of carbon in the modified layer, obtained by the analysis.

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

Abstract: Technology leading to a size reduction in a power conversion apparatus comprising a cooling function and technology relating to enhancing productivity and enhancing reliability necessary for commercial production are provided. Series circuits comprising an upper arm and lower arm of an inverter circuit are built in a single semiconductor module 500. The semiconductor module has cooling metal on two sides. An upper arm semiconductor chip and lower arm semiconductor chip are wedged between the cooling metals. The semiconductor module is inserted inside a channel case main unit 214. A DC positive electrode terminal 532, a DC negative electrode terminal 572, and an alternating current terminal 582 of a semiconductor chip are disposed in the semiconductor module. The DC terminals 532 and 572 are electrically connected with a terminal of a capacitor module. The alternating current terminal 582 is electrically connected with a motor generator via an AC connector.

Abstract: A probe card device includes an upper die unit, a lower die unit, a spacer sandwiched between the upper and lower die units, an impedance adjusting member, and conductive probes. The upper die unit includes a first die and a second die spaced apart from the first die. The first die has a penetrating hole, and the second die has a circuit layer. The impedance adjusting member is disposed on the second die and is electrically coupled to the circuit layer. Each of the conductive probes passes through the upper die unit, the spacer, and the lower die unit. At least one of the conductive probes includes an upper contacting segment protruding from the upper die unit and an extending arm connected to the upper contacting segment. The extending arm is abutted against the circuit layer by passing through the penetrating hole.

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

Abstract: A method for manufacturing an electronic device comprises providing a substrate, applying a first bonding material on the substrate, bonding a plurality of light emitting units to the substrate through the first bonding material, identifying a defective light emitting unit from the plurality of light emitting units, removing the defective light emitting unit from a corresponding position on the substrate, applying a second bonding material, and bonding a repairing light emitting unit to the corresponding position through the second bonding material.

Abstract: A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality of contact pads. A lower surface of the contact pads and a lower surface of the first die pad are arranged in a first plane. An upper surface of the second die pad is arranged in a second plane distant from the first plane by an overall thickness of the semiconductor package.

Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

Abstract: A storage device may include a controller performing non data word line (NDWL) maintenance in sub block mode (SBM). The NDWL maintenance in SBM can include proactive select gate drain (SGD) detection and phased SGD correction. For example, when a block reaches a PE cycle threshold value, SGD phased correction occurs upon detection of an error, by determining whether a sister sub block of the selected block contains data. If the sister sub block contains data, the data is transferred from the sister sub block, and then the block and sister sub block undergo correction for NDLW maintenance.

Abstract: A substrate structure includes a substrate body, at least one first mold area and at least one second mold area. The substrate body has a first surface and a second surface opposite to the first surface, and defines at least one first through hole extending through the substrate body. The first mold area is disposed on the first surface of the substrate body. The second mold area is disposed on the second surface of the substrate body, wherein the first mold area is in communication with the second mold area through the first through hole.

Abstract: A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.

Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

Abstract: A semiconductor package includes a semiconductor chip including a body, a connection pad, a passivation film, a first connection bump disposed, and a first coating layer; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer, a redistribution layer, and a connection via. The first connection bump includes a low melting point metal, the redistribution layer and the connection via include a conductive material, and the low melting point metal has a melting point lower than a melting point of the conductive material.

Abstract: The invention describes a light converting device comprising: a light converter for converting laser light to converted light having a longer peak emission wavelength than the laser light, a heatsink comprising a reflective structure, and a clamping structure mechanically coupling the light converter to the heatsink, the clamping structure for pressing the light converter on a surface of the heatsink such that thermal conductance between the light converter and the heatsink is increased and at least a part of the converted light is reflected by means of the reflective structure when illuminated by means of the laser light, without any adhesive or connection layer between the light converter and the heatsink. The invention further describes a laser-based light source comprising such a light converting device, and a vehicle headlight comprising such a laser-based light source.

Abstract: A multi-chip module includes a plurality of chip parts with each chip part having an electrode, a sealing resin for sealing the plurality of chip parts, and an external connection terminal secured to the sealing resin so as to be exposed from the outer surface of the sealing resin and electrically connected to the electrode of at least one of the chip parts.

Abstract: A curved display apparatus includes a display panel curved along a first direction, and an FPC board used for driving the display panel. The FPC board is connected to a side of a curved side of the display panel. The FPC board is provided with the slits for reducing the stress applied to the FPC board.

Abstract: A protection circuit module includes an insulating substrate, a first surge withstand chip resistor mounted on a pair of first pads formed on one surface of the insulating substrate, a second surge withstand chip resistor mounted on a pair of second pads formed on the other surface of the insulating substrate, and arranged at a position on the other surface of the insulating substrate overlapping the first surge withstand chip resistor in a plan view, a first wiring coupled to one first pad, a second wiring coupled to one second pad, a third wiring coupling the other first pad and the other second pad to the same potential, and a shield wiring provided on an inner layer of the insulating substrate and arranged in a region in which at least the one first pad and the one second pad oppose each other.

Abstract: A method of manufacturing a System in Package (SiP) module includes: welding required electronic units by the SiP module onto a top surface of a Printed Circuit Board (PCB), with welding spots being reserved on a bottom surface of the PCB for obtaining a PCB assembly (PCBA) of the SiP module; pasting tightly a functional film on a surface of the electronic units of the PCBA; filling on plastic materials on the top surface of the PCBA, ensuring that the plastic materials covers the electronic units and the functional film on the top surface of the PCBA, and obtaining solidified PCBA after the plastic materials are solidified; and cutting the solidified PCBA for obtaining a plurality of the SiP modules.

Abstract: A display device is disclosed. The display device includes a substrate having a plurality of pixels, wherein each of the plurality of pixels includes at least one light emitting chip, and a structure on one side of at least one of the plurality of pixels. A base material of the light emitting chip is the same as a base material of the structure.

Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.

Abstract: A semiconductor package includes a semiconductor module, a first package extension frame, a second package extension frame, and a plurality of fasteners. The semiconductor module includes a first side surface, a second side surface, a first major surface, and a second major surface on an opposite side of the semiconductor module from the first major surface. The first package extension frame is configured to attach to the first side surface. The second package extension frame is configured to attach to the second side surface. The plurality of fasteners are configured to mechanically couple the first package extension frame and the second package extension frame to one or more of a circuit board arranged on the first major surface and/or a heat sink arranged on the second major surface.

Abstract: Provided is a method of manufacturing a ultra-small light-emitting diode (LED) electrode assembly, the method including preparing a base substrate, forming an electrode line including a first electrode and a second electrode on the base substrate, positioning a guide member having a plurality of slit portions therein on the base substrate, and inserting ultra-small LED devices into the plurality of slit portions of the guide member.

Abstract: A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

Abstract: Provided is a semiconductor device having: a terminal portion having a through hole is formed on a principal surface portion; and a casing portion in which an opening to make the principal surface portion of the terminal portion exposed is provided, wherein the opening has a corner portion corresponding to a corner of the principal surface portion of the terminal portion, wherein the casing portion has a thick portion, in which thickness of a resin may be greater than that of a middle portion between adjacent corner portions across two sides forming the corner portion, in a surrounding area of the opening. Furthermore, a slit portion extending outward from the corner portion may be formed in the casing portion. At least a part of the outline of the slit portion as viewed from the upper surface direction of the casing portion may be curved.

Abstract: A semiconductor device 1 includes a first drain terminal 4, connected to a drain electrode of a first semiconductor chip, a first gate terminal 5, connected to a gate electrode of the first semiconductor chip, a second drain terminal 6, connected to a drain electrode of a second semiconductor chip, a second gate terminal 7, connected to a gate electrode of the second semiconductor chip, a common source terminal 8, connected to a source electrode of the first semiconductor chip and a source electrode of the second semiconductor chip, and a sealing resin 9, sealing the respective semiconductor chips and the respective terminals. The respective terminals have exposed surfaces (lower surfaces) 43, 53, 63, 73, and 83 substantially flush with an outer surface (lower surface) 9b of the sealing resin 9 and exposed from the outer surface 9b.

Abstract: A method for processing product wafers using carrier substrates is disclosed. The method includes a step of bonding a first carrier wafer to a first product wafer using a first temporary adhesion layer between a first carrier wafer surface and a first product wafer first surface. Another step includes bonding a second carrier wafer to a second product wafer using a second temporary adhesion layer between a second carrier wafer surface and a second product wafer surface. Another step includes bonding the first product wafer to the second product wafer using a permanent bond between a first product wafer second surface and a second product wafer first surface. In exemplary embodiments, at least one processing step is performed on the first product wafer after the first temporary carrier wafer is bonded to the first product wafer before the second product wafer is permanently bonded to the first product wafer.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a composite stiffener selected to provide excellent resistance to warpage without detrimentally imposing excessive stress on a package substrate of the package assembly. In one example, the chip package assembly includes an integrated circuit die stacked on a top surface of a package substrate, and a composite stiffener coupled to a first edge of the package substrate. The composite stiffener includes a first stiffener member and a second stiffener member. The first stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member is disposed over the first stiffener member. The second stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member has a Young's modulus that is less than a Young's modulus of the first stiffener member.

Abstract: The present invention provides a heat dissipation assembly and an electronic device, where the heat dissipation assembly includes: a shielding element, where a via hole is disposed on the shielding element, the shielding element is electrically connected to ground copper of a PCB board, and a heat-generating electronic element is disposed on the PCB board; a heat pipe, located on the via hole, where the heat pipe is electrically connected to the shielding element, and the heat pipe, the PCB board, and the shielding element form an electromagnetic shielding can that is used to accommodate the heat-generating electronic element; and an elastic thermal interface material, disposed between the heat pipe and the heat-generating electronic element and mutually fitted to the heat pipe and the heat-generating electronic element.

Abstract: The present application discloses a packaging structure, the packaging structure includes a first substrate, a side of the first substrate including a power supply terminal; a second substrate; a metal extension layer, extending from the power supply terminal to both ends of the first side of the first substrate; and a packaging layer, covering the metal extension layer and fastening the first substrate and the second substrate.

Abstract: A stack type power module includes: a power semiconductor having a gate and an emitter, each of which has a pad shape, adjacent to each other on one surface of the power semiconductor, and a collector having a pad shape on another surface of the power semiconductor; an upper substrate layer stacked on an upper portion of the power semiconductor, and electrically connected to a metal layer that has a lower surface with which the collector is in contact; and a lower substrate layer stacked on a lower portion of the power semiconductor, and electrically connected to the metal layer that has an upper surface with which each of the gate and the emitter is in contact.

Abstract: A power converting device such that an overcurrent is interrupted and damage to a power semiconductor element can be prevented is obtained. The power converting device includes a power semiconductor element, a wiring member connected to an electrode of the power semiconductor element, a bus bar that supplies power to the power semiconductor element, and a frame that houses the power semiconductor element, wherein the bus bar has a connection terminal connected to the wiring member, and a fuse portion is provided in the connection terminal.

Abstract: A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.

Abstract: A component-mounting resin substrate includes a resin substrate and a component. The resin substrate includes a thermoplastic resin body. The component is mounted on the resin substrate by ultrasonic bonding. In a mounting area of the resin body in which the component is mounted, a cavity that is hollowed from a mounting surface on which the component is mounted is defined. A plating layer that includes a material harder than the resin body is disposed on at least a portion of a wall surface of the cavity.

Abstract: A lighting arrangement includes at least a first and a second LED lighting element arranged next to each other on a carrier surface. The spacer element has, at least in a portion thereof which is in contact with the second LED lighting element, a width which is less than 20% of a width of the first LED lighting element. The first LED lighting element comprises a spacer element projecting into a direction in parallel to the carrier surface. The second LED lighting element is arranged in contact with the spacer element such that it is arranged aligned relative to the first LED lighting element, and such that the first and second LED lighting elements are arranged at a distance forming a gap between the first and second LED lighting elements.

Abstract: A method of manufacturing a semiconductor power package includes: embedding a power semiconductor chip in an encapsulation, the encapsulation forming a housing of the semiconductor power package; and extending a layer of a covering material over at least a part of an outer main surface of the encapsulation. The covering material has a thermal conductivity greater than a thermal conductivity of the material of the encapsulation and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.

Abstract: An electronic component-incorporating substrate includes a lower substrate, an electronic component mounted on the lower substrate, and an upper substrate arranged above the electronic component and the lower substrate. The substrate further includes a substrate connecting member arranged between the lower substrate and the upper substrate and an encapsulation resin filling a gap between the lower substrate and the upper substrate to encapsulate the electronic component and the substrate connecting member. The upper substrate includes a substrate body and a solder resist layer arranged on a lower surface of the substrate body. The solder resist layer includes a groove extending in the solder resist layer from a directly-above region, located directly above at least the electronic component, to a side surface of the upper substrate.

Abstract: A package structure and method for forming the same are provided. The package structure includes a package component, a device die disposed over the package component, and the device die has a first height. The package structure also includes a dummy die adjacent to the device die, wherein the dummy die has a second height smaller than the first height. The package structure further includes a package layer between the device die and the dummy die.

Abstract: A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

Abstract: An LED light fixture is disclosed with an elongated housing that forms a open lower light channel and an upper light channel that is juxtaposed to the open lower light channel with electronics cavity or conduit positioned there between. The LED light fixture preferably has an elongated reflective insert that extends through the open lower light channel and creates a reflection channel from which the indirect and reflected light is emitted and a detachable cover structure that includes a diffusion lens and a removable baffle structure that attaches to side walls of the upper light channel.

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.

Abstract: An antenna carrier plate structure has a first circuit board and a second circuit board. The first circuit board has a first substrate and a conductive connector disposed in the first substrate. The conductive connector has two opposite connecting ends respectively protruding from two opposite surfaces of the first substrate. The second circuit board has a second substrate formed with a through hole, and a connecting plug is disposed in the through hole. One end of the connecting plug is formed with an engaging concave portion for engaging one end of the conductive connector of the first substrate. Therefore, each circuit board can be firmly fixed and electrically connected by engaging to form a multi-layer circuit board module, thereby avoiding joint tolerances during soldering and ensuring a correct connection of the joints.

Abstract: A semiconductor package including a package substrate including a mounting region and at least one through-hole arranged in the mounting region, and a semiconductor chip mounted on the mounting region, the semiconductor chip including a first side and a second side, the second side of the semiconductor chip being opposite to the first side of the semiconductor chip, the at least one through-hole of the package substrate being closer to the second side of the semiconductor chip than the first side of the semiconductor chip may be provided.

Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Abstract: A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means or an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part.

Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.

Abstract: A lid attach process includes providing a substrate and a die attached to the substrate, providing a lid and dipping a periphery of the lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid, and positioning the lid over the die and placing the lid on a top of the substrate with the adhesive material being adapted to interface with a periphery of the substrate.