Abstract: A semiconductor package includes a first semiconductor die, a first substrate, a second semiconductor die, and a second substrate. The first substrate is disposed on the first semiconductor die and includes a plurality of first metal line layers vertically spaced apart from each other, and each of the first metal line layers is electrically connected to one of the followings: a ground source and a plurality of power sources of different types. The second semiconductor die is disposed on the first substrate. The second substrate is disposed on the second semiconductor die and includes a plurality of second metal line layers vertically spaced apart from each other, and each of the second metal line layers is electrically connected to one of the followings: the ground source and the power sources of different types.

Abstract: A semiconductor assembly manufacturing method includes: providing a substrate including a first conductive circuit; disposing a first electronic component on a side of the substrate; forming a first plastic seal layer covering the substrate and the first electronic component; setting up a plurality of grooves in the first plastic seal layer, the groove exposes at least a portion of the first conductive circuit of the substrate; and filling a conductive material in each of the grooves by vacuum printing so as to form a second conductive circuit electrically connected to the first conductive circuit of the substrate, and a second electronic component pad position thereof in the first plastic seal layer.

Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Abstract: A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Abstract: A system integrating a fan-out package, including a first semiconductor die, with a second semiconductor die. In some embodiments the fan-out package includes the first semiconductor die, a mold compound, covering the first semiconductor die on at least two sides, and an electrical contact, on a lower surface of the first semiconductor die. The fan-out package may have a rabbet along a portion of a lower edge of the fan-out package.

Abstract: A semiconductor package includes a lead frame, a semiconductor chip, a plurality of three-dimensional wrings, and a mold resin. The semiconductor chip is mounted on the lead frame. The mold resin covers a part of the lead frame, the semiconductor chip, and a part of each of the plurality of three-dimensional wirings.

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

Abstract: According to one embodiment, a semiconductor device includes at least a package substrate, an external electrode, a mounting substrate, and a mounting electrode. A signal connection point of the external electrode is provided at an end portion in a longitudinal direction of the external electrode. A signal connection point of the mounting electrode is provided at an end portion of the mounting electrode. The end portion of the mounting electrode is opposite to the signal connection point of the external electrode facing to the mounting electrode in the longitudinal direction.

Abstract: Described are methods and apparatuses pertaining to stacked integrated circuits having application in ultra-low-power and small form factor design, with fast prototyping and mass-production cycle time, including application for millimeter wave radio frequency circuits.

Abstract: Apparatuses and methods for internal heat spreading for packaged semiconductor die are disclosed herein. An example apparatus may include a plurality of die in a stack, a bottom die supporting the plurality of die, a barrier and a heat spreader. A portion of the bottom die may extend beyond the plurality of die and a top surface of the bottom die extending beyond the plurality of die may be exposed. The barrier may be disposed alongside the plurality of die and the bottom die, and the heat spreader may be disposed over the exposed top surface of the bottom die and alongside the plurality of die.

Abstract: A semiconductor device package includes a carrier, an emitting device, a first building-up circuit and a first package body. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The emitting element is disposed on the first surface of carrier. The first building-up circuit is disposed on the second surface of the carrier. The first package body encapsulates the lateral surface of the carrier.

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example multi-die package includes a computer processor unit (CPU) die, a memory die stacked in vertical alignment with the CPU die, and artificial intelligence (AI) architecture circuitry to infer a workload for at least one of the CPU die or the memory die. The AI architecture circuitry is to manage power consumption of at least one of the CPU die or the memory die based on the inferred workload.

Abstract: A semiconductor package includes a package substrate having a hole pattern including a first through hole extending in a first direction and a second through hole extending in a second direction substantially perpendicular to the first direction, at least one first semiconductor chip disposed on the package substrate to overlap with the first through hole, at least one second semiconductor chip disposed on the package substrate to overlap with the second through hole, first bonding wires passing through the first through hole to electrically connect the at least one first semiconductor chip to the package substrate, and second bonding wires passing through the second through hole to electrically connect the at least one second semiconductor chip to the package substrate.

Abstract: Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate.

Abstract: A semiconductor package includes a package substrate, a die stack having a first sub-stack part and a second sub-stack part, an interface chip, and a bonding wire structure. The bonding wire structure includes a first signal wire connecting first signal die pads included in the first sub-stack part to each other, a first signal extension wire connecting the first signal wire to the interface chip, a second signal wire connecting second signal die pads included in the first sub-stack part to each other, a second signal extension wire connecting the second signal wire to the interface chip, an interpose wire connecting interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads to the interface chip, and a shielding wire branched from the interpose wire.

Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Abstract: A package and a method of forming the same are provided. A method includes forming a first die structure. The first die structure includes a die stack and a stacked dummy structure bonded to a carrier. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is a farthest integrated circuit die of the die stack from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.

Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips; and a plurality of input/output elements that are configured to perform a signal input/output operation to the plurality of penetration electrodes, wherein the semiconductor chips are joined together via no bump, one of the plurality of input/output elements is connected to each of the plurality of penetration electrodes such that a functional element connected to each of the plurality of penetration electrodes performs an ON or OFF operation at a predetermined timing, and the input/output element connected to a first of two adjacent penetration electrodes among the plurality of penetration electrodes and the input/output element connected to a second of two adjacent pene

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.

Abstract: A package assembly can include: a die electrically connected to outer pins of the package assembly; an electronic component located above the die and electrically connected to the die, wherein the electronic component is connected to the outer pins of the package assembly through conductive pillars; and a heat dissipation structure located between the die and the electronic component to facilitate heat dissipation of the electronic component, where the heat dissipation structure physically isolates the die and the electronic component such that electromagnetic interference from the electronic component to the die is substantially prevented.

Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.

Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

Abstract: A memory device includes a periphery wafer, a memory array chip stack, and a plurality of first conductive contacts. The periphery wafer has a functional surface. The memory array chip stack is disposed on the periphery wafer and has a functional surface, in which the functional surface of the periphery wafer faces toward the functional surface of the memory array chip stack, and a first side of the memory array chip stack is in a staircase configuration. The first conductive contacts are on the first side of the memory array chip stack, and between and interconnecting the functional surface of the periphery wafer and the functional surface of the memory array chip stack.

Abstract: An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.

Abstract: A lighting device (1) is provided comprising a support structure (13) extending from a heat sink (10) and comprising a mounting section (14) with a central mounting face (14.2), first and second lateral mounting faces (14.1, 14.3), and at least one heat dissipation member (18a, 18b) extending from an outer face (11a.1, 11a.3) of the support structure (13) comprising a respective one of the first and the second lateral mounting faces (14.1, 14.2), the at least one first heat dissipation member (18a, 18b) comprising an inclined surface (19a, 19b) which is inclined with respect to the respective one of the first and the second lateral mounting faces (14.1, 14.3) such that a thickness of the at least one first heat dissipation member (18a, 18b) increases along a direction (40) away from the mounting section (14).

Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Abstract: A memory device, a semiconductor device and their manufacturing methods are provided. One of the methods may include: providing a first die and a plurality of second dies, the first die having a first pad, each of the plurality of second dies having a second pad; stacking the plurality of second dies on the first die, the second pads and the first pad arranged in a stepwise manner, and projections of the second pads of any two adjacent second dies on the first die partially overlapped; forming a connecting hole passing through the second dies; and forming a conductive body filling the connecting hole and connecting the first pad and the second pads. This method simplifies the manufacturing process of a semiconductor device, reduces the cost thereof, and improves the production yield.

Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Abstract: A module includes a substrate, a plurality of components on an upper surface of the substrate, a component on a lower surface of the substrate, solder balls on the lower surface, sealing resin layers stacked on the upper surface and the lower surface of the substrate, and a shield film covering a side surface and an upper surface of the module. Part of each solder ball is exposed from a surface of the sealing resin layer, and the exposed parts are shaped to protrude from the sealing resin layer. The module can be connected to a mother substrate by connecting the protruding parts of the solder balls. There are gaps between the solder balls and the sealing resin layer, and the occurrence of cracks in the solder balls can be suppressed by reducing stress arising from a difference in thermal expansion coefficient between the solder and the resin.

Abstract: An interposer includes an interposer body; first and second lower patterns spaced apart from each other on a lower surface of the interposer body; and first and second upper patterns spaced apart from each other on an upper surface of the interposer body. The first and second upper patterns include first and second shape-securing layers spaced apart from each other on the upper surface of the interposer body, and first and second acoustic noise reduction layers disposed on the first and second shape-securing layers, respectively. An electronic component includes a capacitor and the interposer.

Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.

Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.

Abstract: A package structure and method for forming the same are provided. The package structure includes a semiconductor die formed over a first side of an interconnect structure, and the semiconductor die has a first height. The package structure also includes a first stacked die package structure formed over the first side of the interconnect structure, and the first stacked die package structure has a second height. The second height is greater than the first height. The package structure includes a lid structure formed over the semiconductor die and the first stacked die package structure. The lid includes a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die.

Abstract: A System in a Package (SiP) device is provided with an interconnect area or a physical space on a main SiP substrate that allows for a customizable second packaged component or device to be externally interconnected with the components on the main substrate of a packaged SiP to allow for modifications to the functionality of the components and devices on a primary (or main) SiP substrate.

Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

Abstract: A semiconductor device includes a supporting substrate, a semiconductor chip, a resin member, and a heat-dissipating metal layer. The supporting substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the supporting substrate. The semiconductor chip includes a plurality of electrodes. The semiconductor chip is bonded to the supporting substrate on one side thereof with the first surface. The resin member has a first surface and a second surface located opposite from each other in a thickness direction defined for the resin member. The resin member covers at least a side surface of the supporting substrate and a side surface of the semiconductor chip. The heat-dissipating metal layer is arranged in contact with the supporting substrate and the resin member to cover the second surface of the supporting substrate and the second surface of the resin member at least partially.

Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.

Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.

Abstract: A semiconductor device includes a lead frame having a die pad; a semiconductor chip having a front surface in which an integrated circuit is formed, and a back surface that is die-bonded onto the die pad through intermediation of an interposing film and an adhesive layer; and an encapsulating resin for encapsulating the lead frame, the adhesive layer, the interposing film, and the semiconductor chip. The interposing film has a first opening which forms a space between a part of the back surface of the semiconductor chip and the adhesive layer.

Abstract: Aspects of this disclosure relate to bulk acoustic wave components. A bulk acoustic wave component can include a substrate, at least one bulk acoustic wave resonator on the substrate, and a cap enclosing the at least one bulk acoustic wave resonator. The cap can include a sidewall spaced apart from an edge of the substrate. The sidewall can be 5 microns or less from the edge of the substrate.

Abstract: A package structure includes a first semiconductor die, an insulating encapsulant, a plurality of first through insulator vias, a plurality of second through insulator vias, and a redistribution layer. The insulating encapsulant is encapsulating the first semiconductor die. The first through insulator vias are located in a central area of the insulating encapsulant surrounding the first semiconductor die. The second through insulator vias are located in a peripheral area of the insulating encapsulant surrounding the plurality of first through insulator vias located in the central area, wherein an aspect ratio of the plurality of second through insulator vias is greater than an aspect ratio of the plurality of first through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the first semiconductor die, the plurality of first through insulator vias and the plurality of second through insulator vias.

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region.

Abstract: The present invention relates to a module that has a lower component of a module (1) having a material (3) in which at least one first structural element (4) is embedded, and an upper component of a module (2) having a material (3) in which at least a second component (16) is embedded. The upper component of the module (2) and the lower component of the module (1) are stacked, with the lower and the upper component of the module (2) being electrically connected and mechanically linked to each other. In addition, the present invention relates to a simple and cost-effective process for the production of a variety of modules. The invention makes it possible for the modules to be miniaturized with respect to surface and height and/or makes it possible to achieve greater integration by 3D packaging.

Abstract: A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.

Abstract: Discussed is a flexible display device to reduce a width of a bezel. The flexible display device includes a substrate being formed of a flexible material, a plurality of gate lines and a plurality of data lines crossing each other, a plurality of pads formed in a pad area of a non-display area, a plurality of links formed in a link area of the non-display area a plurality of insulation films formed over the entire surface of the substrate, and a first bending hole formed in a bending area of the non-display area, the first bending hole passing through at least one of the insulation films disposed under the link, wherein the bending area is bent such that the pads are disposed on the lower surface of the substrate.