Housing Or Package Filled With Solid Or Liquid Electrically Insulating Material Patents (Class 257/687)
  • Patent number: 11387352
    Abstract: An object of the present disclosure is to suppress a shrinkage cavity without affecting the layout or the insulation performance of the semiconductor element in a power semiconductor device. A power semiconductor device includes a heat radiation plate; an insulating substrate bonded in a bonding region on an upper surface of the heat radiation plate with a bonding material containing a plurality of elements having different solidification points; a semiconductor element mounted on an upper surface of the insulating substrate; and a bonding wire bonded in the bonding region on the upper surface of the heat radiation plate such that the bonding wire surrounds the semiconductor element in plan view.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: July 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Norikazu Sakai
  • Patent number: 11376770
    Abstract: A method of manufacturing an electronic device includes a step of housing an electronic component in a metal mold, then filling the metal mold with a molding material, wherein the metal mold includes a cavity having a rectangular planar shape and housing the electronic component, and a dummy cavity communicated with a side surface having the smallest gap with the electronic component out of four side surfaces included in the cavity, and in the step of filling the metal mold with the molding material, the molding material inflows into the cavity, and the molding material in the cavity inflows into the dummy cavity.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: July 5, 2022
    Assignee: Seiko Epson Corporation
    Inventors: Masataka Kazuno, Tetsuya Otsuki
  • Patent number: 11374136
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11322422
    Abstract: A vehicle power conversion apparatus according to the present disclosure includes a housing attached to a vehicle, a cooler including a heat receiver that is disposed on the side near the housing and has a heated surface provided with semiconductor elements, and a heat radiator disposed on a surface of the heat receiver opposite to the heated surface, and a position adjusting member to adjust the position of the end of the heat radiator distant from the housing in the direction approaching rigging limit of the vehicle.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 3, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuta Matsumoto, Hirokazu Takabayashi
  • Patent number: 11289468
    Abstract: A package structure includes an inner wiring layer, a first dielectric layer, a first outer wiring layer, and an electronic component assembly. The first dielectric layer includes a first surface and a second surface facing away from the first surface. The inner wiring layer and the electronic component assembly are embedded into the first dielectric layer from the first surface. The first outer wiring layer is disposed on the second surface. The electronic component assembly includes a first electronic element and a second electronic element. The second electronic element is disposed close to the second surface, and an electrical connector of the second electronic element faces the second surface. The first electronic element is disposed on a side of the second electronic element facing away from the second surface, and exposed from the first surface. The first outer wiring layer electrically connects the electrical connector of the second electronic element and the inner wiring layer, respectively.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 29, 2022
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Patent number: 11282804
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a polymer layer and a redistribution layer. The encapsulant laterally encapsulates the die. The polymer layer is on the encapsulant and the die. The polymer layer includes an extending portion having a bottom surface lower than a top surface of the die. The redistribution layer penetrates through the polymer layer to connect to the die.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11276806
    Abstract: A semiconductor device package includes a carrier, a die, an encapsulation layer and a thickness controlling component. The die is disposed on the carrier, wherein the die includes a first surface. The encapsulation layer is disposed on the carrier, and encapsulates a portion of the first surface of the die. The encapsulation layer defines a space exposing another portion of the first surface of the die. The thickness controlling component is disposed in the space.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Wen Chiang, Kuang-Hsiung Chen, Lu-Ming Lai, Hsun-Wei Chan, Hsin-Ying Ho, Shih-Chieh Tang
  • Patent number: 11239130
    Abstract: A method includes performing a first molding process to enclose a portion of a first semiconductor die in a first package structure with an opening that exposes a portion of a second semiconductor die mounted to the first semiconductor die, as well as performing a deposition process to deposit a stress absorbing material in the opening of the first package structure to cover the portion of the second semiconductor die, and performing a second molding process to enclose a portion of the stress absorbing structure in a second package structure that extends on a side of the first package structure.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dolores Babaran Milo, Floro Lopez Camenforte, III, Joe Anne Feive Carbonell Lopez
  • Patent number: 11227981
    Abstract: A method for manufacturing a light emitting device includes: a substrate preparation step for preparing a substrate having a first region on which a plurality of light emitting devices are formed, and a second region surrounding the first region; a reinforcing member forming step for forming a reinforcing member by applying a resin material on the second region and hardening the resin material; a mounting step for mounting a plurality of light emitting elements on the first region; a light-transmissive member placing step for forming a plurality of light-transmissive members respectively on the light emitting elements; a sealing member forming step for sealing the plurality of light emitting elements and the plurality of light-transmissive members using a sealing member; and a cutting step for cutting the substrate and the sealing member and separating into individual light emitting devices.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: January 18, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Yoshiki Sato, Kazuya Tamura
  • Patent number: 11217516
    Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Sriram Muthukumar, Charles A. Gealer
  • Patent number: 11172573
    Abstract: A power supply device (100-1) includes: a substrate (20) on which an electric component (25) is mounted; a chassis (10) including a chassis surface (11) to be a surface facing one surface (20a) of the substrate (20); and cured insulating resin (27-1) to be placed between the one surface (20a) of the substrate (20) and the chassis surface (11) so as to be connected to the one surface (20a) and the chassis surface (11), the cured insulating resin (27-1) having a thermal conductivity between 1 W/mK and 10 W/mK inclusive.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 9, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takashi Miyamoto, Naoki Yasuda, Shinichi Okada, Hiroyuki Osuga, Ryota Kusano
  • Patent number: 11156790
    Abstract: The invention provides a photonic package system comprising at least two optical alignment pins integrated on a package substrate. A key feature of this invention is the addition of alignment structures within the package. When combined with the use of micro optics it enables a ‘fiber-less’ photonic package system that requires no physical connection between and optical fiber and the photonic package system.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 26, 2021
    Assignee: University College Cork
    Inventor: Peter O'Brien
  • Patent number: 11107784
    Abstract: A semiconductor device includes: a multilayer substrate which includes a circuit board and an insulating plate on which the circuit board is formed; and a contact part having a cylindrical hollow hole therein and an open end bonded to a bonding area on the front surface of the circuit board via bonding material. In the case of this semiconductor device, wettability of a contact area of the contact part with respect to the bonding material is approximately equal to wettability of at least the bonding area of the circuit board with respect to the bonding material. Thus, the rising of the bonding material into the hollow hole of the contact part during heating performed when the contact part is bonded to the circuit board is reduced.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 31, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Masaoki Miyakoshi, Masayuki Soutome, Kazuya Adachi, Takeshi Yokoyama
  • Patent number: 11102887
    Abstract: An electrical connection device includes a first conductive plate provided with a cutout in a circumferential edge portion of the first conductive plate and a second conductive plate adjacent to the first conductive plate without contacting the first conductive plate. A switching element includes a first terminal connected to the first conductive plate, a second terminal connected to the second conductive plate, and a control terminal, and that is turned on or off according to a voltage of the control terminal, wherein the electrical connection device further includes an insulator embedded in the cutout. A conductive path is provided on the surface of the insulator and that does not contact the first conductive plate, and to which the control terminal is connected.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 24, 2021
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Akira Haraguchi
  • Patent number: 11094603
    Abstract: A power semiconductor device includes a planar rectifying element, a base electrode, a first solder layer, a lead electrode, a second solder layer, and first and second sealing portions. The base electrode is electrically connected to the rectifying element via the first solder layer formed on a first surface of the rectifying element. The lead electrode is electrically connected to the rectifying element via the second solder layer formed on a second surface of the rectifying element. The first sealing portion is formed of a first resin and provided in a recess; the recess is formed by the first surface of the rectifying element and the first solder layer or by the second surface of the rectifying element and the second solder layer. The second sealing portion is formed of a second resin and separately from the first sealing portion to cover an outer surface of the first sealing portion.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 17, 2021
    Assignee: DENSO CORPORATION
    Inventor: Shou Hasegawa
  • Patent number: 11069593
    Abstract: Provided is a technique for preventing warps of cooling plates due to a contraction of a joining material, thereby preventing a reduction in cooling performance of a semiconductor device. The semiconductor device includes the following: a first cooling plate; a second cooling plate facing the first cooling plate; a semiconductor chip joined between the circuit pattern of the first cooling plate and the circuit pattern of the second cooling plate with a joining material; and a case containing part of the first cooling plate, part of the second cooling plate, and the semiconductor chip. The semiconductor chip is mounted in a semiconductor-chip mounting part between the first cooling plate and the second cooling plate. The case is provided with a portion corresponding to the semiconductor-chip mounting part and to surroundings thereof. The portion has an up-and-down width greater than an up-and-down width of the remaining portions of the case.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 20, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noboru Miyamoto, Taishi Sasaki
  • Patent number: 11056455
    Abstract: In some embodiments, an electronic module is disclosed. The electronic module can include a carrier and an integrated device die having an upper surface, a lower surface, and an outer side edge. The integrated device die can include a first surface recessed from the lower surface and a second surface extending between the lower surface and the first surface. The second surface can be laterally inset from the outer side edge. The electronic module can include a mounting compound comprising a first portion disposed between the lower surface of the integrated device die and the carrier and a second portion disposed along at least a portion of the second surface of the integrated device die.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 6, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Vikram Venkatadri, David Frank Bolognia
  • Patent number: 11005054
    Abstract: A display device according to an exemplary embodiment includes: a display panel for displaying an image; a support plate provided on one side of the display panel; and a heat sink layer provided below the support plate, wherein the heat sink layer includes a metal alloy having thermal conductivity that is equal to or greater than 150 W/mK and equal to or less than 340 W/mK, and an elastic modulus that is equal to or greater than 100 GPa and equal to or less than 140 GPa.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hirotsugu Kishimoto
  • Patent number: 11004771
    Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Chi-Hsi Wu, Shin-Puu Jeng, Tsung-Yu Chen, Wensen Hung
  • Patent number: 10998255
    Abstract: Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 4, 2021
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Jerry Lynn White, Hamdan Ismail, Frank Danaher, David James Dougherty, Aruna Manoharan
  • Patent number: 10998248
    Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 4, 2021
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 10957671
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 23, 2021
    Assignee: Intel Deutschland GMBH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Patent number: 10937708
    Abstract: A power module that can realize insulation performance by suppressing the occurrence of bubbles in silicone gel and the detachment between the silicone gel and an insulating substrate during high temperature, during low temperature and during low atmospheric pressure, to thereby suppress degradation of insulation performance. The power module includes: an insulating substrate having a front surface on which a power semiconductor element is mounted; a base plate joined to a back surface of the insulating substrate; a case fixed to the base plate and surrounding the insulating substrate; a cover fixed to the case and forming a sealed region; and a silicone gel serving as a filling member filling the entire sealed region and having internal stress maintained at compressive stress.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 2, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masaki Taya
  • Patent number: 10923441
    Abstract: A method and circuit for implementing transient electronic circuits for security applications, and a design structure on which the subject circuit resides are provided. Silver nanowire traces are fabricated forming a protection circuit in a soluble material. A frangible material is provided separating the soluble material from a solvent layer proximately located. During a tampering event the frangible material is ruptured releasing the solvent which contacts and dissolves the soluble material and disperses the silver nanowire traces creating an electrical open in the protection circuit. The electrical open enables enhanced tampering detection.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: February 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Campbell, Sarah Czaplewski-Campbell, Timothy Tofil, Joseph Kuczynski
  • Patent number: 10910289
    Abstract: The present technology relates to an electronic substrate that achieves a reduction in the size of a substrate and enables a void risk in an underfill to be reduced, and an electronic apparatus. An electronic substrate in one aspect of the present technology includes: an electronic chip that is placed above a substrate; an electrode that exists between the substrate and the electronic chip and electrically connects the substrate and the electronic chip; an underfill with which a space between the substrate and the electronic chip is filled so that the electrode is sealed and protected; a protection target to be protected from inflow of the underfill, the protection target being formed on the substrate; and an underfill inflow prevention unit that is formed in the substrate so as to surround an entirety or a portion of the protection target. The present technology is applicable to, for example, a solid-state image sensor.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 2, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masataka Maehara
  • Patent number: 10903136
    Abstract: A package structure is provided, including a first insulating layer, a second insulating layer, a third insulating layer, and a chip. The second insulating layer is disposed on the first insulating layer, the chip is disposed in the second insulating layer, and the third insulating layer is disposed on the second insulating layer. The heat conductivity of the second insulating layer is lower than the heat conductivity of the first insulating layer, and the hardness of the second insulating layer is lower than the hardness of the first insulating layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 26, 2021
    Assignee: TDK Taiwan Corp.
    Inventors: Ming-Hung Wu, Chi-Fu Wu, An-Ping Tseng, Hao-Yu Wu
  • Patent number: 10896877
    Abstract: An improved SiP structure includes one or more interposers positioned to form a center cavity into which one or more electronic components can be mounted. The improved SiP structure provides a reduced footprint using the one or more interposers and formed center cavity without the need of laser drilling, exposed molding, and/or double side molding.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 19, 2021
    Assignee: Flex Ltd.
    Inventors: Cheng Yang, Dongkai Shangguan, Bo Li, Venkat Iyer
  • Patent number: 10892214
    Abstract: A semiconductor chip includes a mounting surface having a plurality of first conductive contacts and at least one second conductive contact. Each of the first contacts is arranged in a regularly spaced apart array such that centroids of immediately adjacent first contacts are separated from one another in a first direction by a first distance. Each of the first contacts have an identical first lateral extent. The second conductive contact is at least partially within an area which has the first lateral extent and is separated from an immediately first contact by the first distance. Either the second conductive contact has a second lateral extent that is less than the first lateral extent; or a centroid of the second conductive contact is separated in the first direction from the centroid of one of the first contacts by a second distance that is different from the first distance.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 12, 2021
    Assignee: Infineon Technologies AG
    Inventor: Dietrich Bonart
  • Patent number: 10886202
    Abstract: Provided is a semiconductor device capable of having simple wiring in mounting the semiconductor device. The semiconductor device includes at least one P-terminal, at least one N-terminal, a power output terminal, at least one power supply terminal, at least one ground (GND) terminal, at least one control terminal, and a package that is rectangular in a plan view and accommodates an insulated gate bipolar transistor (IGBT) being a high-side switching element, an IGBT being a low-side switching element, and a control circuit. The at least one control terminal is disposed on a first side of the package, opposite to a second side on which the power output terminal is disposed. The at least one P-terminal, the at least one N-terminal, the at least one power supply terminal, and the at least one GND terminal are disposed on a third side of the package, orthogonal to the second side.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 5, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Nakamura
  • Patent number: 10877519
    Abstract: An electronic device housed in glass or other fragile material which is nevertheless proofed against breakage includes a shell, a battery, and a display screen formed on one side of the battery and received in the shell. The shell comprises a glass back cover and a crack-proof layer. The crack-proof layer is formed on the glass back cover. The battery abuts the crack-proof layer. The display screen is assembled beside the battery. The display screen is received in and partially exposed to the shell. The battery is electronically connected to the display screen. The electronic device is protected within the glass back cover which is itself proofed against shock and breakage when dropped or impacted. The disclosure further provides a method for manufacturing the electronic device.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: December 29, 2020
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Yi-Ching Lin, Ting-Chu Lee
  • Patent number: 10833040
    Abstract: A semiconductor package includes a core member having a cavity penetrating through first and second surfaces, a semiconductor chip disposed in the cavity and having an active surface having connection, a passive component module disposed in the cavity, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the passive components are exposed, a connection member on the second surface and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Ho Baek, Young Sik Hur, Joo Hwan Jung
  • Patent number: 10796981
    Abstract: A semiconductor package includes an electrically insulating first encapsulant body having an upper surface, a first semiconductor die encapsulated within the first encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the first encapsulant body, a plurality of electrically conductive leads, each of the leads having interior ends that are encapsulated within the first encapsulant body and outer ends that are exposed from the first encapsulant body, and a first direct electrical connection between the first conductive pad and the interior end of a first lead from the plurality. The first direct electrical connection includes a first conductive track formed in the upper surface of the first encapsulant body. The first encapsulant body includes a laser activatable mold compound. The first conductive track is formed in a first laser activated region of the laser activatable mold compound.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 6, 2020
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Khay Chwan Saw
  • Patent number: 10772194
    Abstract: A circuit board that includes a substrate that has an upper surface on which a circuit pattern is formed, and a lower surface to which a plurality of bus bars that are spaced apart are fixed; a placement through hole that extends through the upper surface and the lower surface and faces a bus bar of the plurality of bus bars and in which an electronic component is placed; and a terminal conductor foil that protrudes inward into the placement through hole from the lower surface and to which a terminal of the electronic component is connected.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: September 8, 2020
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tou Chin, Arinobu Nakamura
  • Patent number: 10748832
    Abstract: A heat sink for a semiconductor chip device includes cavities in a lower surface thereof for receiving electrical components on a top surface of the semiconductor chip, and a pedestal extending through an opening in the semiconductor chip for contacting electrical components on a bottom surface of the semiconductor chip. A lid may also be provided on the bottom surface of the semiconductor chip for protecting the electrical components and for heat sinking the electrical components to an adjacent device or printed circuit board.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: August 18, 2020
    Assignee: Elenion Technologies, LLC
    Inventor: Nathan A. Nuttall
  • Patent number: 10737410
    Abstract: A method of manufacturing a sealed circuit card assembly includes disposing a circuit card assembly within a volume defined by a housing and at least partially filling the volume with a curable liquid such that the curable liquid encapsulates at least a circuit card. The method may also include curing the curable liquid to form a potted circuit card assembly and, after at least partially filling the volume with the curable liquid and after curing the curable liquid, vacuum impregnating the potted circuit card assembly with a sealant to seal any exposed interfaces or cracks to form the sealed circuit card assembly. Accordingly, the sealed circuit card assembly may include a first cured material encapsulating the circuit card of the circuit card assembly and a second cured material disposed within, for example, a porosity of the first cured material.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 11, 2020
    Assignee: GOODRICH CORPORATION
    Inventors: Michael A. Metzger, James M. Martin, Jr., Paul L. Summers
  • Patent number: 10727209
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first element insulating part, and an insulating sealing member. The first semiconductor element includes a first semiconductor chip and a first chip electrode electrically connected to the first semiconductor chip. The first semiconductor chip has a first surface crossing a first direction, a second surface crossing the first direction and distant from the first surface, and a third surface between the first and second surfaces. The first chip electrode is disposed on the first surface. The first element insulating part includes a first portion and a second portion continuous to the first portion. The insulating sealing member includes a third portion and a fourth portion continuous to the third portion. The first portion is between the first surface and the third portion, and the second portion is between the third surface and the fourth portion.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 28, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiro Iguchi, Akiya Kimura, Akihiro Sasaki
  • Patent number: 10651133
    Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Su Chang Lee
  • Patent number: 10651215
    Abstract: The present invention relates to a sensor system. The sensor system comprises a component carrier and a sensor having a control unit and a sensor unit. At least a part of the sensor unit is located within the component carrier.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 12, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Mikael Tuominen
  • Patent number: 10643922
    Abstract: A base plate includes a heat dissipation metal plate and a resin insulating layer. The resin insulating layer is formed on the heat dissipation metal plate. The resin insulating layer is provided with a notch where part of the heat dissipation metal plate is exposed. A case is bonded to an exposure part being part of the heat dissipation metal plate by means of a bonding agent.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshitaka Otsubo, Yoshitaka Kimura
  • Patent number: 10617012
    Abstract: A method of manufacturing a flexible electronic device is described. The method comprises arranging an electronic component on a temporary carrier, providing a flexible laminate comprising an adhesive layer, pressing the temporary carrier and the flexible laminate together with the adhesive layer facing the temporary carrier such that the electronic component is pushed into the adhesive layer, and removing the temporary carrier. Further, a corresponding flexible electronic device is described.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: April 7, 2020
    Assignee: AT & S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventors: Andreas Zluc, Johannes Stahr
  • Patent number: 10510669
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
  • Patent number: 10510936
    Abstract: A light-emitting device package includes a lead frame, a light-emitting device chip, a molding structure, and a plurality of slots. The lead frame includes a first lead and a second lead including metal and spaced apart from each other. The light-emitting device chip is mounted on a first area of the lead frame, which includes a part of the first lead and a part of the second lead. The molding structure includes an outer barrier surrounding an outside of the lead frame and an inner barrier. The plurality of slots are formed in each of the first lead and the second lead. The inner barrier divides the lead from into the first area and a second area. The inner barrier fills between the first lead in the second lead. The second area is located outside of the first area. The plurality of slots are filled by the molding structure.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-hoon Yun, Jong-sup Song, Seol-young Choi
  • Patent number: 10490491
    Abstract: A lead frame extends from inside a sealing resin to outside the sealing resin, and is placed to make contact with a main surface of an insulating sheet opposite to a heat dissipation plate. A semiconductor element is jointed to at least a portion of a main surface of the lead frame opposite to the insulating sheet within the sealing resin. The surface of the insulating sheet in contact with the lead frame is inclined and lowered to move away from the lead frame in an end region including at least a portion of an outermost end in plan view of the insulating sheet. The sealing resin enters a region between the lead frame and the insulating sheet in the end region. The lead frame is flat at least within the sealing resin.
    Type: Grant
    Filed: December 25, 2015
    Date of Patent: November 26, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Tada, Kei Yamamoto, Mariko Takahara
  • Patent number: 10462915
    Abstract: An electronic module includes a first circuit board. The first circuit board has electronic components, spacers, a cover plate, and a casting compound. The spacers are positioned so as to rest at least in corner regions of the first circuit board. The cover plate is positioned on the spacers. The casting compound acts as an end face and seals a gap formed by the spacers between the first circuit board and the cover plate, so as to form a housing for the electronic components, which are positioned therein. The casting compound secures the cover plate to the first circuit board via positive engagement. A coefficient of linear thermal expansion of the casting compound corresponds substantially to a coefficient of linear thermal expansion of the circuit board and of the cover plate.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: October 29, 2019
    Assignee: Robert Bosch GmbH
    Inventor: Uwe Liskow
  • Patent number: 10461042
    Abstract: A semiconductor module includes: a first substrate having a first insulating substrate and a first conductor layer; a power device part having a first electrode, a second electrode and a gate electrode; a second substrate having a second insulating substrate, a second conductor layer and a third conductor layer wherein a hole is formed in the second insulating substrate, the second conductor layer has a bonding portion and a surrounding wall portion; an inner resin portion; a control IC; and an outer resin portion, wherein the first substrate, the power device part, the second substrate and the control IC are stacked in this order, a connector is disposed in the inside of the hole, and the gate electrode is electrically connected to a control signal output terminal of the control IC through a connector.
    Type: Grant
    Filed: January 31, 2016
    Date of Patent: October 29, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kosuke Ikeda, Yuji Morinaga
  • Patent number: 10399256
    Abstract: A method of manufacturing a sealed circuit card assembly includes disposing a circuit card assembly within a volume defined by a housing and at least partially filling the volume with a curable liquid such that the curable liquid encapsulates at least a circuit card. The method may also include curing the curable liquid to form a potted circuit card assembly and, after at least partially filling the volume with the curable liquid and after curing the curable liquid, vacuum impregnating the potted circuit card assembly with a sealant to seal any exposed interfaces or cracks to form the sealed circuit card assembly. Accordingly, the sealed circuit card assembly may include a first cured material encapsulating the circuit card of the circuit card assembly and a second cured material disposed within, for example, a porosity of the first cured material.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: September 3, 2019
    Assignee: GOODRICH CORPORATION
    Inventors: Michael A. Metzger, James M. Martin, Jr., Paul L. Summers
  • Patent number: 10381286
    Abstract: A power module is disclosed. The power module includes a first substrate, a first metal layer, at least one conductive structure and at least one power device. The first metal layer is disposed on the first substrate. The first metal layer has a first thickness d1. The first thickness d1 satisfies: 5 ?m?d1?50 ?m. The conductive structure is disposed at a position different to the first metal layer on the first substrate. The conductive structure has a second thickness d2. The second thickness d2 satisfies: d2?100 ?m. The power device is disposed on the first substrate, the first metal layer or the conductive structure. The driving electrode of the power device is electrically connected to the first metal layer. The power electrode of the power device is electrically coupled to the conductive structure.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: August 13, 2019
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Shou-Yu Hong, Gan-Yu Zhou, Jian-Hong Zeng, Zhen-Qing Zhao
  • Patent number: 10332814
    Abstract: A bonded system includes a reconstituted wafer including a hygroscopic material. A moisture barrier layer is arranged over a surface of the reconstituted wafer. An adhesive layer is arranged over a surface of the moisture barrier opposite the reconstituted wafer. A carrier is arranged over a surface of the adhesive layer opposite the moisture barrier. The adhesive layer adhesively bonds the reconstituted wafer and the carrier together.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies AG
    Inventors: Claus Von Waechter, Christian Altschaeffl, Holger Doepke, Uwe Hoeckele, Franz Xaver Muehlbauer, Daniel Porwol, Tobias Schmidt, Christian Schweiger, Carsten Von Koblinski
  • Patent number: 10332813
    Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sushumna Iruvanti, Shidong Li, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 10256192
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, at least one component-embedded substrate disposed adjacent the semiconductor chip in the through-hole and spaced apart from the semiconductor chip by a predetermined distance and having a plurality of passive components embedded therein, an encapsulant encapsulating at least portions of the first connection member, the at least one component-embedded substrate, and the semiconductor chip, and a second connection member disposed on the first connection member, the at least one component-embedded substrate, and the semiconductor chip.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Hee Yi, Byoung Chan Kim, Yong Ho Baek, Jung Hyun Cho