Housing Or Package Filled With Solid Or Liquid Electrically Insulating Material Patents (Class 257/687)
  • Patent number: 10332813
    Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sushumna Iruvanti, Shidong Li, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 10332814
    Abstract: A bonded system includes a reconstituted wafer including a hygroscopic material. A moisture barrier layer is arranged over a surface of the reconstituted wafer. An adhesive layer is arranged over a surface of the moisture barrier opposite the reconstituted wafer. A carrier is arranged over a surface of the adhesive layer opposite the moisture barrier. The adhesive layer adhesively bonds the reconstituted wafer and the carrier together.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies AG
    Inventors: Claus Von Waechter, Christian Altschaeffl, Holger Doepke, Uwe Hoeckele, Franz Xaver Muehlbauer, Daniel Porwol, Tobias Schmidt, Christian Schweiger, Carsten Von Koblinski
  • Patent number: 10256173
    Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first package body and at least one connecting element. The substrate has a first surface. The first package body is disposed adjacent to the first surface of the substrate, and defines at least one cavity. The connecting element is disposed adjacent to the first surface of the substrate and in a corresponding cavity. A space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity. An end portion of the connecting element extends beyond an outermost surface of the first package body.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 9, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jun-Chieh Wu, Yu-Hsiang Chao, Chung-Yao Chang, Chun-Cheng Kuo
  • Patent number: 10256192
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, at least one component-embedded substrate disposed adjacent the semiconductor chip in the through-hole and spaced apart from the semiconductor chip by a predetermined distance and having a plurality of passive components embedded therein, an encapsulant encapsulating at least portions of the first connection member, the at least one component-embedded substrate, and the semiconductor chip, and a second connection member disposed on the first connection member, the at least one component-embedded substrate, and the semiconductor chip.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Hee Yi, Byoung Chan Kim, Yong Ho Baek, Jung Hyun Cho
  • Patent number: 10249567
    Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: April 2, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Jie-Mo Lin, Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang
  • Patent number: 10242926
    Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 26, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Cheow Khoon Oh, Ming-Chen Lu, Xiaoming Sui, Bo Chen, Vincent Xue
  • Patent number: 10236806
    Abstract: The present disclosure relates to electric motors. The teachings thereof may be embodied in a power module, e.g., a power module for the delivery of a phase current for a current phase of an electric motor. For example, a power module may include: a circuit carrier having a surface; at least two first contact surfaces, a second contact surface, at least two third contact surfaces defined on the surface; a first power transistor connected to each of the at least two first contact surfaces; at least two second power transistors connected to the second contact surface; wherein the at least two second power transistors are connected via a further contact surface to one of the at least two third contact surfaces; and the at least two first and the at least two third contact surfaces are arranged one after the other, in one direction, and the second contact surface is disposed next to both the at least two first and the at least two third contact surfaces.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: March 19, 2019
    Assignee: CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Harald Holzer, Frank Meyer, Thomas Schmid, Matthias Hammerl, Gerald Hauer
  • Patent number: 10211072
    Abstract: Embodiments of the present disclosure generally describe methods for minimizing the occurrence and the extent of die shift during the formation of a reconstituted substrate in fan-out wafer level packaging processes. Die shift is a process defect that occurs when a die (device) moves from its intended position within a reconstituted substrate during the formation thereof. Generally, the methods disclosed herein include depositing a device immobilization layer and/or a plurality of device immobilization beads over and/or adjacent to a plurality of singular devices (individual dies), and the carrier substrate they are positioned on, before forming a reconstituted substrate with an epoxy molding compound. The device immobilization layer and/or the plurality of device immobilization beads immobilize the plurality of singular devices and prevents them from shifting on the carrier substrate during the molding process.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Roman Gouk, Guan Huei See, Yu Gu, Arvind Sundarrajan, Kyuil Cho, Colin Costano Neikirk, Boyi Fu
  • Patent number: 10193250
    Abstract: According to example embodiments, a substrate for a power module includes a first part, a second part, and a third part on a same surface of an underlying part of the substrate. The first part, the second part, and the third part may be spaced apart from each other, electrically insulated from each other, and not directly contacting each other. The third part may surround the first part and the second part. A first element module may be on the third part. The first part, the second part, and the third part may be conductive.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Che-heung Kim, Chang-sik Kim, Seong-woon Booh
  • Patent number: 10186607
    Abstract: An object is to provide a technique that enables suppression of oscillation of a gate signal waveform. A power semiconductor device includes a power semiconductor chip, a plurality of collector main terminals and a plurality of emitter main terminals electrically connected to the power semiconductor chip, and a signal line. The plurality of collector main terminals and the plurality of emitter main terminals have protrusion portions which protrude from a disposition surface of the power semiconductor chip, respectively, and the signal line surrounds, with respect to these protrusion portions, an entire circumference of all the protrusion portions and is spaced apart therefrom in plan view.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: January 22, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hatori, Shuichi Kitamura, Tetsuo Motomiya
  • Patent number: 10170673
    Abstract: An LED package structure includes a multilayer circuit board, an LED chip, and a cover. The multilayer circuit board has a conductive layer, a first resin layer disposed on the conductive layer, and a first circuit layer disposed on the first resin layer. The first resin layer has a first opening, and a portion of the conductive layer is partially exposed from the first resin layer via the first opening such that a mounting region is exposed. The first circuit layer has a second opening, and the second opening exposes the mounting region. The LED chip is fixed on the mounting region by passing it through the first and second openings, and the LED chip is connected to the first circuit layer by wires. The cover is disposed on the first resin layer and covers the LED chip and the first circuit layer.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 1, 2019
    Assignees: LITE-ON OPTOTECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chen-Hsiu Lin, Tsung-Kang Ying, Pin-Feng Hung
  • Patent number: 10068879
    Abstract: An integrated circuit (IC) device is described. The IC device includes a substrate. A connection component including a cavity therethrough is attached to the substrate. A memory die is positioned in the cavity of the connection component and is electrically coupled to the substrate. A logic die extends over the memory die and at least a portion of the connection component, and is electrically coupled to the connection component and the memory die. The connection component is formed free of through silicon vias and is electrically coupled to the substrate through wire bonding.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: September 4, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventor: Arun Virupaksha Gowda
  • Patent number: 10037970
    Abstract: Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: July 31, 2018
    Assignee: NXP USA, Inc.
    Inventors: David Clegg, James S. Golab, Trent Uehling, Tingdong Zhou
  • Patent number: 9983154
    Abstract: The present disclosure is related to a method for detection of defects in a printed pattern of geometrical features on a semiconductor die, the pattern comprising an array of features having a nominal pitch, the method comprising determining deviations from the nominal pitch in the printed pattern, and comparing the printed pattern with another version of the pattern, the other version having the same or similar pitch deviations as the printed pattern. According to various embodiments, the other version of the pattern may a printed pattern on a second die, or it may be a reference pattern, obtained by shifting features of the array in a version having no or minimal pitch deviations, so that the pitch deviations in the reference pattern are the same or similar to the pitch deviations in the printed pattern under inspection.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: May 29, 2018
    Assignee: IMEC VZW
    Inventors: Sandip Halder, Philippe Leray
  • Patent number: 9984948
    Abstract: A power electronics module includes: a baseplate, a power semiconductor chip arranged on the baseplate, and an encapsulation structure arranged on the baseplate and configured to encapsulate the power semiconductor chip, wherein the encapsulation structure is an epoxy having an elastic modulus in a range of 1 to 20 Giga Pascal, GPa, at room temperature and a coefficient of thermal expansion less than 20 ppm/K.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: May 29, 2018
    Assignee: ABB Schweiz AG
    Inventors: David Guillon, Heinz Lendenmann, Hui Huang
  • Patent number: 9985186
    Abstract: A method for laminating a film over a light emitting diode (LED), where the thickness of a portion of the film disposed over the top surface of the LED is reduced by pressing a flattening element against the top surface of the LED. The resulting form of the phosphor encapsulation allows for an improved color homogeneity.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: May 29, 2018
    Assignee: Lumileds LLC
    Inventor: Peter Mahowald
  • Patent number: 9966819
    Abstract: The invention relates to an electric machine (10) which is embodied as an alternator, comprising a rotor (20) and an axis of rotation (183), a stator iron (17) which maintains a stator winding (18). Said stator winding (18) comprises phase terminals of winding wires (204), a rectifier circuit (151) which comprises at least one bridge circuit consisting of a positive diode (99) and a negative diode (58). Said positive diode (99) and the negative diode (58) are connected in an electrically conductive manner to the phase terminal of winding wires (204) by means of a metal connecting element (133, 146) which has two half arms (215). One half arm (215) is connected in an electrically conductive manner to a positive diode (99) by means of a connecting section (216) and another half arm (215) is connected in an electrically conductive manner to the negative diode (58) by means of another connecting section.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: May 8, 2018
    Assignee: SEG Automotive Germany GmbH
    Inventors: Ruediger Schroth, Klaus Herbold, Gianna Rivera-Schlottbohm, Vassilios Sekertzis
  • Patent number: 9953914
    Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: April 24, 2018
    Assignee: Invensas Corporation
    Inventor: Ilyas Mohammed
  • Patent number: 9929130
    Abstract: An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 27, 2018
    Assignee: Dialog Semiconductor GmbH
    Inventor: Ian Kent
  • Patent number: 9780054
    Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Javier Soto Gonzalez, Nicholas R. Watts, Ravi K Nalla
  • Patent number: 9761570
    Abstract: A method for making an electronic component package from an encapsulated panel. The encapsulated panel includes two packaging substrate assembles including electronic components. Access sides of the electronic components face outward from the encapsulated panel. Standoffs separate the packaging substrate assemblies from each other.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 12, 2017
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Jason R. Wright
  • Patent number: 9741645
    Abstract: Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method of fabricating a semiconductor structure includes forming an insulative material stack above a plurality of solder bump landing pads. The solder bump landing pads are above an active side of a semiconductor die. A plurality of trenches is formed in the insulative material stack by laser ablation to expose a corresponding portion of each of the plurality of solder bump landing pads. A solder bump is formed in each of the plurality of trenches. A portion of the insulative material stack is then removed.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventor: Chuan Hu
  • Patent number: 9685495
    Abstract: A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.
    Type: Grant
    Filed: March 18, 2012
    Date of Patent: June 20, 2017
    Assignee: STATS ChipPAC, Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 9686854
    Abstract: In an electronic device, a heat generating element is connected directly to an electrically-conductive joining material that is the start point of the heat dissipation path on the one surface of the substrate, and the other surface of the substrate is provided by an other surface side insulating layer. An electrically-conductive other surface side electrode connected to an external heat dissipation member is disposed on the surface of the other surface side insulating layer right under the heat generating element. On the other surface side of the substrate, an other surface side inner layer wire that is the end point of the heat dissipation path extends to the other surface side insulating layer and is insulated electrically from the other surface side electrode through the other surface side insulating layer.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: June 20, 2017
    Assignee: DENSO CORPORATION
    Inventors: Yuuki Sanada, Norihisa Imaizumi, Shinya Uchibori, Masaji Imada, Toshihiro Nakamura, Eiji Yabuta, Masayuki Takenaka
  • Patent number: 9679882
    Abstract: A method of multi-chip wafer level packaging comprises attaching a first semiconductor die to a top side of a wafer, forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer, forming a first group of through assembly vias in the first photo-sensitive material layer, attaching a second semiconductor die to the first photo-sensitive material layer, forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer and forming a second group of through assembly vias in the second photo-sensitive material layer.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chun Hui Yu, Chen-Hua Yu, Da-Yuan Shih
  • Patent number: 9659881
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar, wherein the elastic modulus of the substrate is of about 3 to about 10 GPa at about 20 to about 30° C. and of about 1 to about 5 GPa at about 250 to about 270° C.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiun Yi Wu, Yu-Min Liang
  • Patent number: 9636771
    Abstract: The invention relates to an electromagnetic pulse-welding device for joining a metal sheet to a metal part, consisting of an electric energy source which is connected to a coil by means of a current conductor, the active part of said coil being in the direct proximity of the metal sheet, said metal sheet being at a distance from the metal part. The passive part of the coil has a larger cross-section than the active part and said active part borders on one part of the surface in a positive fit, to a cooling insulator, the material having a relatively high thermal conductivity and a relatively low magnetic and electric conductivity compared to the material of the coil.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: May 2, 2017
    Assignee: PST Products GmbH
    Inventor: Pablo Pasquale
  • Patent number: 9633937
    Abstract: The electronic package includes a substrate and an electronic component mounted to a surface of the substrate. An interposer is mounted to the surface of the substrate such that the interposer surrounds the electronic component and is electrically connected to the substrate. An over-mold covers the electronic component. In other forms, the example electronic package may be incorporated into an electronic assembly. The electronic assembly further includes a second electronic component mounted to the interposer. As an example, the second electronic component may be mounted to the interposer using solder bumps. It should be noted that any technique that is known now, or discovered in the future, may be used to mount the second electronic component to the interposer.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Huiyang Fei, Prasanna Raghavan
  • Patent number: 9550670
    Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: January 24, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Christian Geissler, Thorsten Meyer, Gerald Ofner, Reinhard Mahnkopf, Andreas Augustin, Christian Mueller
  • Patent number: 9524955
    Abstract: A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: December 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
  • Patent number: 9490224
    Abstract: A resin sealed semiconductor device includes a semiconductor element having a plurality of metal plated plastic particle core or metal particle core micro-balls including an internal terminal surface and an external connection electrode. Metal wires electrically connect the semiconductor element to the internal terminal and are bonded to the internal terminal surface by a wire bond connection coupling the metal wire to the metal plating, where the metal wire and the metal plating are different materials. A sealing body seals the semiconductor element, a part of each the plurality of the terminals, and the metal wires, where a back surface of the semiconductor element is exposed by the sealing body, and a part of each the plurality of micro-balls project from a bottom surface of the sealing body to provide the external connection electrodes.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 8, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Noriyuki Kimura
  • Patent number: 9484282
    Abstract: There is provided a resin-sealed semiconductor device (BGA type semiconductor device) whose heat dissipating characteristic is improved, so that it is prevented from deteriorating in reliability. This BGA type semiconductor device includes a wiring substrate on a predetermined area on which a semiconductor chip is mounted; a plurality of metal bumps that are formed to be arranged at predetermined intervals in an area of the substrate different from the area on which the semiconductor chip is mounted; and a sealing resin layer that covers at least the semiconductor chip. Each of the plurality of metal bumps is covered with the sealing resin layer described above, with a part thereof exposed at a top face of the sealing resin layer.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: November 1, 2016
    Assignee: Rohm Co., Ltd.
    Inventor: Shoji Yasunaga
  • Patent number: 9474160
    Abstract: Printed circuit board apparatus with electromagnetic interference shields and methods of making the same.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 18, 2016
    Assignee: Advanced Bionics AG
    Inventor: Logan Peter Palmer
  • Patent number: 9431318
    Abstract: In an electronic device, a one-side heat radiation element and a two-side heat radiation element are disposed on a surface of a substrate adjacent to a heat sink. The one-side heat radiation element has a rear-side covered conductive portion and a rear-surface molded portion on the rear-side covered conductive portion adjacent to the heat sink, and radiates heat to the substrate. A surface of a rear-side exposed conductive portion of the two-side heat radiation element adjacent to the heat sink is exposed and the two-side heat radiation element radiates heat to the substrate and the heat sink. The rear-surface molded portion controls a limit position of the one-side heat radiation element toward the heat sink due to deformation of the substrate. A heat radiation gel is filled in between the rear-side exposed conductive portion and the heat sink to radiate heat from the two-side heat radiation element toward the heat sink.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: August 30, 2016
    Assignee: DENSO CORPORATION
    Inventor: Seiji Morino
  • Patent number: 9379096
    Abstract: A semiconductor device includes a plurality of semiconductor elements; first semiconductor chips including first semiconductor elements, the first semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements and having a current flowing greater than that of the other semiconductor elements; second semiconductor chips having second semiconductor elements, the second semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements for controlling the first semiconductor elements; an insulating substrate having a first wiring pattern bonded with the first semiconductor chips; and an insulating member having a second wiring pattern mounted with the second semiconductor chips.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: June 28, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toshio Denta, Tomonori Seki, Tadanori Yamada, Tadahiko Sato
  • Patent number: 9368414
    Abstract: A method of manufacturing a semiconductor device includes: preparing a semiconductor device comprising a first substrate, a second substrate disposed on the first substrate, inner terminals disposed between the first and second substrates, and a filling material disposed between the first and second substrates and between the inner terminals; loading the semiconductor device on a stage; irradiating an electromagnetic wave to the filling material in a direction parallel to a top surface of the first substrate by an electromagnetic wave generating unit; and scanning the filling material as the electromagnetic wave generating unit is moved in relation to the stage in a direction along a first side of the semiconductor device while maintaining the irradiating direction of the electromagnetic wave.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: June 14, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hyeon Baek, Jaehong Kim
  • Patent number: 9365415
    Abstract: An electronic device may include first and second laterally spaced apart interconnect substrates defining a slotted opening, and a first IC in the slotted opening and electrically coupled to one or more of the first and second interconnect substrates. The electronic device may include a first other IC over the first IC and electrically coupled to one or more of the first and second interconnect substrates, and encapsulation material over the first and second interconnect substrates, the first IC, and the first other IC.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: June 14, 2016
    Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD
    Inventor: Jing-En Luan
  • Patent number: 9320139
    Abstract: A circuit board having an interior space includes a multi-layer structure and a compartmentalized frame embedded in the multi-layer structure. The multi-layer structure has a plurality of plates stacked along a stacking direction and a gel combining any two adjacent plates. The plates include two outer plates and at least one inner plate arranged between the outer plates. The compartmentalized frame defines a predetermined space. The compartmentalized frame is arranged between the outer plates and substantially abuts the outer plates. The compartmentalized frame is arranged in a path of a flowing direction of gel which flows toward the predetermined space to prevent any gel from flowing into the predetermined space. Thus, the circuit board of the instant disclosure is provided with the interior space accurately formed by embedding the compartmentalized frame.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: April 19, 2016
    Assignee: BOARDTEK ELECTRONICS CORPORATION
    Inventor: Chien-Cheng Lee
  • Patent number: 9196356
    Abstract: A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 24, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yang Hong, Yong Wee Francis Poh, Tze Ho Simon Chan
  • Patent number: 9184067
    Abstract: Semiconductor packages with multiple substrates can incorporate apertures or slots between devices to minimize or reduce formation of defects during a molding process. The apertures or slots can be formed adjacent a top substrate in alignment with removable regions adjacent a bottom substrate whereby the apertures or slots can facilitate outflow of materials from cavities between the substrates. The apertures or slots may subsequently be removed in conjunction with the removable regions during a singulation process thereby producing the desired semiconductor packages with improved device reliability and yield.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 10, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: KyungHwan Kim, DeokKyung Yang, SeongHun Mun, KeoChang Lee
  • Patent number: 9177907
    Abstract: A method of manufacturing an integrated circuit device includes providing a substrate; forming at least one cavity in the substrate; positioning a die within the at least one cavity of the substrate; and depositing a die attach material around the die within the at least one cavity to mechanically bond the die to the substrate.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: November 3, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Nathan P. Lower, Ross K. Wilcoxon, Nathaniel P. Wyckoff
  • Patent number: 9172020
    Abstract: The present invention provides a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is disposed, and a package body having a cavity and supporting the lead frame. The chip area is exposed through the cavity. The lead frame includes a first terminal group disposed at a first side of the chip area and a second terminal group disposed at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal connected to the chip area and a second terminal separated from the chip area. The second terminal of the first terminal group is exposed through the cavity, and the second terminal of the second terminal group is buried in the package body.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 27, 2015
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Byoung Sung Kim, Sang Eun Lim, Jae Jin Lee, Yeoun Chul Son
  • Patent number: 9150406
    Abstract: An integrated multi-axis mechanical device and integrated circuit system. The integrated system can include a silicon substrate layer, a CMOS device region, four or more mechanical devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, on which any number of CMOS and mechanical devices can be configured. The mechanical devices can include MEMS devices configured for multiple axes or for at least a first direction. The CMOS layer can be deposited on the silicon substrate and can include any number of metal layers and can be provided on any type of design rule. The integrated MEMS devices can include, but not exclusively, any combination of the following types of sensors: magnetic, pressure, humidity, temperature, chemical, biological, or inertial. Furthermore, the overlying WLP layer can be configured to hermetically seal any number of these integrated devices.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: October 6, 2015
    Assignee: mCube Inc.
    Inventor: Xiao (Charles) Yang
  • Patent number: 9153519
    Abstract: A semiconductor device has a connection structure in which a power semiconductor chip is mounted on an insulating substrate having conductor patterns bonded to front and rear surfaces thereof and the insulating substrate is bonded to a heat-dissipating base member to dissipate heat generated from the power semiconductor chip to outside. The conductor pattern bonded to the heat-dissipating base member is formed such that a thickness of a circumferential portion of a bonding surface of the conductor pattern bonded to the insulating substrate is less than that of a center of the bonding portion.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: October 6, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Fumio Nagaune
  • Patent number: 9136292
    Abstract: An electronic package includes a substrate wafer having front and rear faces. An emitting integrated circuit chip is mounted to the front face of the substrate wafer and includes a light radiation optical emitter. A receiving integrated circuit chip is also mounted to the front face of the substrate wafer and includes at least one light radiation optical sensor. A transparent encapsulant extends above the optical sensor and the optical emitter. An opaque encapsulant encapsulates the transparent encapsulant. The opaque encapsulant has a front window situated above the optical emitter and which is offset laterally relative to the optical sensor. The transparent encapsulant accordingly has an uncovered front face situated above the optical emitter and offset laterally relative to the optical sensor. The opaque encapsulant may include an additional front window. The receiving integrated circuit chip further includes a second optical sensor situated opposite the additional front window.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: September 15, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac
  • Patent number: 9105523
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaya Kadono, Shunpei Yamazaki, Yukio Yamauchi, Hidehito Kitakado
  • Patent number: 9076985
    Abstract: A display device which can be produced at reduced material cost and has a smaller peripheral frame area, and a method for producing the same, are provided. A display device includes a first substrate including a display area, which includes an organic EL light emitting layer; a second substrate located so as to face the first substrate; a dam member located along, and outside with respect to, a part of an outer edge of the display area, the dam member joining the first substrate and the second substrate to each other; and a filler filling a space between the first substrate and the second substrate while being in contact with the dam member.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: July 7, 2015
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hirotsugu Sakamoto, Hiroshi Oooka, Takeshi Ookawara, Kouhei Takahashi, Yuko Matsumoto
  • Patent number: 9064737
    Abstract: A power semiconductor module includes at least two power semiconductor units that are interconnected and that have controllable semiconductors. Each semiconductor unit is associated with a cooling plate to which the semiconductors are connected in a heat-conducting manner. The object is to provide a semiconductor module that is compact and cost-effective and at the same time explosion-proof. The power semiconductor module of the invention has a module housing which houses the power semiconductor units. The cooling plates form at least part of the module housing.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: June 23, 2015
    Assignee: Siemens Aktiengesellschaft
    Inventors: Joerg Dorn, Thomas Kuebel
  • Patent number: 9056763
    Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 16, 2015
    Assignee: Intel Corporation
    Inventors: Christian Geissler, Thorsten Meyer, Gerald Ofner, Reinhard Mahnkopf, Andreas Augustin, Christian Mueller
  • Patent number: 9041211
    Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface, a wiring layer formed on the first surface of the first sealing insulating layer, an insulating layer formed on the wiring layer, a second semiconductor chip mounted on the second surface of the first sealing insulating layer, and a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 26, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kenta Uchiyama