Abstract: A printed wiring board according to an embodiment includes a metal plate and a wiring member. The meal plate includes a current path part, which is a main current path of an electronic part mounted on or above a front surface of the metal plate, and a heat radiation part, which radiates heat generated from the electronic part. The wiring member is arranged on or above a back surface of the metal plate. The current path part and the heat radiation part are in the same layer to be integrally formed with the wiring member.

Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

Abstract: A method of manufacturing a circuit board includes: a single-sided copper-clad base is provided; a plurality of grooves are defined in the base facing away from the copper-clad side for receiving electronic elements, a depth of each of the grooves is equal to a thickness of the corresponding electronic element; the electronic elements are fixed into their respective grooves; a plurality of holes are defined in the laminating member to expose the electrodes of the electronic elements; an electroplated layer is formed on the surface of the embedded body, the electroplated layer is electrically connected with the electrodes of the electronic elements. A circuit board made by the method is also provided.

Abstract: A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies. The annular lower lid includes a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening. The semiconductor device assembly further includes a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts. The semiconductor device assembly further includes the upper lid disposed over the annular lower lid and the stack of semiconductor dies.

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

Abstract: Forming a groove in a dicing region so as to expose a conductive pattern material on a side surface, closer to a first side of each of mounting regions, of a substrate; when forming a first sealing portion enclosing a wireless region and a second sealing portion enclosing an antenna region adjacent to the wireless region on a side of a second side of each of the mounting regions, reducing a thickness in a height direction such that a thickness of the second sealing portion becomes smaller in thickness than a thickness of the first sealing portion; forming a shielding film such that a scattered matter made of a conductive material is allowed to pass through an upper surface of the second sealing portion, to be deposited onto the conductive pattern material exposed on a side surface of the substrate; and separating the substrate into the mounting regions individually.

Abstract: On a conductive plate of an insulated substrate, one open end of a main body part of a cylindrical contact member is bonded by solder. In a hollow part of a hollow cylinder shaped external electrode terminal, a part of the other open end side of the main body part of the cylindrical contact member is inserted from an open end of the external electrode terminal. The other end of the external electrode terminal is separated into branches by cuts inserted in a through-hole insertion part. A column surface of the outside of the branches of the external electrode terminal has an arc shape. Pressure in a direction from inside the external electrode terminal toward the outside is applied to the branches of the through-hole insertion part by an auxiliary wedge. With such a configuration, assembly defects accompanying connection of the external electrode terminal and other members may be eliminated.

Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

Abstract: A package structure including an integrated fan-out package and plurality of conductive terminals is provided. The integrated fan-out package includes an integrated circuit component, a plurality of conductive through vias, an insulating encapsulation having a first surface and a second surface opposite to the first surface, and a redistribution circuit structure. The insulating encapsulation laterally encapsulates the conductive through vias and the integrated circuit component. Each of conductive through vias includes a protruding portion accessibly revealed by the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit component and covers the first surface of the insulating encapsulation and the integrated circuit component.

Abstract: A method of tuning inductive and/or capacitive components within an integrated circuit device. The method comprises measuring bare-die mounted performance of such a component formed within a semiconductor die, determining a package distribution layer pattern for the at least one component for achieving a desired performance for the at least one component based at least partly on the measured bare-die mounted performance, and packaging the semiconductor die with the determined package distribution layer pattern for the at least one component.

Abstract: The present disclosure proposes a packaging structure for a metallic bonding based opto-electronic device and a manufacturing method thereof. According to the embodiments, the packaging structure for an opto-electronic device may comprise an opto-electronic chip and a packaging base. The opto-electronic chip comprises: a substrate having a first substrate surface and a second substrate surface opposite to each other; an opto-electronic device formed on the substrate; and electrodes for the opto-electronic device which are formed on the first substrate surface. The packaging base has a first base surface and a second base surface opposite to each other, and comprises conductive channels extending from the first base surface to the second base surface.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

Abstract: Provided is a mounting structure that can bond a first heat dissipation element to a second substrate through a hole in a first substrate without using a binder such as solder, an adhesive, or the like. A mounting structure of the present disclosure includes a first substrate (10) in which a penetrating hole (11) is formed, a second substrate (20) and a first heat dissipation element (30) overlapped with both surfaces of the first substrate (10), respectively, so as to cover the penetrating hole (11), and a second heat dissipation element (40) sandwiched and attached between the second substrate (20) and the first heat dissipation element (30) inside the penetrating hole (11).

Abstract: Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip including a plurality of first contact pads, the plurality of first contact pads facing the RDL; a second chip disposed between the first chip and the redistribution layer (RDL) wherein a portion of the first chip is disposed outside a lateral extent of the second chip; and a conductive via laterally separated from the second chip, the conductive via extending between the RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the second chip.

Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.

Abstract: The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.

Abstract: A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

Abstract: The present invention discloses a wireless package with a resilient connector for connecting a substrate to an antenna. The antenna is disposed directly on a top surface of a molding compound of the wireless package. The resilient connector has a lower terminal bonded to the substrate, a horizontal contact portion, and an oblique support portion integrally extending between the horizontal contact portion and the lower terminal. The horizontal contact portion has a flat top surface that is coplanar with the top surface of the molding compound and is in direct contact with the antenna such that the contact resistance distribution is concentrated and the production yield of the wireless package is improved.

Abstract: A power module includes an insulated circuit board, a semiconductor element, a first buffer plate, and first and second joining materials. The semiconductor element is disposed on a side of one main surface of the insulated circuit board. The first buffer plate is disposed between the insulated circuit board and the semiconductor element. The first joining material is divided into a plurality of portions in a plan view. The first buffer plate is higher in coefficient of linear expansion than the semiconductor element and lower in coefficient of linear expansion than the insulated circuit board. The first buffer plate is lower in Young's modulus than the semiconductor element.

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

Abstract: The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.

Abstract: The present invention discloses a power semiconductor module, comprising: a substrate; a semiconductor provided on a top side of the substrate; and a package formed on the semiconductor and the substrate, wherein the package has openings at a top side thereof, through which terminal contacts of the semiconductor and the substrate are exposed outside and accessible from outside.

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer.

Abstract: A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.

Abstract: The invention provides a semiconductor package and a method for fabricating the same. The semiconductor package includes a redistribution layer (RDL) structure, a semiconductor die, a molding compound and a supporter. The RDL structure has a first surface and a second surface opposite to the first surface. The semiconductor die is disposed on the first surface of the RDL structure and electrically coupled to the RDL structure. The molding compound is positioned overlying the semiconductor die and the first surface of the RDL structure. The supporter is positioned beside the semiconductor die and in contact with the first surface of the RDL structure.

Abstract: An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed on a part of the substrate, and includes a catalyst layer covering the part of the substrate, and a conducting layer formed on the catalyst layer. The reflecting layer is formed on another part of the substrate that is exposed from the wiring structure. The light-emitting diodes are disposed on the wiring structure and are electrically connected to the wiring structure.

Abstract: Embodiments relate to a light emitting structure including a light emitting diode, a first contact, and a second contact. The light emitting diode includes a body of transparent semiconductor material with a top surface and a light emitting region below the top surface. The light emitting region emits light in response to current passing through the light emitting region; the emitted light passes through the body of the light emitting diode. The first contact is connected to the top surface of the body and has a spiral shape to induce an electromagnetic field. The electromagnetic field shapes the light emitted from the light emitting region and passes through the body of the light emitting diode. The second contact is connected to a surface of the light emitting structure. A voltage difference can be applied across the first contact and second contact to generate the current through the light emitting region.

Abstract: In a semiconductor device, an outer peripheral case body has guiding portions formed therein as a plurality of recesses. The plurality of guiding portions each include an upper end opening. The outer peripheral case body has inner peripheral side openings formed in its inner peripheral surface, each of which is continuous with the upper end opening, extends from an upper end face toward a base body and is continuous with the guiding portion. The first insertion portion is inserted into a first guiding portion of the plurality of guiding portions. The first external terminal portion is continuous with the first insertion portion and extends through the upper end opening in the first guiding portion to outside of the outer peripheral case body. The first connection terminal portion is continuous with the first insertion portion and connected to a conductive pattern through the inner peripheral side opening.

Abstract: The semiconductor device has a first external electrode having an outer peripheral section, which has a circular shape in top plan view and which is to be attached to an alternator. On the first external electrode there mounted: a MOSFET chip; a control circuitry to which voltages at or a current flowing between a first main terminal and a second main terminal of the MOSFET chip is inputted and which generates, on the basis of the voltages or the current, a control signal applied to a gate of the MOSFET chip; and a capacitor for providing a power supply to the control circuitry. The semiconductor device further has a second external electrode disposed opposite to the first external electrode with respect to the MOSFET chip. An electrical connection is made between the first main terminal of the MOSFET chip and the first external electrode, and between the second main terminal of the MOSFET chip and the second external electrode.

Abstract: A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer. An insulating layer is deposited over the first conductive layer and second conductive layer. A third conductive layer includes a first portion of the third conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer. An electrical component is disposed over the first conductive layer and second conductive layer. An encapsulant is deposited over the first conductive layer, second conductive layer, and electrical component. A cut is made through the encapsulant, first conductive layer, and second conductive layer. A fourth conductive layer is deposited over side surfaces of the first conductive layer, second conductive layer, and encapsulant.

Abstract: A semiconductor module includes a die pad area between positions where a plurality of power terminals are arranged and positions where an HVIC and an LVIC are arranged. A plurality of RC-IGBTs are arranged in the die pad area at positions closer to the plurality of power terminals than to the HVIC and the LVIC.

Abstract: An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component.

Abstract: According to one embodiment, an electronic device includes a substrate including a first face, a plurality of first conductors on the first face, a plurality of second conductors on the first face, and a first electronic component mounted on the first face, and including a first terminal connected to the plurality of first conductors, and a second terminal connected to the plurality of second conductors.

Abstract: A semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the bottom portion; and a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad, wherein: the first terminal portion is provided with a first plate-shaped portion; the second terminal portion is provided with a second plate-shaped portion; and each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad.

Abstract: A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.

Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The Wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

Abstract: A multilayered printed circuit board (PCB) may include a plurality of pads associated with facilitating a connection to a component. The component may include a first edge and a second edge. The plurality of pads may include a first pad, located between a second pad and the first edge. The PCB may include a plurality of vertically disposed vias electrically connected to the plurality of pads and a plurality of horizontally disposed signal layers, electrically connected by the plurality of vias, to route a set of signals toward the first edge. The set of signals may include a first signal that is routed by a first via, of the plurality of vias, and a first signal layer of the plurality of signal layers and a second signal that is routed by a second via, of the plurality of vias, and a second signal layer of the plurality of signal layers.

Abstract: A method of assembling QFP devices includes providing a lead frame having leads that extend from a dam bar to a die flag, and performing a first molding process that fills spaces between the leads and between the dam bar and the die flag with a first mold compound. The first mold compound also forms a ring around the die flag, where the ring extends from both lateral sides of the lead frame. A first area around the die flag is removed to separate the leads from the die flag, and a second area near an inner corner of the dam bar is removed to form a mold gate. A die is attached to the die flag and electrically connected to the leads with bond wires, and then a second molding process is performed to encapsulate the die, bond wires and inner leads.

Abstract: A light emitting device includes a first substrate, a second substrate and a plurality of micro epitaxial structures. The second substrate is disposed opposite to the first substrate. The micro epitaxial structures are periodically disposed on the substrate and located between the first substrate and the second substrate. A coefficient of thermal expansion of the first substrate is CTE1, a coefficient of thermal expansion of the second substrate is CTE2, a side length of each of the micro epitaxial structures is W, W is in the range between 1 micrometer and 100 micrometers, and a pitch of any two adjacent micro epitaxial structures is P, wherein W/P=0.1 to 0.95, and CTE2/CTE1=0.8 to 1.2.

Abstract: A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.

Abstract: Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally adjacent to a stack of dies positioned on the first die. The stack of dies electrically couples the first die to an uppermost die, and a thermally conductive pillar extends through the molding compound from the first die to an upper surface of the molding compound. The thermally conductive pillar is electrically isolated from the stack of dies and the uppermost die. The thermally conductive pillar laterally abuts and contacts the molding compound.

Abstract: A two-stage singulation process is used in the fabrication of phosphor coated light emitting elements. Prior to the application of the phosphor coating, the individual light emitting elements are singulated using a laser dicing process (130); after application of the phosphor coating (150), the phosphor coated light emitting elements are singulated using a mechanical dicing process (180). Before laser dicing of the light emitting elements, the wafer is positioned on a piece of dicing- or die-attach-tape held by a frame; after laser dicing, the tape is stretched (140) to provide space between the individual light emitting elements that allows for the wider kerf width of the subsequent mechanical dicing (180) after application of the phosphor coating (150).

Abstract: A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. The second ground layer is electrically connected to the first ground layer through one of the solder balls.

Abstract: A heat transfer cooling module is described. One embodiment of the module has a plate attached to a bracket. A tower is affixed the plate. One end of the tower can be in contact with the heat source. The opposite end of the tower has a radiator attached which dissipates the heat that travels from the first end of the tower to the opposite end of the tower. Both the tower and the radiator are made from efficient materials for the transfer of heat. Another embodiment of the heat transfer cooling module is shown where the device is in two pieces, the first a fin module affixed to a bracket. The heat source is in contact with a base of the fin module where the heat travels through the base, to the fins where it dissipates to ambient.

Abstract: A semiconductor device includes a terminal, a first semiconductor chip, a second semiconductor chip located on the first semiconductor chip, a first pad located on the first semiconductor chip and electrically disconnected from a semiconductor circuit of the first semiconductor chip, a second pad located on the second semiconductor chip and electrically connected to a semiconductor circuit of the second semiconductor chip, a first wire electrically connecting the first terminal to the first pad, and a second wire electrically connecting the first pad to the second pad.

Abstract: Provided is a power converter which is applied to a power converter equipped with a switching element provided on a line, and a radiator connected to a predetermined potential such as a ground potential. A noise eliminator in which a conductive member is covered with insulator is provided between the switching element (semiconductor switch) and the radiator (heatsink). A flexible connecting line connected to a conductive member of the noise eliminator is connected to an on-board line disposed on a circuit board.

Abstract: An electronic component mounting board reduces shadows produced along its perimeter to improve the mountability of an electronic device and an electronic module. An electronic component mounting board (1) includes a substrate (2a) including a mount area (4) in which an electronic component (10) is mountable. The substrate (2a) includes electrode pads located at ends of the mount area (4) as viewed from above. The electronic component mounting board (1) includes a frame (2b) located outside the electrode pads (3) on the upper surface of the substrate (2a). The frame (2b) includes at least one side surface that slopes from an upper end to a lower end of the frame (2b), and flares from the upper end to the lower end as viewed from above.