Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate, an electrical component disposed on the first substrate, a second substrate disposed over the electrical component, an adhesive layer, a spacer, and an encapsulation layer. The adhesive layer is disposed between the electrical component and the second substrate. The spacer directly contacts both the adhesive layer and the second substrate. The encapsulation layer is disposed between the first substrate and the second substrate.

Abstract: In a method of manufacturing an embedded magnetic component, a cavity is formed in an insulating substrate. One or more drops of adhesive are applied to the cavity and a magnetic core is inserted in the cavity. The cavity and the magnetic core are then covered with a first insulating layer. Through holes are formed through the first insulating layer and the insulating substrate, and plated up to form conductive vias. Metallic traces are added to exterior surfaces of the first insulating layer and the insulating substrate to form upper and lower winding layers. The metallic traces and the conductive vias form the windings for an embedded magnetic component, such as a transformer or an inductor.

Abstract: A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

Abstract: A semiconductor device includes a semiconductor element, a circuit board, metal wires, and an expanding member. The circuit board has an upper surface and a lower surface opposite the upper surface. The metal wires are formed on at least one of the upper surface and the lower surface. At least two connection terminals are formed in a terminal formation surface of the semiconductor element which is disposed so as to face the upper surface of the circuit board. The expanding member is fixed to the terminal formation surface of the semiconductor element, has a larger coefficient of linear thermal expansion than the semiconductor element, and has a size larger than the interval between adjacent two of the at least two connection terminals.

Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

Abstract: A semiconductor device includes an insulating substrate having a metal plate, an insulating resin plate, and a circuit plate laminated in order; a semiconductor element fixed to the circuit plate; a wiring member connected to an electrode disposed on a front surface of the semiconductor element or to the circuit plate of the insulating substrate; a housing accommodating the insulating substrate, the semiconductor element, and the wiring member; and a sealing material including a thermosetting resin, and sealing the insulating substrate, the semiconductor element, and the wiring member accommodated in the housing. The circuit plate of the insulating substrate is selectively formed on the insulating resin plate as a combination of a circuit pattern with a sealing material adhering pattern.

Abstract: In a manufacturing method for a thermistor element (3) including: a thermistor portion (49) which is a sintered body formed from a thermistor material; and a pair of electrode wires (25) which are embedded in the thermistor portion (49) and at least one end portion of each of the electrode wires projects at an outer side of the thermistor portion (49), the resistance value of the thermistor element (3) is adjusted by performing a removal processing of removing a part of the thermistor portion (49).

Abstract: A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate.

Abstract: A semiconductor package and manufacturing method thereof includes a chip member installed on an upper surface, a lower surface, or both of a substrate. The semiconductor package and manufacturing method thereof also include a mold part stacked embedding the chip member, a connection member disposed at a center portion of the mold part, and a solder part formed on a portion of the connection member.

Abstract: The present disclosure provides a semiconductor structure, including a first silicon layer having a through silicon via (TSV), a III-V structure over the first silicon layer, electrically coupling to the TSV, and a redistribution layer (RDL) under the first silicon layer, electrically coupling to the TSV. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes providing a III-V-on-Si structure, comprising a III-V device over a silicon layer, forming a through silicon via (TSV) in the silicon layer, electrically coupling to the III-V device, and forming a redistribution layer (RDL) over a side of the silicon layer opposite to the III-V device.

Abstract: A MEMS sensor according to the present invention includes a base substrate including a displaceably supported movable portion and a lid substrate covering the movable portion and functioning as a magnetic sensor that detects magnetism by making use of the Hall effect.

Abstract: A semiconductor device includes a semiconductor substrate, a conductor provided on a main surface of the semiconductor substrate, an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor, and an external connection terminal connected to the portion of the conductor exposed from the opening. In a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract: In an embodiment, photoelectric conversion units (10) each include a package (12) accommodating a photoelectric conversion device (11). The package (12) has a front surface (12a) having a window (13); and a side surface (12c). The package (12) includes a first coupling portion (14) protruding from the side surface (12c) in a first direction X parallel to a light incident surface (11a) of the photoelectric conversion device (11), and a second coupling portion (15) recessed from the side surface (12c) in the first direction X. The first coupling portion (14) includes a first terminal (16) electrically connected with the photoelectric conversion device (11), and the second coupling portion (15) includes a second terminal (17) electrically connected with the photoelectric conversion device (11). The first coupling portion (14) and the second coupling portion (15) have shapes and sizes matching each other, and are coupled with each other by fitting.

Abstract: An inverter circuit board to which a P-N terminal is attached such that stress applied to the circuit board can be distributed, making it possible to prevent detachment of the P-N terminal or damage to the circuit board or any components mounted thereon. Also provided is an inverter-containing electric compressor. A P-N terminal via which DC power is inputted is attached to this inverter circuit board, on which an inverter circuit is mounted. The P-N terminal is provided with the following: a pair of pins; a busbar of a prescribed length joined perpendicularly to one end of each pin; a resin molded member formed integrally with the pair of pins and the busbars; and surface-mounting terminals, soldered to the surface of the circuit board, and through-hole terminals, inserted into and soldered to through-holes in the circuit board, said terminals being provided on the pair of busbars.

Abstract: A semiconductor device includes a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode, and a second semiconductor chip having a third surface facing the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface and a third electrode on the fourth surface. The semiconductor device further includes a metal wire electrically connecting the first and third electrodes, a first insulating layer on the second surface, a first conductive layer that is on the first insulating layer and electrically connected to the second electrode, and a first external terminal electrically connected to the first conductive layer.

Abstract: Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

Abstract: A light emitting package includes a first lead frame; a second lead frame spaced apart from the first lead frame in a first direction; a body coupled to the first lead frame and the second lead frame; and a light emitting element on the first lead frame. The first lead frame includes first to fourth side parts, the first side part includes a first protrusion that protrudes outwards from one side surface of the body, and a first contact part disposed at the end of the first protrusion. The second lead frame includes fifth to eighth side parts, the fifth side part includes a second protrusion that protrudes outwards from a side surface of the body, which is symmetrical to the one side surface of the body, and a second contact part disposed at the end of the second protrusion. Each of the first contact part and the second contact part includes a second layer and first layer covers the second layer.

Abstract: A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.

Abstract: A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.

Abstract: An electrical contactor assembly is provided including: an electrical contactor; an electrical bus bar; a panel; at least one post protruding through the panel and in contact with the electrical bus bar, the post being constructed from an electrically and thermally conductive material, wherein a first end of the at least one post is configured to electrically and thermally connect to the electrical contactor; and a liquid cooled heat sink thermally connected to a second end of the at least one post through the electrical bus bar, wherein the liquid cooled heat sink in operation circulates liquid coolant through the liquid cooled heat sink to absorb heat.

Abstract: Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.

Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

Abstract: A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a second printed circuit board are provided. The first surface mounting unit includes a first chip and a first conductive frame, and the first conductive frame has a first carrier board and a first metal member connected to the first carrier board. A first side of the first chip is electrically connected to the first carrier board of the first conductive frame. A second side of the first chip and the first metal member are connected to the first circuit board by a first pad and a second pad respectively. The second circuit board is connected to the first carrier board and hence, the first surface mounting unit is located between the first circuit board and the second circuit board.

Abstract: A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a wide band-gap switch, a base plate, and a press device. The insulated gate bipolar transistor and the wide band-gap switch are connected in parallel and are each mounted with a first planar terminal to a side of the base plate. Further, a second planar terminal of the insulated gate bipolar transistor and a second planar terminal of the wind band-gap switch are connected with an electrically conductive connection element, and the press device is arranged on the second planar terminal of the insulated gate bipolar transistor. Hence, when arranging the semiconductor modules in a stack arrangement, any press force is primarily applied to the insulated gate bipolar transistors of the semiconductor modules.

Abstract: A semiconductor device manufacturing method is provided. In a semiconductor wafer prepared, the width of a dicing line is larger than a cut region to be diced with a dicing blade, a first chip forming region and a second chip forming region are adjacent and have the dicing line therebetween, some of the pads are formed on a first chip forming region side, and the remaining pads are formed on a second chip forming region side. The semiconductor wafer is diced with the dicing blade in such manner that, when the some of the pads are diced, a part of the dicing blade on the second chip forming region side does not abut the some of the pads, and, when the remaining pads are diced, a part of the dicing blade on the first one chip forming region side does not abut the remaining pads.

Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

Abstract: A first conductive pattern includes: a first feeding point for supplying a potential to the first conductive pattern located at one end thereof; one or more diode elements located over the first conductive pattern; and a plurality of switching elements over the first conductive pattern on the opposite side to the first feeding point with the diode elements in between. A second conductive pattern includes a second feeding point that is provided in proximity to the first feeding point and supplies a potential different from that for the first conductive pattern to the second conductive pattern. The plurality of the switching elements is electrically connected with the second conductive pattern through a plurality of bonding wires. The second conductive pattern is provided with a slit pattern that defines an area of connection of the plurality of the bonding wires with the second conductive pattern over the second conductive pattern.

Abstract: A copper-based alloy wire made of a material selected from the group consisting of a copper-gold alloy, a copper-palladium alloy and a copper-gold-palladium alloy is provided. The alloy wire has a polycrystalline structure of a face-centered cubic lattice and consists of a plurality of equi-axial grains. The quantity of grains having annealing twins is 10 percent or more of the total quantity of the grains of the copper-based alloy wire.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

Abstract: An IC module for installation in a portable data carrier and for electrical connection with an electronic device located in the data carrier supports at least two different connection technologies. It carries for this purpose contacting elements having a first set of contacting pads for a first connection technology and a second set of contacting solder areas for a second connection technology. A contacting pad of the first set of contacting pads in each case is connected electroconductively to a contacting pad of the second set of contacting pads. The connection can preferably be electively effected by a pressure-form technology or by means of connection wires as a soldered connection.

Abstract: A semiconductor component includes an inner semiconductor component housing and an outer semiconductor component housing. The inner semiconductor component housing includes a semiconductor chip, a first plastic housing composition and first housing contact surfaces. At least side faces of the semiconductor chip are embedded in the first plastic housing composition and the first housing contact surfaces are free of the first plastic housing composition and include a first arrangement. The outer semiconductor component housing includes a second plastic housing composition and second housing contact surfaces which include a second arrangement. The inner semiconductor component housing is situated within the outer semiconductor component housing and is embedded in the second plastic housing composition. At least one of the first housing contact surfaces is electrically connected with at least one of the second housing contact surfaces.

Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a substrate; forming an interconnect layer over the substrate; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the semiconductor die being spaced apart from the conductive pillars; and bonding a second semiconductor die with the conductive pillars.

Abstract: An integrated package may be manufactured in a die face up orientation with a component proximate to the attached die by creating a cavity in the mold compound during fabrication. The cavity is created with an adhesive layer on the bottom to hold a component such that the top surface of the component is co-planar with the top surface of the attached die. This may allow backside grinding to take place that will not damage the component because the top surface alignment between the attached die and the component prevents the depth of the cavity from extending into the portion of the package that is ground away.

Abstract: A signal block and a double-faced cooling power module that uses the signal block is provided. The signal block includes a plurality of signal clips that are formed in a ribbon shape to connect a first signal pad formed on a semiconductor chip and a second signal pad formed on a signal lead frame. An insulator fixes the position of the plurality of signal clips while spacing the signal clips apart from each other.

Abstract: A semiconductor device includes a plurality of main terminals extending from one end of a base plate toward the other end thereof, a group of semiconductor chips on a side of higher electric potential disposed on one side of the main terminal and mounted on the base plate, and a group of semiconductor chips on a side of lower electric potential disposed on the other side of the main terminal and mounted on the base plate. The one main terminal has an extending portion extending, in a direction perpendicular to the extending direction of the main terminal, toward one of both sides of the main terminal, and two adjacent semiconductor chips in one of the group of semiconductor chips on the side of higher electric potential and the group of semiconductor chips on the side of lower electric potential are axisymmetrically disposed with respect to the extending portion.

Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

Abstract: Deformable conductive contacts are provided. A plurality of deformable contacts on a first substrate may be joined to a plurality of conductive pads on a second substrate during die level or wafer level assembly of microelectronics. Each deformable contact complies to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. Since an individual contact can make the conductive coupling within a range of distances from a target pad, an array of the deformable contacts provides tolerance and compliance when there is some variation in height of the conductive elements on either side of the join. A flowable underfill may be provided to press the deformable contacts against opposing pads and to permanently join the surfaces at a fixed distance. The deformable contacts may include a wiping feature to clear their target pads for establishing improved metal-to-metal contact or a thermocompression bond.

Abstract: An electrical device for soldering to a circuit board with a solder includes a capacitor, a lead frame including a solder dam, and a solder joint electrically coupling the capacitor to the lead frame. The solder dam includes one of a physical barrier to flow or an area of reduced wettability to the solder. The solder dam is between the solder joint and the circuit board. The solder dam is on one or both of a lead portion and main portion of the lead frame. In one embodiment, the first solder dam extends substantially the full width of the first lead portion. The solder dam may be a barrier and/or include a metal oxide. A method of manufacturing the device includes soldering a lead frame to a capacitor with a solder and modifying a surface on the lead frame to include a physical barrier and/or an area of reduced wettability.

Abstract: A light emitting device includes: a substrate; an electrode pattern formed on the substrate; a light emitting element connected to the electrode pattern; a ridge-shaped resin covering portion which covers a part of the electrode pattern, and which includes a first and second outer edge portions; first and second through holes formed to penetrate through the electrode pattern such that the substrate is exposed; and first and second hole arrays including the first and second through holes arranged along the first and second outer edge portions, respectively. The first and second outer edge portions cover at least a part of the first and second through holes, respectively, and are bonded to the substrate in the first and second through holes, respectively.

Abstract: A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

Abstract: An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first heat exchanger disposed on the primary device and having an opening over an area corresponding to the at least one secondary device; a second heat exchanger disposed in the opening on the at least one secondary device; at least one heat pipe coupled to the first heat exchanger and the second heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including a first portion, a second portion and at least one heat pipe coupled to the first portion and the second portion; and coupling the heat exchanger to the multi-chip package.

Abstract: A semiconductor module includes a rectangular base plate; a substrate which is placed on the base plate and on which a circuit including a semiconductor chip and so forth is formed; a rectangular parallelepiped case made of resin that is attached to the base plate and houses the substrate within; and a plurality of external terminals lower ends of which are fixed to the substrate with upper ends thereof being exposed on a top face of the case. The case is provided with a first case opening portion and a second case opening portion that are respectively formed by cutting off a front face and a rear face of the case from an upper edge thereof along a longitudinal direction thereof; and the top face of the case between the first case opening portion and the second case opening portion includes an external terminal holding portion to hold the plurality of external terminals along the longitudinal direction with the upper ends thereof being exposed.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A multilayered printed circuit board (PCB) may include a plurality of pads associated with facilitating a connection to a component. The component may include a first edge and a second edge. The plurality of pads may include a first pad, located between a second pad and the first edge. The PCB may include a plurality of vertically disposed vias electrically connected to the plurality of pads and a plurality of horizontally disposed signal layers, electrically connected by the plurality of vias, to route a set of signals toward the first edge. The set of signals may include a first signal that is routed by a first via, of the plurality of vias, and a first signal layer of the plurality of signal layers and a second signal that is routed by a second via, of the plurality of vias, and a second signal layer of the plurality of signal layers.

Abstract: An integrated circuit chip attachment in a microstructure device is accomplished through the use of an adhesive-based material in which graphene flakes are incorporated. This results in superior thermal conductivity. The spatial orientation of the graphene flakes is controlled, for example by adhering polar molecules to the graphene flakes and exposing the flakes to an external force field, so that the graphene flakes have desired orientations under the integrated circuit chip, alongside of the integrated circuit chip and above the integrated circuit chip.

Abstract: Electrical components such as integrated circuits and other components may be mounted on a substrate such as a printed circuit substrate. A molded plastic cap may cover the components and a portion of the printed circuit substrate to form a packaged electrical device. Metal structures such as springs, posts, and other metal members may be insert molded within the plastic cap. A metal layer on the surface of the cap may be patterned to from electromagnetic shielding, signal paths, contact pads, sensor electrodes, antennas, and other structures. Multiple substrates each with a respective set of mounted electrical components may be joined using a flexible printed circuit. The flexible printed circuit may be covered with a rigid cap portion or an elastomeric material or may be left uncovered.

Abstract: This invention is provided with: a circuit board which is placed in a package and in which an electric circuit including a power semiconductor element is formed; and a plurality of press-fit terminals each having a wire-bond portion electrically connected in the package to the electric circuit, a press-fit portion for making electrical connection with an apparatus to be connected, and a body portion whose one end portion continuous to the wire bond portion is internally fastened to the package and whose other end portion supports the press-fit portion so as to place the press-fit portion away from the package; wherein in each of the plurality of press-fit terminals, at a portion in the body portion exposed from the package, there is formed a constriction portion that is constricted from both sides in a direction perpendicular to the center line, so as to leave a portion around the center line.