Abstract: The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening.

Abstract: A plate structure having a chip embedded therein, comprises an aluminum plate having at least one aluminum oxide layer formed on its surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and a build-up structure mounted on the surface of the aluminum plate, the active surface of the chip, and the surface of the electrode pad, wherein the build-up structure comprises at least one conducting to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed. Therefore, the plate structure having a chip embedded therein can be processed by a simple method to achieve the tenacity of aluminum and the rigidity of aluminum oxide.

Abstract: A semiconductor device including a package (2) having a plurality of wall portions (9a) and a plurality of conductor portions (4), a semiconductor element such as a solid-state image pickup device (1) mounted in an internal space of the base, thin metal wires (5) electrically connecting the semiconductor element and the conductor portions (4) between the wall portions (9a), a resin sealing material (7) implanted in the spaces between the wall portions (9a), and a closing member such as a cover glass (6). The region for connecting the thin metal wires (5) and the wall portion (9a) region overlap each other, so that the device can be reduced in size and in height. The cover glass (6) can not move easily from the correct position because the wall portions (9a) serve as supporting columns, thereby improving the yield.

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. A relay post is provided on the dielectric plate. The first band-shaped conductor is connected to the circuit pattern by an interconnection via the relay post.

Abstract: A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.

Abstract: To provide an airtight terminal and a piezoelectric vibrator having a strong rigidity of a lead despite a small-sized constitution, and provide a method of fabricating an airtight terminal constituting a lead penetrating inside of a stem by one piece and a piezoelectric vibrator with an excellent yield. A stem 11 filled with a filling member 13 is penetrated only with one piece of a lead 12 formed from a lead frame. As an electric terminal, a conductive lead 16 connected to the stem 11 is provided other than the lead 12. The lead 12 and the conductive lead 16 of an airtight terminal 10 constituted by the stem 11, the lead 12, the filling member 13, the conductive lead 16 are connected to a piezoelectric vibrating piece 20, further, the stem 11 is capped to a case 30 to thereby constitute a piezoelectric vibrator 1.

Abstract: An electrical assembly, comprising a heat producing semiconductor device supported on a first major surface of a direct bond metal substrate that has a set of heat sink protrusions supported by its second major surface. In one preferred embodiment the heat sink protrusions are made of the same metal as is used in the direct bond copper.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: A metallic film and a grounding pattern are surely connected to each other so as to achieve electrical shield of an electronic circuit unit. In an electronic circuit unit, the metallic film is provided on a top surface of a sealing resin portion for burying an electronic component, the side surfaces of the sealing resin portion that are opposite to each other, and the side surfaces of the multi-layered substrate that are opposite to each other. The metallic film is connected to the grounding patterns that are provided on the top surface of the multi-layered substrate or between the laminated layers of the multi-layered substrate. Therefore, it is possible to achieve a superior electrical shielding effect through the metallic film, as compared with the related art. Since the metallic film is formed on the side surfaces of the sealing resin and the side surfaces of the multi-layered substrate, when the metallic film is formed by a plating method, the blind hole may not be provided in the related art.

Abstract: A semiconductor module is disclosed. One embodiment provides a first electrically conductive carrier composed of a first material, a second electrically conductive carrier composed of the first material, an electrically insulating element composed of a second material, which connects the first carrier and the second carrier to one another, a first semiconductor substrate applied to the first carrier, a second semiconductor substrate applied to the second carrier, and an electrically conductive layer applied above the first carrier, the second carrier and the insulating element. The electrically conductive layer electrically conductively connects the first semiconductor substrate to the second semiconductor substrate.

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. A relay post is provided on the dielectric plate. The first band-shaped conductor is connected to the circuit pattern by an interconnection via the relay post.

Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. Third dielectric plates are arranged on the base plate between the band-shaped conductors and the first dielectric plate or the second dielectric plate, having a line conductor pattern formed on their surfaces. The surfaces of the third dielectric plate are arranged at a position lower than the band-shaped conductor and higher than the surface of the first or the second dielectric plate with respect to a main surface of the base plate.

Abstract: A method for fabricating copper-faced electronic modules is described. These modules are mechanically robust, thermally accessible for cooling purposes, and capable of supporting high power circuits, including operation at 10 GHz and above. An imprinting method is described for patterning the copper layers of the interconnection circuit, including a variation of the imprinting method to create a special assembly layer having wells filled with solder. The flip chip assembly method comprising stud bumps inserted into wells enables unlimited rework of defective chips. The methods can be applied to multi chip modules that may be connected to other electronic systems or subsystems using feeds through the copper substrate, using a new type of module access cable, or by wireless means. The top copper plate can be replaced with a chamber containing circulating cooling fluid for aggressive cooling that may be required for servers and supercomputers.

Abstract: A lead frame of a through-hole light emitting diode (LED) is used to carry an LED chip, and a lens is used to package the chip and a portion of the lead frame. The lead frame includes at least two leads. One lead is used to carry the chip and each of the leads is extended outward from the lens and has a positioning bump. The positioning bumps partially protrude from the lens, such that when the lead frame is disposed on a circuit board, the lead frame is positioned through the positioning bumps and aligns the lens to guide an optical axis of the through-hole LED, thereby achieving the purposes of convenient assembly, thinness, and a reduced thermal-conducting distance.

Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.

Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operation, the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.

Abstract: A light emitting die package is disclosed. The die package includes a substrate, a reflector plate, and a lens. The substrate may be made from thermally conductive but electrically insulating material or from a material that is both thermally and electrically conductive. In embodiments wherein the substrate is made from an electrically conductive material, the substrate further includes an electrically insulating, thermally conductive material formed on the electrically conductive material. The substrate has traces for connecting to a light emitting diode (LED) at a mounting pad. The reflector plate is coupled to the substrate and substantially surrounds the mounting pad. The lens substantially covers the mounting pad. Heat generated by the LED during operation is drawn away from the LED by both the substrate (acting as a bottom heat sink) and the reflector plate (acting as a top heat sink). The reflector plate includes a reflective surface to direct light from the LED in a desired direction.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A semiconductor package is disclosed with a recess (51) for an integrated circuit die (52). The recess is made by bending or deforming all layers of a package substrate, and therefore the recess contains circuitry to connect to the integrated circuit die. The integrated circuit die is electrically connected to the package substrate by either wirebonds (53a), TAB or die solder balls (53b). The package substrate (50), a single sided printed wiring board, has a thick metal core (100) and one or more thin build up layers.

Abstract: A multilayer circuit carrier, electronic devices and panel, and a method for producing a multilayer circuit carrier include at least one semiconductor chip, at least one rewiring layer with a rewiring structure, and at least one insulation layer, which has passage structures.

Abstract: A wiring substrate (1) comprises an insulating base (10) with connection holes (11), buried conductors (12) provided in the connection holes (11) without reaching a rear surface of the insulating base (10), and wiring layers 14 connected to the buried conductors (12). The buried conductors (12) thicken the wiring layers (14), and can form aligning parts (110) on the rear surface of the connection holes (11) to be used for three-dimensional mounting structure. Each wiring layer (14) includes thin terminals (14A), wirings (14B) and thick electrodes (14C). Not only the terminals (14A) and wirings (14B) but also the buried conductors (12) are raised by the same manufacturing process. A semiconductor element (2) is attached to the electrodes (14C) of the wiring substrate (1).

Abstract: A flip-chip LED package structure is disclosed. The flip-chip LED package structure includes a submount, patterned conductive films, a LED chip and two bumps. Several grooves are formed on the sidewalls of the submount. The patterned conductive films are formed on the grooves. The patterned conductive films extend from the grooves to parts of a top surface and a backside surface of the submount. The bumps are formed on two electrodes of the LED chip. The LED chip is disposed on the submount and connects electrically with the patterned conductive films via the bumps. The flip-chip LED package structure is disposed on a circuit board and connects electrically with the circuit without the wire bonding.

Abstract: In the high-frequency module of the present invention, an insulating resin is formed so as to seal a high-frequency semiconductor element mounted on a surface of a substrate and further to seal electronic components. Furthermore, a metal thin film is formed on the surface of the insulating resin. This metal thin film provides an electromagnetic wave shielding effect.

Abstract: A wired circuit board can control characteristic impedance at connection points between wires of a suspension board with circuit and terminal portions of the wired circuit board connected thereto with a simple structure, to improve signal transmission efficiency even for fine pitch wiring or for high frequency signals. The wired circuit board includes a relay flexible wiring circuit board formed by a first wired circuit board including a first metal substrate, a first insulating base layer, a first conductor layer and a first insulating cover layer which is substantially identical in layer structure with the suspension board with circuit and a second wired circuit board connected with the first wired circuit board for connecting with a control circuit board. Since the suspension board with circuit and the first wired circuit board are rendered substantially identical in layer structure, both characteristic impedances at these connection points can be matched.

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.

Abstract: A terminal assembly for active implantable medical devices includes a structural pad, in the form of a substrate or attached wire bond pad, for convenient attachment of wires from the circuitry inside the implantable medical device.

Abstract: A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging.

Abstract: An electronic component includes an electronic chip (110) and a chip carrier portion (120) having sidewalls (121) and a bottom portion (122). The electronic chip is mounted over the bottom portion of the chip carrier portion, and the chip carrier portion shields the electronic chip from radiation outside of the electronic component.

Abstract: A die carrier has a body with a primary surface adapted for attachment to a substrate die. The body at least partially defines a fluid chamber. A fill port and an evacuate port are each fluidically connected to the fluid chamber.

Abstract: Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: An electronic component includes: a package that includes a metal portion formed by pressing a metal, and an insulating portion attached to the metal portion through fusing; a chip housed in the package; first external terminals that are electrically connected to the chip with metal wires, and are partially embedded in the insulating portion; and ground terminals that are convexities of metal portion and are electrically connected to the chip with metal wires, connecting points between the first external terminals and the chip being located at the same height as connecting points between the ground terminals and the chip.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A wired circuit board that can control characteristic impedance at connection points between wires of a suspension board with circuit and terminal portions of the wired circuit board connected thereto with a simple structure, to improve signal transmission efficiency even for fine pitch wiring or for high frequency signal. To provide this wired circuit board, a relay flexible wiring circuit board 1 is formed by a first wired circuit board 14 comprising a first metal substrate 16, a first insulating base layer 17, a first conductor layer 18 and a first insulating cover layer 19 which is substantially identical in layer structure with the suspension board with circuit 3 and a second wired circuit board 15 connected with the first wired circuit board 14 for connecting with a control circuit board 4.

Abstract: A semiconductor device includes an electrically insulating board; conductive interconnections formed on a first face of the board and on a second face opposite to the first face; a semiconductor chip fixed to the board through at least the interconnections on the first face, said semiconductor chip having a semiconductor element electrically connected to the interconnections; a conductive bump formed on the second face of the board and electrically connected to the interconnections on the second face; and a first through-hole passing through the board to ventilate at least a part of the region between the board and the semiconductor chip.

Abstract: An electronic apparatus of the present invention comprises an electronic circuit board; an electrically conductive casing for encasing the electronic circuit board; a semiconductor element module electrically connected to the electronic circuit board; and a resin fixture intervening between the electrically conductive casing and the semiconductor element module, the resin fixture mounted with the semiconductor element module and fitted to the electrically conductive casing. As a result, the resin fixture can suppress a transfer of heat generated in the electronic circuit board to the semiconductor element module.

Abstract: A multi-chip module has semiconductor devices and a wiring substrate for mounting the semiconductor devices, in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.

Abstract: The electronic device is formed in a die including a body of semiconductor material having a first face covered by a covering structure and a second face. An integral thermal spreader of metal is grown galvanically on the second face during the manufacture of a wafer, prior to cutting into dice. The covering structure comprises a passivation region and a protective region of opaque polyimide; the protective region and the passivation region are opened above the contact pads for the passage of leads.

Abstract: A conductive mounting board provided in a package has a recessed portion and a projecting portion, and an insulating mounting board is disposed on the recessed portion. The insulating mounting board is disposed on the recessed portion. The insulating mounting board has an insulating board on the surface of which a wiring portion is disposed. A semiconductor laser, constituted by stacked semiconductor layers each being made from a compound semiconductor composed of a group III based nitride, is disposed on the insulating mounting board and the conductive mounting board. An n-side electrode of the semiconductor laser is in contact with the insulating mounting board and a p-side electrode thereof is in contact with the conductive mounting board. Heat generated in the semiconductor laser is radiated via the conductive mounting board, and short-circuit between the n-side electrode and the p-side electrode is prevented by the insulating mounting board.

Abstract: A structure of a substrate for a high-density semiconductor package is provided. The structure of the substrate comprises a metal substrate and an interconnect substrate disposed on the second surface of the metal substrate. The interconnect substrate comprises at least one or more metal and inter-metal dielectric layers comprising a plurality of traces/lines, pads and vias appropriate for the design. One or more dice are attached to the top surface of the metal substrate, wire bonds are used to connect the dice through open slots on the metal substrate to the Ni/Au plated pads on the interconnect substrate. The uppermost wiring layers are electrically connected to the ball pads on the bottom surface through a plurality of wiring layers and conductive vias. The ball pads are attached to the lowest wiring layer.

Abstract: A ball grid array (BGA) package includes a central cavity for receiving a semiconductor die therein. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically-conductive adhesive layer. Bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging.

Abstract: A package for encasing one or more semiconductor devices includes a composite base component with opposing first and second surfaces formed from a mixture of metallic powders. A first metallic powder is copper or a copper-base alloy and a second metallic powders is a metal or metal alloy with a coefficient of thermal expansion less than that of copper. There is sufficient copper or copper-base alloy present for the composite base to preferably have a coefficient of thermal expansion of at least 9×10−6/° C. A ring frame formed from a nickel/iron-based alloy having a plurality of interconnections extending through sidewalls thereof is bonded to the composite base by a braze with a melting temperature in excess of 700° C. In an alternative embodiment, the composite base brazed to a frame formed from a ceramic having a coefficient of thermal expansion in excess of 8×10−6/° C.

Abstract: By providing an end portion of a radiation plate located on and near an end portion of an insulator sheet, to which a lead frame extends, at a position away from the end portion of the insulator sheet inside of the insulator sheet in a plane direction of the insulator sheet, it is possible to secure a creeping distance between the lead frame and the radiation plate without decreasing a lead frame area on which components can be actually mounted.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.

Abstract: A low-cost header for connecting an electronic components board to a circuit board is disclosed, consisting of side walls made of an unwarpable plastic material and joined together to form a frame around an area substantially the same as the area of the components board. A plurality of metal pins are located in the frame, each having one end extending from said frame such that these ends can be soldered to the components board concurrently with the solder attachment of the components to the board. The other ends of the pins can be formed so that they are adjusted for either through-hole attachment to circuit boards, or for surface mounting.

Abstract: A microwave monolithic integrated circuit (MMIC) assembly and related method are disclosed. A dielectric substrate has a surface on which radio frequency circuits and microstrip lines are formed. At least one MMIC chip opening is dimensioned for receiving therethrough a MMIC chip. A metallic carrier is mismatched as to coefficient of thermal expansion to the dielectric substrate and includes a component surface adhesively secured to the dielectric substrate on the surface opposing the radio frequency circuits and microstrip lines. At least one raised pedestal is on the component surface that is positioned at the MMIC chip opening. A MMIC chip is secured on the pedestal and extends through the MMIC chip opening for connection to the radio frequency circuits and microstrip lines. Stress relief portions are formed in the metallic carrier that segment the carrier into subcarriers and provide stress relief during expansion and contraction created by temperature changes.