Field Effect Transistor In Single Crystal Material, Complementary To That In Non-single Crystal, Or Recrystallized, Material (e.g., Cmos) Patents (Class 257/69)
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Patent number: 7964873Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first polysilicon member that is formed on the substrate and includes an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region; a first insulator formed on the first polysilicon member and having an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region; and a first electrode formed on the first• insulator and having an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region.Type: GrantFiled: November 12, 2004Date of Patent: June 21, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Chun-Gi You
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Patent number: 7964900Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.Type: GrantFiled: September 24, 2009Date of Patent: June 21, 2011Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Wen-Chin Lin, Denny Tang, Chuan-Ying Lee, Hsu Chen Cheng
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Patent number: 7964916Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.Type: GrantFiled: June 2, 2010Date of Patent: June 21, 2011Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan L. de Jong, Deepak C. Sekar
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Patent number: 7952097Abstract: A method for improving the reliability and yield of a thin film transistor by controlling the crystallinity thereof. The method comprises the steps of forming a gate electrode on an island amorphous silicon film, injecting an impurity using the gate electrode as a mask, forming a coating film containing at least one of nickel, iron, cobalt, platinum and palladium so that it adheres to parts of the impurity regions, and annealing it at a temperature lower than the crystallization temperature of pure amorphous silicon to advance the crystallization starting therefrom and to crystallize the impurity regions and channel forming region.Type: GrantFiled: July 31, 2001Date of Patent: May 31, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Hongyong Zhang
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Patent number: 7952101Abstract: The present invention has an object of providing a light emitting device including an OLED formed on a plastic substrate, which can prevent the degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light emitting layer in the OLED (hereinafter, referred to as barrier films) and a film having a smaller stress than that of the barrier-films (hereinafter, referred to as a stress relaxing film), the film being interposed between the barrier films, are provided. Owing to a laminate structure of a plurality of barrier films, even if a crack occurs in one of the barrier films, the other barrier film(s) can effectively prevent moisture or oxygen from penetrating into the organic light emitting layer. Moreover, the stress relaxing film, which has a smaller stress than that of the barrier films, is interposed between the barrier films, thereby making it possible to reduce a stress of the entire sealing film.Type: GrantFiled: July 18, 2008Date of Patent: May 31, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Mai Akiba
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Patent number: 7928438Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.Type: GrantFiled: November 19, 2007Date of Patent: April 19, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
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Patent number: 7928445Abstract: A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region 3d and an N+ drain region 11d. A gate electrode includes a first gate electrode 9 formed on an insulating film 7 and a second gate electrode 13 formed on the first gate electrode 9 via a gate electrode insulating film 11. Between the gate insulating film 7 and the N+ source region 11s, a field insulating film 15 is disposed, over which an edge of the first gate electrode 9 is disposed. A gate voltage applied to the second gate electrode 13 via a gate wiring 13g is divided between the gate insulating film 7 and the gate electrode insulating film 11.Type: GrantFiled: March 11, 2008Date of Patent: April 19, 2011Assignee: Ricoh Company, Ltd.Inventor: Naohiro Ueda
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Patent number: 7923781Abstract: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.Type: GrantFiled: March 27, 2008Date of Patent: April 12, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hideto Ohnuma
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Patent number: 7923779Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.Type: GrantFiled: October 31, 2005Date of Patent: April 12, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroki Adachi
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Patent number: 7919777Abstract: A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.Type: GrantFiled: September 24, 2009Date of Patent: April 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyuck Lim, Young-soo Park, Wenxu Xianyu, Young-kwan Cha
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Publication number: 20110073866Abstract: In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns.Type: ApplicationFiled: August 31, 2010Publication date: March 31, 2011Inventors: Young-Hoo Kim, Hyo-San Lee, Sang-Won Bae, Bo-Un Yoon, Kun-Tack Lee
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Patent number: 7911005Abstract: A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing arsenic and phosphorus as impurities; and a second transistor formed in a logic region, and having a second source/drain region containing at least arsenic as an impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by phosphorus and is deeper than the junction depth of the second source/drain region.Type: GrantFiled: July 17, 2009Date of Patent: March 22, 2011Assignee: RENESAS Electronics CorporationInventor: Hiroki Shirai
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Patent number: 7910933Abstract: A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.Type: GrantFiled: May 20, 2009Date of Patent: March 22, 2011Assignee: AU Optronics Corp.Inventors: Wein-Town Sun, Chun-Sheng Li, Jian-Shen Yu
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Patent number: 7906779Abstract: A thin film transistor includes a polysilicon layer formed over a substrate having a channel region, a source region and a drain region, a conductive layer formed in an upper layer of the polysilicon layer for covering at least a part of the source region and the drain region, an interlayer insulating film formed in a region to cover at least a region including the polysilicon layer, a contact hole formed to penetrate the interlayer insulating film with a depth to expose the conductive layer and a wiring layer formed along a sidewall of the contact hole.Type: GrantFiled: November 28, 2007Date of Patent: March 15, 2011Assignee: Mitsubishi Electric CorporationInventor: Kazushi Yamayoshi
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Patent number: 7893532Abstract: An external contact material for external contacts of a semiconductor device and a method for producing the same are described. The external contact material includes a lead-free solder material. Provided in the solder material is a filler which forms a plurality of gas pores and/or has plastic particles which are arranged in the volume of the solder material.Type: GrantFiled: September 13, 2006Date of Patent: February 22, 2011Assignee: Infineon Technologies AGInventors: Michael Bauer, Irmgard Escher-Poeppel, Edward Fuergut, Simon Jerebic, Bernd Rakow, Peter Strobel, Holger Woerner
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Patent number: 7893437Abstract: A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconductor substrate, and a gate electrode formed on the first gate insulation layer. The example device also includes a second gate insulation layer formed on the gate electrode, a first source region formed on the semiconductor substrate between the first source electrode and the first gate insulation layer, a first drain region formed on the semiconductor substrate between the drain electrode and the first gate insulation layer, an insulating layer formed on the first source electrode, on the first source region, and on the first drain region, and a second source electrode formed on the insulating layer over the first source electrode.Type: GrantFiled: March 21, 2008Date of Patent: February 22, 2011Assignee: Dongbu Electronics Co., Ltd.Inventor: Sang-Hyun Ban
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Patent number: 7884367Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.Type: GrantFiled: October 6, 2009Date of Patent: February 8, 2011Assignee: Sharp Kabushiki KaishaInventors: Yutaka Takafuji, Takashi Itoga
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Patent number: 7880206Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.Type: GrantFiled: July 17, 2009Date of Patent: February 1, 2011Assignee: Crosstek Capital, LLCInventor: Hee-Jeong Hong
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Patent number: 7861406Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, annealing the at least one contact area to form at least one silicide, and removing the unreacted first metal layer and second metal layer from the transistor structure and forming a conductive material in the at least one contact opening.Type: GrantFiled: March 29, 2007Date of Patent: January 4, 2011Assignee: Intel CorporationInventors: Saurabh Lodha, Pushkar Ranade, Christopher Auth
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Patent number: 7863621Abstract: A thin film transistor includes a semiconductor layer formed on a polycrystalline silicon layer crystallized by a super grain silicon (SGS) crystallization method. The thin film transistor is patterned such that the semiconductor layer does not include a seed or a grain boundary created when forming the semiconductor layer on the polycrystalline silicon layer.Type: GrantFiled: September 6, 2006Date of Patent: January 4, 2011Assignee: Samsung Mobile Display Co., Ltd.Inventors: Tae-Hoon Yang, Ki-Yong Lee, Jin-Wook Seo, Byoung-Keon Park
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Patent number: 7863162Abstract: A manufacturing method of a semiconductor device in which the oxygen and carbon concentrations are reduced at the interface of each layer making up the semiconductor multilayer film. A first semiconductor layer is formed on a single-crystal substrate in a first reactor; the substrate is transferred from the first reactor to a second reactor through a transfer chamber; and a second semiconductor layer is formed on the first semiconductor layer in the second reactor. During substrate transfer, hydrogen is supplied when the number of hydrogen atoms bonding with the surface atoms of the first semiconductor layer is less than the number of surface atoms of the first semiconductor layer, and the supply of hydrogen is stopped when the number of hydrogen atoms bonding with the surface atoms of the first semiconductor layer is greater than the number of surface atoms of the first semiconductor layer.Type: GrantFiled: January 11, 2006Date of Patent: January 4, 2011Assignee: Hitachi, Ltd.Inventors: Isao Suzumura, Katsuya Oda
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Patent number: 7858964Abstract: A semiconductor device includes a substrate that includes a first layer and a recrystallized layer on the first layer. The first layer has a first intrinsic stress and the recrystallized layer has a second intrinsic stress. A transistor is formed in the recrystallized layer. The transistor includes a source region, a drain region, and a charge carrier channel between the source and drain regions. The second intrinsic stress is aligned substantially parallel to the charge carrier channel.Type: GrantFiled: February 9, 2009Date of Patent: December 28, 2010Assignee: Infineon Technologies AGInventors: Roman Knoefler, Armin Tilke
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Patent number: 7838346Abstract: Ni silicide is formed through simple steps. After forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate, thereby forming Ni suicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited with a thickness of 10 nm or more over the semiconductor film while heating the substrate to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, and removing an oxide film on the semiconductor film, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film.Type: GrantFiled: July 17, 2009Date of Patent: November 23, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hajime Tokunaga
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Patent number: 7829953Abstract: A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, a gate insulating layer formed on the semiconductor substrate, an NMOS gate formed on the gate insulating layer of the NMOS region, and a PMOS gate formed on the gate insulating layer of the PMOS region. Any one of the NMOS gate and the PMOS gate includes a one-layered conductive layer pattern, and another of the NMOS gate and the PMOS gate includes a three-layered conductive layer pattern.Type: GrantFiled: December 28, 2007Date of Patent: November 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung Suk Jung, Jong-Ho Lee, Sung Kee Han, Ha Jin Lim
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Patent number: 7821008Abstract: A catalytic element is added to an amorphous semiconductor film and heat treatment is conducted therefor to produce a crystalline semiconductor film with good quality, a TFT (semiconductor device) with a satisfactory characteristic is realized using the crystalline semiconductor film. A semiconductor layer includes a region containing an impurity element which has a concentration of 1×1019/cm3 to 1×1021/cm3 and belongs to group 15 of the periodic table and an impurity element which has a concentration of 1.5×1019/cm3 to 3×1021/cm3 and belongs to group 13 of the periodic table, and the region is a region to which a catalytic element left in the semiconductor film (particularly, the channel forming region) moves.Type: GrantFiled: April 10, 2007Date of Patent: October 26, 2010Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Misako Nakazawa, Naoki Makita
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Patent number: 7821138Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.Type: GrantFiled: March 17, 2009Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
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Patent number: 7808001Abstract: An n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate 100. The p-channel MOS transistor includes a gate electrode 102a, a first offset sidewall 103a formed on side surfaces of the gate electrode 102a so as to contain fine particles 110 of group IV semiconductor therein. The n-channel MOS transistor includes a gate electrode 102b and a second offset sidewall 103b formed on side surfaces of the gate electrode 102b. After ion implantation of group IV semiconductor, heat treatment is performed to form the fine particles 110, so that a thickness of the first offset sidewall 103a can be made larger than a thickness of the second offset sidewall 103b.Type: GrantFiled: June 11, 2007Date of Patent: October 5, 2010Assignee: Panasonic CorporationInventor: Shinji Takeoka
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Patent number: 7791077Abstract: An integrated circuit, which is configured such that a MOS transistor and a bipolar transistor are integrated at the same time, is formed on an insulating substrate which includes a display device. An electronic device or a display includes a plurality of semiconductor devices which are formed by using a semiconductor thin film and are formed in the semiconductor thin film that is provided on an insulating substrate and is crystallized in a predetermined direction. The plurality of semiconductor devices include a MOS transistor and at least either one of a lateral bipolar thin-film transistor and a MOS-bipolar hybrid thin film transistor.Type: GrantFiled: August 6, 2007Date of Patent: September 7, 2010Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventor: Genshiro Kawachi
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Patent number: 7790561Abstract: The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418, 428) over a substrate (310), and forming a gate sidewall spacer (610, 630) along one or more sidewalls of the gate dielectric layer (413, 423) and the gate electrode layer (418, 428) using a plasma enhanced chemical vapor deposition process, and forming different hydrogen concentration in NMOS and PMOS sidewall spacers (610, 630) using a local hydrogen treatment (LHT) method.Type: GrantFiled: July 1, 2005Date of Patent: September 7, 2010Assignee: Texas Instruments IncorporatedInventors: Richard P. Rouse, Shashank S. Ekbote, Haowen Bu
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Patent number: 7781839Abstract: A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly over the oxide layer. The semiconductor device further includes a second semiconductor layer (26) having a second lattice constant formed directly over the first semiconductor layer, wherein the second lattice constant is different from the first lattice constant.Type: GrantFiled: March 30, 2007Date of Patent: August 24, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Voon-Yew Thean, Bich-Yen Nguyen
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Patent number: 7777231Abstract: A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.Type: GrantFiled: April 29, 2009Date of Patent: August 17, 2010Assignee: AU Optronics Corp.Inventors: Feng-Yuan Gan, Han-Tu Lin
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Patent number: 7772592Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.Type: GrantFiled: November 19, 2007Date of Patent: August 10, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
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Patent number: 7768012Abstract: Only five photomasks are used to fabricate a LCD pixel array structure. A gate dielectric layer of the LCD pixel array structure is formed by two deposition steps to increase the storage capacity of the storage capacitor.Type: GrantFiled: December 1, 2009Date of Patent: August 3, 2010Assignee: AU Optronics CorporationInventor: Yi-Sheng Cheng
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Patent number: 7755089Abstract: A semiconductor device includes a semiconductor substrate, p-type first and n-type second semiconductor regions formed on the substrate so as to be insulated with each other, n-channel and p-channel MOS transistors formed on the first and second semiconductor regions, the n-channel transistor including a first pair of source/drain regions formed on the first semiconductor region, a first gate insulator formed in direct contact with the first semiconductor region and formed as an amorphous insulator containing at least La, and a first gate electrode formed on the first gate insulator, the p-channel MOS transistor including a second pair of source/drain regions formed opposite to each other on the second semiconductor region, a second gate insulator including a silicon oxide film and the amorphous insulating film formed thereon on the second semiconductor region, and a second gate electrode formed on the second gate insulator.Type: GrantFiled: September 20, 2007Date of Patent: July 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masamichi Suzuki, Masato Koyama
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Patent number: 7755090Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.Type: GrantFiled: October 9, 2007Date of Patent: July 13, 2010Assignee: Sony CorporationInventors: Takashi Abe, Nobuo Nakamura, Keiji Mabuchi, Tomoyuki Umeda, Hiroaki Fujita, Eiichi Funatsu, Hiroki Sato
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Patent number: 7750374Abstract: An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.Type: GrantFiled: November 14, 2006Date of Patent: July 6, 2010Assignee: Freescale Semiconductor, IncInventors: Cristiano Capasso, Srikanth B. Samavedam, Eric J. Verret
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Patent number: 7741645Abstract: A first set of semiconductor devices is formed on a first semiconductor substrate comprising a first semiconductor material having a first melting point. A first via-level dielectric layer containing first contact vias is formed on the first semiconductor substrate. A second semiconductor substrate comprising a second semiconductor material having a second melting point lower than the first melting point is formed either by bonding or deposition. A second set of semiconductor devices is formed on the second semiconductor substrate. A second via-level dielectric layer, second contact vias contacting the second set of semiconductor devices, and inter-substrate vias electrically connecting the first contact vias are thereafter formed. A metal interconnect layer containing a metal interconnect structure is formed over the second via-level dielectric layer to electrically connect the first and second set of semiconductor devices through the second contact vias and the inter-substrate vias.Type: GrantFiled: May 28, 2008Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventor: Huilong Zhu
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Patent number: 7719034Abstract: A semiconductor device having an improved gate process margin includes two active regions spaced apart from each other on a semiconductor substrate and respectively having bent sides with recesses and protrusions corresponding to each other, and two line-shaped gate patterns respectively formed in the longitudinal directions of the active regions. A gap at which the two gate patterns are spaced apart from each other by the recesses and the protrusions in the active regions is relatively narrower by a width difference between the recesses and the protrusions.Type: GrantFiled: December 29, 2006Date of Patent: May 18, 2010Assignee: Hynix Semiconductor Inc.Inventor: Hyoung Soon Yune
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Patent number: 7705359Abstract: The present invention provides an electronic device having more than two conductive layers that cross but not in contact with each other. At least one of the conductive layers comprises a width change part, a width of which changes in a length direction of at least one of the conductive layer. The width change part is formed away from a region of at least one of the conductive layers that crosses a neighboring conductive layer. The present invention also provides a flat panel display device that includes the electronic device described above and manufactured in accordance with the principles of the present invention. The electronic device of the present invention may comprise a thin film transistor.Type: GrantFiled: February 22, 2008Date of Patent: April 27, 2010Assignee: Samsung Mobile Display Co., Ltd.Inventor: Eun-Ah Kim
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Patent number: 7700470Abstract: Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: September 22, 2006Date of Patent: April 20, 2010Assignee: Intel CorporationInventors: Willy Rachmady, Uday Shah, Jack T. Kavalieros, Brian S. Doyle
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Patent number: 7696517Abstract: Transistors having a Hafnium-Silicon gate electrode and high-k dielectric are disclosed. A workpiece is provided having a gate dielectric formed over the workpiece, and a gate formed over the gate dielectric. The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.Type: GrantFiled: March 25, 2008Date of Patent: April 13, 2010Assignee: Infineon Technologies AGInventors: Hongfa Luan, Prashant Majhi
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Patent number: 7683374Abstract: A method of fabricating a photodetector device includes preparing a silicon substrate, forming a patterned mesa on the silicon substrate, and forming a patterned conductive layer over the patterned mesa.Type: GrantFiled: November 29, 2005Date of Patent: March 23, 2010Assignee: Industrial Technology Research InstituteInventors: Cha-Hsin Lin, Lurng-Shehng Lee, Ching-Chiun Wang
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Patent number: 7662704Abstract: An electro-optical device includes: a substrate; a plurality of pixel units provided in a display region on the substrate; and a driving circuit that is provided in a peripheral region surrounding the display region and includes semiconductor elements that drive the plurality of pixel units, each of the semiconductor elements having a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has an SOI (silicon on insulator) structure including a first single crystal silicon layer, and the second semiconductor layer is formed of a second single crystal silicon layer that is formed on the first semiconductor layer by epitaxial growth.Type: GrantFiled: October 6, 2006Date of Patent: February 16, 2010Assignee: Seiko Epson CorporationInventor: Masahiro Yasukawa
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Patent number: 7638805Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.Type: GrantFiled: October 29, 2007Date of Patent: December 29, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani
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Publication number: 20090309103Abstract: A display device includes source/drain electrodes on a substrate, a pixel electrode, an insulating partition wall layer, a channel-region semiconductor layer. The source/drain electrodes and the pixel electrode are formed on the substrate and in contact with each other. The insulating partition wall layer is formed on the substrate and provided with a first opening extending to between the source electrode and the drain electrode and a second opening formed on the pixel electrode and extending to the pixel electrode. The channel-region semiconductor layer is formed on the bottom of the first opening. The insulating film is formed on the partition wall layer so as to cover the first opening including the channel-region semiconductor layer. The oriented film covers the first opening from above the insulating film and the second opening from the pixel electrode.Type: ApplicationFiled: June 16, 2009Publication date: December 17, 2009Applicant: Sony CorporationInventor: Iwao Yagi
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Patent number: 7622740Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.Type: GrantFiled: May 18, 2007Date of Patent: November 24, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Etsuko Fujimoto
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Patent number: 7619250Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.Type: GrantFiled: August 11, 2006Date of Patent: November 17, 2009Assignee: Sharp Kabushiki KaishaInventors: Yutaka Takafuji, Takashi Itoga
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Patent number: 7619253Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. An amorphous semiconductor thin film is irradiated with ultraviolet light or infrared light, to obtain a crystalline semiconductor thin film (102). Then, the crystalline semiconductor thin film (102) is subjected to a heat treatment at a temperature of 900 to 1200° C. in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.Type: GrantFiled: January 25, 2007Date of Patent: November 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Tamae Takano
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Patent number: 7619252Abstract: An integrated circuit having a first connection, a second connection, a substrate, and a control connection, in provided. The control connection controls a conductivity of the integrated circuit between the first connection and the second connection.Type: GrantFiled: August 4, 2005Date of Patent: November 17, 2009Assignee: Atmel Automotive GmbHInventors: Berthold Gruber, Lars Hehn
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Patent number: RE41068Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 ? to 500 ?, and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 ?m.Type: GrantFiled: October 29, 1999Date of Patent: January 5, 2010Assignee: STMicroelectronics, Inc.Inventors: Artur P. Balasinski, Kuei-Wu Huang