Abstract: A metal-ceramic multilayer structure is provided. The underlying layers of the metal/ceramic multilayer structure have sloped sidewalls such that cracking of the metal-ceramic multilayer structure may be reduced or eliminated. In an embodiment, a layer immediately underlying the metal-ceramic multilayer has sidewalls sloped less than 75 degrees. Subsequent layers underlying the layer immediately underlying the metal/ceramic layer have sidewalls sloped greater than 75 degrees. In this manner, less stress is applied to the overlying metal/ceramic layer, particularly in the corners, thereby reducing the cracking of the metal-ceramic multilayer. The metal/ceramic multilayer structure includes one or more alternating layers of a metal seed layer and a ceramic layer.

Abstract: A hermetically sealed semiconductor package that includes a power semiconductor die having electrodes thereof electrically connected to the external surface mountable terminals of the package without the use of wirebonds.

Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.

Abstract: An integrated vacuum package having an added volume on a perimeter within the perimeter of a bonding seal between two wafers. The added volume of space may be an etching of material from the inside surface of the top wafer. This wafer may have vent holes that may be sealed to maintain a vacuum within the volume between the two wafers after the pump out of gas and air. The inside surface of the top wafer may have an anti-reflective pattern. Also, an anti-reflective pattern may be on the outside surface of the top wafer. The seal between the two wafers may be ring-like and have a spacer material. Also, it may have a malleable material such as solder to compensate for any flatness variation between the two facing surfaces of the wafers.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (?m).

Abstract: A chip-type semiconductor ceramic electronic component including a ceramic body made of a semiconductor ceramic, first external electrodes formed on opposite end surfaces of the ceramic body, and second external electrodes extending to cover surfaces of the first external electrodes and part of side surfaces of the ceramic body. A curvature radius of a corner portion of the ceramic body is R (?m), a maximum thickness of a layer of the first external electrode layer, which is in contact with the ceramic body, measured from the end surface of the ceramic body is y (?m), and a minimum thickness of a layer of the second external electrode, which is in contact with the side surface of the ceramic body, measured from an apex of the corner portion of the ceramic body is x (?m), and 20?R?50, ?0.4 x+0.6?y?0.4 is satisfied when 0.5?x?1.1, and ?0.0076 x+0.16836?y?0.4 is satisfied when 1.1?x?9.0.

Abstract: An electronic component module comprising at least one ceramic circuit carrier (2, 3) and a cooling device with at least one heat sink (4), a bonding region arranged between the ceramic circuit carrier (2, 3) and the cooling device adapted for bonding the circuit carrier (2, 3) to the cooling device (4). The bonding region (5, 7; 6, 8) comprises a bonding layer comprised of metal and a eutectic region (7, 8).

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone. The inventive package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate which performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the die and the package, and providing an exterior surface for making electrical connections between package and a user's printed circuit board. In some embodiments, the acoustic port is located in the substrate directly under the silicon condenser die which decreases the thickness of the inventive package.

Abstract: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

Abstract: A light-emitting diode (LED) structure with an improved heat transfer path with a lower thermal resistance than conventional LED lamps is provided. For some embodiments, a surface-mountable light-emitting diode structure is provided having an active layer deposited on a metal substrate directly bonded to a metal plate that is substantially exposed for low thermal resistance by positioning it on the bottom of the light-emitting diode structure. This metal plate can then be soldered to a printed circuit board (PCB) that includes a heat sink. For some embodiments of the invention, the metal plate is thermally and electrically conductively connected through several heat conduction layers to a large heat sink that may be included in the structure.

Abstract: A resistance memory element is provided which has a relatively high switching voltage and whose resistance can be changed at a relatively high rate. The resistance memory element includes an elementary body and a pair of electrodes opposing each other with at least part of the elementary body therebetween. The elementary body is made of a semiconductor ceramic expressed by a formula: {(Sr1-xMx)1-yAy}(Ti1-zBz)O3 (wherein M represents at least one of Ba and Ca, A represents at least one element selected from the group consisting of Y and rare earth elements, and B represents at least one of Nb and Ta), and satisfies 0<x?0.5 and 0.001?y+z?0.02 (where 0?y?0.02 and 0?z?0.02); 0.5<x?0.8 and 0.003?y+z?0.02 (where 0?y?0.02 and 0?z?0.02); or 0.8<x?1.0 and 0.005?y+z?0.01 (where 0?y?0.02 and 0?z?0.02).

Abstract: A portion of a frame body is fixed on a surface of a heat-radiating plate, and on frame body, a semiconductor chip is die-bonded. Next, a prescribed electrode of semiconductor chip and corresponding lead terminal and the like are electrically connected by a prescribed wire. Next, the lead frame is set in a metal mold such that the semiconductor chip is covered with resin from above the semiconductor chip. Thermoplastic resin is introduced into the metal mold, and semiconductor chip and the like are sealed. By taking out the resulting body from the metal mold, a semiconductor is formed. Thus, a semiconductor device can be provided with reduced manufacturing cost.

Abstract: A circuit board has an insulative layer including a first surface and a second surface opposite to the first surface. A plurality of electrically conductive patterns is formed on the first surface of the insulative layer. Conductive lands are formed in a die mounting region of the first surface of the insulative layer and electrically connected to one of the plurality of conductive patterns on the first surface. An extending pattern extends from the conductive lands to outside of the mounting region. A protective layer covers the first surface of the insulative layer and the electrically conductive patterns. A trench is formed in the protective layer to expose the conductive lands and the extending patterns.

Abstract: A fabrication method for metallized a ceramics substrate including the steps of: forming a first conductive paste layer containing metallic powder on a sintered ceramics substrate; forming a second conductive paste layer containing metallic powder of which average particle diameter is different from that of metallic powder constituting the first conductive paste layer; and forming a first conductive layer and a second conductive paste layer. The surface roughness of the first conductive layer and the second conductive layer is different. By this method, it is possible to secure airtightness of the metallized ceramics substrate even if it is a multilayered substrate having a plurality of metallized layers.

Abstract: The invention relates to the fabrication of integrated circuits in general, and notably the circuits of image sensors intended to form the electronic core of photographic apparatus or cameras. The chip is first aligned with respect to the package and then the package is aligned with respect to the optical system. The alignment of the chip with respect to the package is done optically. The alignment of the package with respect to the system is done mechanically with respect to the edges of the package. According to the invention, provision is made for optical marks to be provided on the package, these marks each having an edge aligned with a lateral edge of the package, so as to minimize the positioning errors which would be due to inaccurate positioning of the chip with respect to the edges of the package.

Abstract: Disclosed is a power module having improved joint reliability. Specifically disclosed is a power module including a power module substrate wherein a circuit layer is brazed on the front surface of a ceramic substrate, a metal layer is brazed on the rear surface of the ceramic substrate and a semiconductor chip is soldered to the circuit layer. The metal layer is composed of an Al alloy having an average purity of not less than 98.0 wt. % but not more than 99.9 wt. % as a whole. In this metal layer, the Fe concentration in the side of a surface brazed with the ceramic substrate is set at less than 0.1 wt. %, and the Fe concentration in the side of a surface opposite to the brazed surface is set at not less than 0.1 wt. %.

Abstract: Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener. A locking mechanism may be used to enhance attachment of the heat slug to the stiffener. The heat slug may be directly attached to the die through an opening in the stiffener.

Abstract: A semiconductor device includes a resin case, a plurality of external connection terminals fixedly provided on the resin case, and at least one semiconductor element provided in the resin case. At least one terminal block has at least one wiring terminal for electrically connecting the semiconductor element and the external connection terminals.

Abstract: A circuit module includes an electronic component, a ceramic multilayer substrate and a resin wiring substrate. The ceramic multilayer substrate is provided with a wiring layer disposed on top thereof and a cavity in which the electronic component is mounted, wherein a space between the electronic component and the cavity is filled with a thermosetting resin and a surface of the filled cavity is planarized. The resin wiring substrate has an insulating adhesive layer disposed at one side thereof and provided with at least one opening filled with a conductive resin. The ceramic multilayer substrate and the resin wiring substrate are bonded by the insulating adhesive layer, and the wiring layer on the ceramic multilayer substrate is electrically connected with the conductive resin.

Abstract: An electrical assembly includes at least two PTC-resistor elements, each of which has a base body having a flat shape. Each base body has main surfaces that contain electrodes. A carrier plate has spacers for positioning base bodies of the at least two PTC resistor elements. A width each spacer is about equal, in at least one area, to a distance between facing electrodes of adjacent PTC-resistor elements.

Abstract: A high reliability package which includes electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.

Abstract: A silicon nitride substrate having appropriately adjusted warpage and surface roughness can be obtained by mixing magnesium oxide of 3 to 4 wt % and at least one kind of rare-earth element oxide of 2 to 5 wt % with silicon nitride source material powder to form a sheet-molded body, sintering the sheet-molded body, and performing a heat treatment at a temperature of 1,550 to 1,700 degree C. with a pressure of 0.5 to 6.0 kPa with a plurality of substrates being stacked. Also, a silicon nitride circuit board and a semiconductor module using the same are provided.

Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.

Abstract: A semiconductor plastic package and a method of fabricating the semiconductor plastic package are disclosed. A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.

Abstract: An element-mounting substrate includes a ceramic substrate, an electrode layer formed on the substrate and a ceramic coating layer which is formed on a part of the electrode layer and has a thickness of 5 to 50 ?m. A process for producing the element-mounting substrate includes the steps of forming an electrode precursor layer in the shape of a pattern of an electrode layer on a ceramic plate or a green sheet of a large diameter, forming a ceramic coating precursor layer on a part of the electrode precursor layer and then firing the resulting precursor. In this process, it is preferable to form the ceramic coating layer so as to cover the electrode layer on a predetermined cutting line of the firing product. According to the element-mounting substrate in which a part of the electrode layer is covered with a ceramic, a failure in mounting an element attributable to the thickness of the ceramic coating layer can be prevented when the element is mounted.

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract: An integrated vacuum package having an added volume on a perimeter within the perimeter of a bonding seal between two wafers. The added volume of space may be an etching of material from the inside surface of the top wafer. This wafer may have vent holes that may be sealed to maintain a vacuum within the volume between the two wafers after the pump out of gas and air. The inside surface of the top wafer may have an anti-reflective pattern. Also, an anti-reflective pattern may be on the outside surface of the top wafer. The seal between the two wafers may be ring-like and have a spacer material. Also, it may have a malleable material such as solder to compensate for any flatness variation between the two facing surfaces of the wafers.

Abstract: Integrated circuit-chip hot spot temperatures are reduced by providing localized regions of higher thermal conductivity in the conductive material interface at pre-designed locations by controlling how particles in the thermal paste stack- or pile-up during the pressing or squeezing of excess material from the interface. Nested channels are used to efficiently decrease the thermal resistance in the interface, by both allowing for the thermally conductive material with a higher particle volumetric fill to be used and by creating localized regions of densely packed particles between two surfaces.

Abstract: An air cavity package is manufactured by attaching a die to a surface of a copper heat sink, dispensing a bead of epoxy around a periphery of the heat sink surface after the die is attached to the copper heat sink so that the bead of epoxy generally surrounds the die and placing a ceramic window frame on the bead of epoxy. The epoxy is cured to attach a bottom surface of the ceramic window frame to the copper heat sink.

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract: A light-emitting diode (LED) structure with an improved heat transfer path with a lower thermal resistance than conventional LED lamps is provided. For some embodiments, a surface-mountable light-emitting diode structure is provided having an active layer deposited on a metal substrate directly bonded to a metal plate that is substantially exposed for low thermal resistance by positioning it on the bottom of the light-emitting diode structure. This metal plate can then be soldered to a printed circuit board (PCB) that includes a heat sink. For some embodiments of the invention, the metal plate is thermally and electrically conductively connected through several heat conduction layers to a large heat sink that may be included in the structure.

Abstract: Provided are a thermal barrier coating material and a member coated with thermal barrier that can suppress the separation when used at a high temperature, and have a high thermal barrier effect; a method for manufacturing the member coated with thermal barrier; a turbine member coated with the thermal barrier coating material; and a gas turbine. More specifically provided are a shield coating member comprising a heat-resistant substrate, a bond coat layer formed on the heat-resistant substrate, and a ceramic layer formed on the bond coat layer, wherein the ceramic layer comprises a ceramic represented by a general formula A2Zr2O7, wherein A denotes a rare earth element, and the ceramic layer has (a) a porosity of 1 to 30%, (b) cracks in a thickness direction in pitches of 5 to 100% the total thickness of layers other than the bond coat layer on the heat-resistant substrate, or (c) columnar crystals.

Abstract: A semiconductor substrate includes a substrate layer and a circuit film formed over the substrate layer. One or more openings are formed in the circuit film and the substrate layer. Conductive plates are formed over the circuit film at the peripheries of the openings. A semiconductor die is attached to the circuit film, below the openings with an adhesive material. A conductive material is disposed in the openings to electrically connect the semiconductor die to the conductive plates.

Abstract: A semiconductor chip has an active face in which an integrated circuit region is implanted. The chip includes an inclined lateral contact pad extending beneath the plane of the active face and electrically linked to the integrated circuit region. An electronic module includes a substrate having a cavity in which the chip is arranged. The module can be applied to the production of thin contactless micro-modules for smart cards and contactless electronic badges and tags.

Abstract: A package for use in encapsulating an electronic device is disclosed. The package includes a dielectric frame having first and second sides with a pair of apertures extending through the dielectric frame. These apertures are separated by a raised shelf span extending inwardly from an internal perimeter of the dielectric frame. The raised shelf span defines a first thickness of the dielectric frame and a raised sidewall extending outwardly from the second side along an external perimeter of said dielectric frame defines a second thickness of said frame, with the second thickness being greater than the first thickness. Also provided is a metallic component having a flange and a pedestal that extends perpendicularly from the flange. The flange is bonded to the first side of the dielectric frame and extends across one of the pair of apertures with the pedestal extending into that aperture. A gap between the pedestal and the dielectric frame having a width of at least 0.015 inch.

Abstract: Provided is a semiconductor module wherein a stress relaxing layer is arranged between a ceramic substrate, upon which semiconductor elements are mounted, and a cooling device on the rear side of the ceramic substrate; and the ceramic substrate, the cooling device and the stress relaxing layer are integrally formed. Furthermore, the stress relaxing layer is separated into a plurality of separated sections by two slits. Furthermore, the slits are positioned between the semiconductor elements when viewed from the thickness direction of the stress relaxing layer and not in a projection region of the semiconductor element.

Abstract: A ceramic wiring board 10 includes a ceramic substrate 11 and a wiring layer 12 formed on the ceramic substrate 11. The wiring layer 12 includes a wiring part 13 and a connection part 14, the wiring part 13 having a base metal layer 15, a first diffusion preventive layer 16 and a first Au layer 17 which are stacked in sequence on a surface of the ceramic substrate 11, and the connection part 14 having a second diffusion preventive layer 19, a void suppression layer 20 and a solder layer 18 which are stacked in sequence at a desired position on the wiring part 13. The void suppression layer 20 is made of, for example, Au or an Au—Sn alloy containing 85 mass % or more of Au.

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract: A coupling between a device and a mating part includes an elastic material and perhaps a tensioner coupled to the elastic material. The elastic material is wrapped around at least part of the device. The tensioner or other method is used to stretch the elastic material, thereby reducing the thickness of the elastic material. With the thickness of the elastic material reduced by the stretching, the device is inserted into a hole in a mating part. Then the tension on the elastic material is removed, allowing the elastic material to increase in thickness, so as to fill at least part of the gap between the device and the mating part. The coupling may act as an effective heat transfer device for transmitting (by conduction) heat produced by the heat-producing device, to the mating part, which may act as, or be thermally coupled to, a heat sink.

Abstract: Provided are a thermal barrier coating material and a member coated with thermal barrier that can suppress the separation when used at a high temperature, and have a high thermal barrier effect; a method for manufacturing the member coated with thermal barrier; a turbine member coated with the thermal barrier coating material; and a gas turbine. More specifically provided are a shield coating member comprising a heat-resistant substrate, a bond coat layer formed on the heat-resistant substrate, and a ceramic layer formed on the bond coat layer, wherein the ceramic layer comprises a ceramic represented by a general formula A2Zr2O7, wherein A denotes a rare earth element, and the ceramic layer has (a) a porosity of 1 to 30%, (b) cracks in a thickness direction in pitches of 5 to 100% the total thickness of layers other than the bond coat layer on the heat-resistant substrate, or (c) columnar crystals.

Abstract: A package of the present invention has a laminate structure formed by laminating a plurality of ceramic layers, and has a mount surface to be a joint surface when mounted on a mother board, defined parallel with the laminating direction. A first ceramic layer has a recess with an L-shaped cross section across the mount surface and a side surface, defined at each end thereof in a direction perpendicular to the laminating direction, and an external electrode formed on each recess, the external electrode having a surface thereof exposed to the mount surface.

Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.

Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.

Abstract: A method for structured application of a laminatable intermediate layer (9) to a substrate (1) for a semiconductor module, wherein a separating layer is indirectly or directly applied to the substrate (1) over a large surface, the intermediate layer (9) is applied to the substrate (1), including the separating layer(s), by lamination, over a large surface, the intermediate layer (9) is opened in places on the substrate (1), where recesses are provided for the intermediate layer (9), and the separating layer (8) is removed in these places.

Abstract: A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.

Abstract: In one embodiment, the present invention includes a semiconductor package with lossy material inserts. The lossy material inserts may reduce electronic noise such as package resonance. Other embodiments are described and claimed.

Abstract: A semiconductor device is provided that includes one or more ceramic material layers and one or more low dielectric constant (low-K) epoxy layers on top to be electrically coupled to an integrated circuit device, such as a chip die. The resulting ceramic/organic hybrid substrate takes advantage of the thin low-cost, low-K epoxy layer, by routing the dense circuitry from the chip die to the ceramic material layer. In addition, the use of low-K epoxy layer may reduce the number of ceramic material layers required to about three layers, thus significantly reducing the cost of the substrate. Low-K epoxy material layer may be laminated onto the ceramic material layer to reduce throughput time and cost. The ceramic/organic hybrid substrate may also take advantage of the properties of ceramic materials, which have a much more rigid structure than organic materials and a low CTE (coefficient of thermal expansion) that works well with ultra low-K chip dies.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.