Abstract: A sensor wafer may be configured for in-situ measurements of parameters during an etch process. The sensor wafer may include a substrate, a cover, and one or more components positioned between the substrate and the cover. An etch-resistant coating is formed on one or more surfaces of the cover and/or substrate. The coating is configured to resist etch processes that etch the cover and/or substrate for a longer period than standard thin film materials of the same or greater thickness than the protective coating.

Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.

Abstract: A semiconductor package device includes a leadframe, a first die and a package body. The leadframe includes a first die paddle and a lead. The first die paddle has a first surface and a second surface opposite to the first surface. The first die is disposed on the first surface of the first die paddle. The package body covers the first die and at least a portion of the first surface of the first die paddle and exposing the lead. The package body has a first surface and a second surface opposite to the first surface. The second surface of the package body is substantially coplanar with the second surface of the first die paddle. The lead extends from the second surface of the package body toward the first surface of the package body. A length of the lead is greater than a thickness of the package body.

Abstract: An object is to provide a technology capable of suppressing a crack of a crystalline nitride layer which is generated due to a stress caused by difference in thermal expansion coefficients between a crystalline nitride and diamond. A semiconductor device includes a crystalline nitride layer, a structure containing silicon, and a diamond layer. The structure is disposed on a first main surface of the crystalline nitride layer. The diamond layer is disposed at least on a lateral portion of the structure and has a void between the diamond layer and the first main surface of the crystalline nitride layer. The void is a stress absorbing space, for example.

Abstract: A stiffener apparatus for reducing warpage of an integrated circuit package during heating and cooling are provided. The stiffener apparatus includes an IC substrate configured to receive an IC die on a top side of the IC substrate. The stiffener apparatus includes a primary stiffener ring adhered to the top side of the IC substrate and defining an opening in a region of the IC die such that the primary stiffener ring surrounds the region of the IC die. The primary stiffener ring defines a plurality of grooves. The stiffener apparatus includes a secondary stiffener ring having a plurality of catches configured to engage with the plurality of grooves to removably attach the secondary stiffener ring to the primary stiffener ring on a side of the primary stiffener ring opposite the IC substrate. A method of using a stiffener apparatus during a manufacturing operation is also provided.

Abstract: A waterproofed environmental sensing device with water detection provisions includes an environmental sensor to sense one or more environmental properties. The device further includes an electronic integrated circuit implemented on a substrate and coupled to the environmental sensor via a wire bonding. An air-permeable cap structure is formed over the environmental sensor, and a protective layer is formed over the wire bonding to protect the wire bonding against damage.

Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.

Abstract: An object of the present invention is to provide a seal ring having a metal brazing material layer on one surface of a base material containing KOVAR and a metal plating layer on the other surface, ensuring that the seal ring can prevent generation of a stain on the surface of a metal plating layer and excellent airtightness of an electronic component housing package can be achieved. The present invention has attained the object above by a seal ring which is an annular sealing ring having a nickel layer on the first surface of a base material containing KOVAR (iron-nickel-cobalt alloy) and a metal brazing material layer on the second surface opposite the first surface, wherein the thickness of the nickel layer is from 0.1 to 20 ?m.

Abstract: This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.

Abstract: Aspects of the disclosure provide a waterproof packaging technique for fabricating waterproof microphones in mobile devices. A device based on the waterproof packaging technique can include a microelectromechanical system (MEMS) device, a housing enclosing the MEMS device, and a liquid-resistant air inlet passive device (LRAPD) on the housing. The LRAPD can include at least one channel connecting an exterior of the housing with a chamber formed between the housing and the MEMS device. An inside surface of the channel can be coated with a liquid-repellant coating. In some examples, the liquid-repellant coating can be a self-assembled monolayer (SAM) coating.

Abstract: A radio frequency module includes a wiring substrate, a plurality of components mounted on an upper surface of the wiring substrate, a sealing resin layer laminated on the upper surface of the wiring substrate and covering the plurality of components, a groove formed in an upper surface of the sealing resin layer and extending between predetermined components of the plurality of components, and a shielding wall made of conductive paste in the groove. The sealing resin layer has a stepped area defining the higher portion and lower portion in the upper surface. The groove intersects the stepped area when the wiring substrate is seen in plan view.

Abstract: A semiconductor device is provided. The semiconductor device includes a terminal portion and a casing portion. The terminal portion has a through hole in a principal surface portion. The casing portion has a depression at a position facing the through hole and has an end surface facing portion facing an end surface of the terminal portion. An end surface protruding portion is provided on at least one of the end surface and the end surface facing portion.

Abstract: This application relates to transducer apparatus (300, 400), especially for MEMS capacitive transducers. The apparatus has a voltage bias generator (102) for receiving a supply voltage (VDD) and generating a bias voltage (VB) for biasing a capacitive transducer (101). A voltage supply path extends between a supply voltage input terminal (309a) and the voltage bias generator (102). A programmable trim circuit (207), in use, controls the bias voltage generated by the voltage bias generator. A first filter (301) is configured to applying filtering to the voltage supply path. A programming contact pad (308) is configured to form an external contact of the transducer apparatus when packaged and is electrically coupled to the programmable trim circuit via a signal path that does not include the first filter.

Abstract: An embodiment is MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.

Abstract: A lid array panel includes multiple lids, where each lid includes an outer side wall. The lid array panel further includes a bridge section surrounding and attached to the outer side walls of the lids, where the lids are connected to each other by the bridge section, the lid array panel further includes a reinforcement attached to the bridge section. A package structure includes a carrier, a chip disposed on an upper surface of the carrier, a lid, a bridge section, and a reinforcement. The lid includes a top wall and an outer side wall, the top wall and the outer side wall of the lid together define a cavity, and the outer side wall of the lid is attached to the upper surface of the carrier. The bridge section surrounds, and is attached to, the outer side wall of the lid. The reinforcement is attached to the bridge section.

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Abstract: A wafer level package includes a substrate including bonding pads and a first protection dam and having a plurality of circuit pattern units disposed on a side; a printed circuit board having a plurality of connection pads, a second protection dam and via holes disposed thereon; and a connection unit connected to some of the plurality of connection pads and the second protection dam disposed on the printed circuit board. Freedom of design can be improved through the wafer level package and the manufacturing method thereof, and reliability of the wafer level package can be improved. The manufacturing process can be simplified as the bridge process is omitted when wiring is designed, and the size of an element may be reduced.

Abstract: A device and techniques for fabricating the device are described for forming a wafer-level thermal sensor package using microelectromechanical system (MEMS) processes. In one or more implementations, a wafer level thermal sensor package includes a thermopile stack, which includes a substrate, a dielectric membrane, a first thermoelectric layer, a first interlayer dielectric, a second thermoelectric layer, a second interlayer dielectric, a metal connection assembly, a passivation layer, where the passivation layer includes at least one of a trench or a hole, and where the substrate includes a cavity adjacent to the at least one trench or hole, and a bond pad disposed on the passivation layer and electrically coupled to the metal connection assembly; and a cap wafer assembly coupled to the thermopile stack, the cap wafer assembly including a wafer having a cavity formed on a side of the wafer configured to be adjacent to the thermopile stack.

Abstract: Some features pertain to a package that includes an enhanced electromagnetic shield. The package includes a substrate, an electronic component coupled to the substrate, and a mold partially surrounding the electronic component. The package further includes a first shield over the mold, and a second shield over the first shield. One of the first shield or the second shield is a high permeability shield and the remaining first or second shield is a high conductivity shield relative to the high permeability shield.

Abstract: Methods and system which eliminate steps in the mounting a discrete device to an electronic circuit using a conductive film, shortening the time required to attach each discrete device. The methods place a discrete device onto the conductive tape and partially cure portions of the adhesive. The discrete device is then removed from the conductive tape along with the adhesive and conductive particles which have been transferred onto the contact pads of the discrete device. The discrete device is then placed on the substrate and aligned. Pressure and heat are applied to complete the bond.

Abstract: This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity.

Abstract: A semiconductor package device comprises a substrate, an electronic component and a protection layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a first opening penetrating the substrate. The electronic component is disposed on the first surface of the substrate. The protection layer is disposed on the second surface of the substrate. The protection layer has a first portion adjacent to the first opening and a second portion disposed farther away from the first opening than is the first portion of the protection layer. The first portion of the protection layer has a surface facing away from the second surface of the substrate. The second portion of the protection layer has a surface facing away from the second surface of the substrate.

Abstract: A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.

Abstract: An example heat exchanger may comprise a base to thermally conductively engage with a computing component, a plurality of fins that may extend from the base on the same side as the computing component, and an auxiliary fluid channel defined by the plurality of fins. The plurality of fins may transfer thermal energy from the computing component to a fluid medium surrounding the plurality of fins. The auxiliary fluid channel may facilitate the transfer of thermal energy from an electronic component, other than the computing component, disposed within the auxiliary fluid channel to a fluid medium flowing through the auxiliary fluid channel.

Abstract: Apparatus, systems and methods for reducing feedback in a hearing aid that includes a transducer configured to detect sound, a sound processor configured to process signals from the transducer, a receiver configured to receive signals outputted from the sound processor, and an acoustic feedback reduction system. The acoustic feedback reduction system is configured to provide signals to the sound processor to produce a null targeting signal steerable toward a source of feedback.

Abstract: A process of forming a thermal interface material structure includes forming an assembly that includes a thermal interface material disposed between a first mating surface and a second mating surface. The first mating surface is associated with a module lid, and the second mating surface is associated with a heat sink. Protruding surface features are incorporated onto the first mating surface or the second mating surface. The process also includes compressing the assembly to form a thermal interface material structure. The thermal interface material structure includes the thermal interface material disposed within an interface defined by the first mating surface and the second mating surface. The protruding surface features protrude from the first mating surface or the second mating surface into selected areas of the interface to limit relative movement of the mating surfaces into the selected areas during thermal cycling to reduce thermal interface material migration out of the interface.

Abstract: An attachment structure for use with a standalone control unit. The control unit includes a threaded insert located in an enclosed cavity which allows screws to be used for grounding of an EMI/RFI board, along with creating a sealed, enclosed pocket. The attachment structure allows for grounding of the PCB to the sheet metal base plate without creating a leak path to the outside of the control unit. This ground approach encapsulates the screw to prevent the formation of a leak path.

Abstract: A method of fabricating an electronic device, the method including: arranging a device chip with no bump located on a lower surface of the device chip on a mounting substrate including a bump located on an upper surface of the mounting substrate; and bonding a pad located on the lower surface of the device chip and the bump by applying an ultrasonic wave to the device chip from an upper surface of the device chip.

Abstract: A differential pressure detection element includes: a support portion having an opening; a cantilever portion supported in a cantilever manner by the support portion so as to protrude into the opening; a diffusion layer including a piezoresistive portion provided at a fixed end of the cantilever portion; a pair of wiring portions electrically connected to the diffusion layer; a first insulating layer covering the diffusion layer; and a second insulating layer laid on the first insulating layer. A linear expansion coefficient of the first insulating layer is smaller than a linear expansion coefficient of a material of which the cantilever portion is composed, and a linear expansion coefficient of the second insulating layer is larger than the linear expansion coefficient of the first insulating layer.

Abstract: A circuit package for electrically connecting a plurality of modules. The circuit package having a first and second mounting plate, each including a plurality of module connectors configured to receive and form electrical connections with the plurality of modules. The circuit package also having a first and second sidewall mounted to the first and second mounting plates. The first sidewall including a plurality of sidewall fins extending outward from the first sidewall so that the plurality of sidewall fins are positioned between the first and second mounting plates and at least partially interleave with the plurality of modules.

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a top length and a bottom portion with a bottom length, and the top length is greater than the bottom length. The semiconductor device structure also includes a package layer formed between the lid structure and the die structure, and a sidewall of the bottom portion of the lid structure is not aligned with a sidewall of the die structure.

Abstract: Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package stiffener may also be coupled with the adhesive adjacent to the die. A magnetic thin film may be coupled with the package stiffener. Other embodiments may be described and/or claimed.

Abstract: An RC-IGBT has a chip area of the semiconductor chip larger than that of a semiconductor chip including an IGBT section but not including an FWD section, as it is provided with the FWD section. It is demanded to reduce the chip area of the RC-IGBT semiconductor chip. Provided is a semiconductor device including: a transistor section including a plurality of transistors; a free wheeling diode section being at least opposite to one side of the transistor section and provided outside the transistor section, when the transistor section is seen from a top view; and a gate runner section and a gate pad section provided to contact the transistor section and not surrounding an entire periphery of the transistor section, when the transistor section is seen from a top view.

Abstract: A semiconductor device, such as a semiconductor power device, includes: a semiconductor die having a semiconductor die front surface, a package formed onto the semiconductor die, the package having a portion facing the front surface of the semiconductor die, and a thermally-conductive layer including graphene over the front portion of the package facing the front surface of the semiconductor die.

Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.

Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.

Abstract: The embodiments disclose a method for creating a digital device protective artwork case conforming to digital device shapes and sizes and includes electronically stitched artwork designs that seamlessly wraparound the digital device protective artwork case, a shock absorbing flexible bumper core with flexible buttons to operate digital device buttons, a flexible back, a hard outer shell back, a hard outer shell portable charger external battery with blinking LED eyes battery level indicators, a tempered glass front face, a digital device protective artwork case website including at least one processor, at least one digital electronic stitching processor, at least one database, at least one communication device, an internet connection, and at least one manufacturing data interface to transfer user selections of protective artwork case styles and stock artwork designs to at least to at least one manufacturing device including an electronically stitched image application device and a mold material depositing dev

Abstract: Embodiments of the present invention are directed to a system and method for a central intelligence system for managing, analyzing, and maintaining large scale, connected information systems. The centralized information system may receive data from servers, databases, mainframes, processes, and other technological assets. A user is able to use the centralized information system to run analysis on the data associated with the connected systems, including: historical analysis, real-time analysis, and predictive modeling. The system can monitor the data and automatically correct identified errors without the need of human intervention. The centralized information system can also generate risk management profiles and automatically modify data to conform to the risk management profiles.

Abstract: A method for manufacturing a semiconductor device includes: preparing a first substrate; forming a metal film having a Ti layer as the most outermost surface on one surface of the first substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a first pad portion; preparing a second substrate; forming on one surface of the second substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a second pad portion; vacuum annealing the first substrate and the second substrate to remove an oxide film formed on the Ti layer in the first pad portion and the second pad portion; and bonding the first pad portion and the second pad portion together.

Abstract: An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package.

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

Abstract: The present invention provides a MEMS and a sensor having the MEMS which can be formed without a process of etching a sacrifice layer. The MEMS and the sensor having the MEMS are formed by forming an interspace using a spacer layer. In the MEMS in which an interspace is formed using a spacer layer, a process for forming a sacrifice layer and an etching process of the sacrifice layer are not required. As a result, there is no restriction on the etching time, and thus the yield can be improved.

Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.

Abstract: A surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover, and the MEMS microphone die is substrate-mounted and acoustically coupled to an acoustic port provided in the surface mount package. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.

Abstract: An improved microelectromechanical device includes an upper plate, a lower plate, and a spacing structure. The upper plate includes a first surface and an opposite second surface. The lower plate is spaced from the upper plate. The lower plate includes a third surface that faces the first surface of the upper plate and a fourth surface that is opposite of the third surface. The lower plate also includes a series of structures disposed with the third surface of the lower plate. The spacing structure is coupled to the upper and lower plate. The spacing structure includes a base portion that is sealed to the first surface of the upper plate and the third surface of the lower plate. The spacing structure further includes a protrusion that extends from the base portion between the upper and lower plates.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: A thermally conductive sheet including a sheet body that is a cured product of a thermally conductive resin composition including a binder resin and carbon fibers covered with insulating coating films, wherein the carbon fibers exposed on a surface of the sheet body are not covered with the insulating coating films and are covered with a component of the binder resin.

Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.