Cap Or Lid Patents (Class 257/704)
  • Patent number: 9224689
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 29, 2015
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Patent number: 9214592
    Abstract: An image sensor package and method of manufacture that includes a crystalline handler with conductive elements extending therethrough, an image sensor chip disposed in a cavity of the handler, and a transparent substrate disposed over the cavity and bonded to both the handler and image sensor chip. The transparent substrate includes conductive traces that electrically connect the sensor chip's contact pads to the handler's conductive elements, so that off-chip signaling is provided by the substrate's conductive traces and the handler's conductive elements.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: December 15, 2015
    Assignee: Optiz, Inc.
    Inventor: Vage Oganesian
  • Patent number: 9211626
    Abstract: A semiconductor device includes a semiconductor chip, and a grinding-processed layer laminated on one surface of the semiconductor chip. Further, the semiconductor device includes a sealing resin that seals the semiconductor chip and the grinding-processed layer; and a metal remaining-thickness checking portion provided adjacent to the grinding-processed layer, sealed by the sealing resin, and having a inclined plane that is inclined with respect to a laminating direction of the grinding-processed layer.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: December 15, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeshi Kondo, Hideki Naruoka, Hajime Tsukahara
  • Patent number: 9199839
    Abstract: Method of hermetically sealing a hole with a fuse material, comprising the following steps: applying a portion of wettable material onto a surface such that it completely surrounds the hole made through said surface and is located outside the hole, or completely surrounds a first part of said surface corresponding to a location of the hole; applying a portion of fuse material on the portion of wettable material and on a second part of said surface located around the portion of wettable material; reflowing the portion of fuse material to form a bump of fuse material which has a shape corresponding to a part of a sphere, which is fastened only to the portion of wettable material and which hermetically plugs the hole; wherein the hole is made in said surface before reflowing the portion of fuse material.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: December 1, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, EPCOS AG
    Inventors: Jean-Louis Pornin, Arnoldus Den Dekker, Marcel Giesen, Florent Greco, Gudrun Henn, Bruno Reig, Damien Saint-Patrice
  • Patent number: 9174836
    Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: November 3, 2015
    Assignee: RAYTHEON COMPANY
    Inventors: Roland Gooch, Buu Diep, Thomas Allan Kocian, Stephen H. Black, Adam M. Kennedy
  • Patent number: 9162871
    Abstract: A metal mesh lid MEMS package includes a substrate, a MEMS electronic component coupled to the substrate, and a metal mesh lid coupled to the substrate with a lid adhesive. The metal mesh lid includes a polymeric lid body having a top port formed therein and a metal mesh cap coupled to the lid body. The metal mesh cap covers the top port and serves as both a particulate filter and a continuous conductive shield for EMI/RF interferences. Further, the metal mesh cap provides a locking feature for the lid adhesive to maximize the attach strength of the metal mesh lid to the substrate.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: October 20, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Bob Shih-Wei Kuo, Russell Shumway, Louis B. Troche, Jr.
  • Patent number: 9142519
    Abstract: An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 22, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Takahashi, Shuuichi Kariyazaki
  • Patent number: 9111951
    Abstract: Provided is a semiconductor device configured to prevent a penetration of moisture into an internal circuit. The moisture from a bonding pad to the internal circuit is blocked by providing an underlying polysilicon film (10) formed as a lower layer of a bonding pad, a bonding pad (1) formed above the underlying polysilicon film (10) through intermediation of an inter-layer insulation film (21), and an outer circumferential interconnecting line (3) formed so as to surround an outer side of the bonding pad 1, and by connecting the outer circumferential interconnecting line (3) and the underlying polysilicon film (10) with a continuous outer circumferential contact.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 18, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Keisuke Uemura, Jun Osanai
  • Patent number: 9090454
    Abstract: Embodiments of methods of fabricating a sensor device includes attaching a first wafer to a sensor wafer with a first bond material, and attaching a second wafer to the sensor wafer with a second bond material, the second bond material having a lower bonding temperature than the first bond material. After attaching the second wafer, an opening (e.g., a trench cut) through the second wafer is formed, and an adhesive material is provided through the opening to further secure the second wafer to the sensor wafer. Embodiments of sensor devices formed using such methods include a first device cavity having a first pressure, and a second device cavity having a second pressure.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philip H. Bowles, Stephen R. Hooper
  • Patent number: 9081137
    Abstract: Methods and structures are provided for implementing embedded hybrid electrical-optical printed circuit board (PCB) constructs. The embedded hybrid electrical-optical PCB construct includes electrical channels and optical channels within a single physical PCB layer. The embedded hybrid electrical-optical PCB construct includes an electrically conductive sheet or a copper sheet, and a reflective mesh adhesive layer provided with the electrical channels and optical channels within the single physical PCB layer.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: July 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Doyle, Joseph Kuczynski, Kevin A. Splittstoesser, Timothy J. Tofil
  • Patent number: 9070693
    Abstract: There are provided a semiconductor package and a manufacturing method thereof, capable of increasing integration by mounting electronic devices on both surfaces of a substrate. The semiconductor package includes a first substrate having mounting electrodes on both surfaces thereof; a plurality of electronic devices mounted on both surfaces of the first substrate; and a second substrate exposed in cavities and bonded to a bottom surface of the first substrate so as to accommodate the electronic devices mounted on the bottom surface of the first substrate in the cavities.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Min Gi Cho
  • Patent number: 9061893
    Abstract: The present invention relates to a surface mount package for a micro-electro-mechanical system (MEMS) microphone die and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components that simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the MEMS microphone die is mechanically attached, providing an interior surface for making electrical connections between the MEMS microphone die and the package, and providing an exterior surface for surface mounting the microphone package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: June 23, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9059148
    Abstract: A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: June 16, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Kuei-Wei Huang, Chih-Wei Lin, Chih Chun Chiu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9041182
    Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihiko Nagano, Kazuhide Abe, Hiroshi Yamada, Kazuhiko Itaya, Taihei Nakada
  • Patent number: 9040360
    Abstract: Methods for manufacturing multiple bottom port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphones are manufactured from panels of substrates, sidewall spacers, and lids. Each MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port disposed in the substrate. The panels are joined together, and each individual substrate, sidewall spacer, and lid cooperate to form an acoustic chamber for its respective MEMS microphone die. The joined panels are then singulated to form individual MEMS microphones.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 26, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9041192
    Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 26, 2015
    Assignee: Broadcom Corporation
    Inventors: Seyed Mahdi Saeidi, Sam Ziqun Zhao
  • Patent number: 9041169
    Abstract: A semiconductor packaging container allowing to use in millimeter band is provided at a low cost. The inner SIG pads and the inner GND pads, capable of a direct connection with a signal terminal of a semiconductor chip 10 are provided on the bottomed cylindrical dielectric case formed of the liquid crystal polymer. Further, the external SIG pads integrally formed with the inner SIG pads 201, 202 and the external GND pad 303 integrally formed with the inner GND pad are provided on the back of the bottom surface of the dielectric case as the external terminal. The inner GND pads and are to form the coplanar waveguide with the inner SIG pads and. Also, the inner GND pads and are to add capacitive reactance for canceling the inductance caused by the space at the semiconductor chip portion to the coplanar waveguide.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 26, 2015
    Assignee: YOKOWO CO., LTD.
    Inventors: Shoichi Koshikawa, Junichiro Nikaido, Shintaro Takase, Yoshio Aoki
  • Patent number: 9041191
    Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.
    Type: Grant
    Filed: November 19, 2011
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9041190
    Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing 98 wt % or more of one metallic element such as silver having a melting point of 400° C. or higher, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazutaka Takagi
  • Patent number: 9035446
    Abstract: Provided is a power module. The power module includes a power semiconductor chip. The power module further includes a case that accommodates the power semiconductor chip. A silicone gel seals the power semiconductor chip within the case. The silicone gel including a heat-resistant silicone gel containing 20 to 100 mass ppm of a metal complex comprising a metal selected from a group consisting of iron and platinum.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 19, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Daisuke Kimijima, Yuji Ichimura
  • Patent number: 9035447
    Abstract: A power semiconductor module and a power semiconductor module assembly, which includes a plurality of power semiconductor modules, are disclosed. The power semiconductor module includes an electrically conducting base plate, an electrically conducting top plate, arranged in parallel to the base plate and spaced apart from the base plate, at least one power semiconductor device, which is arranged on the base plate in a space formed between the base plate and the top plate, and at least one presspin, which is arranged in the space formed between the base plate and the top plate to provide contact between the semiconductor device and the top plate. A metallic protection plate can be provided at an inner face of the top plate facing towards the base plate, wherein the material of the protection plate has a melting temperature higher than the melting temperature of the top plate.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 19, 2015
    Assignee: ABB TECHNOLOGY AG
    Inventors: Franc Dugal, Dominik Trüssel
  • Patent number: 9035451
    Abstract: The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of cavities with different pressures on a wafer package system, and an associated apparatus. In some embodiments, the method is performed by providing a work-piece having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the work-piece in a first ambient environment having a first pressure. The bonding forms a plurality of cavities abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of cavities leading to a gas flow path that could be held at a pressure level different from the first pressure. The one or more openings in the one or more of the plurality of cavities are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of cavities to be held at the different pressure.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Kuei-Sung Chang, Chun-Wen Cheng
  • Patent number: 9029179
    Abstract: A method for producing a MEMS device having improved charge elimination characteristics includes providing a substrate having one or more layers, and applying a first charge elimination layer onto at least one portion of one given layer of the substrate. The method may then (1) apply a sacrificial layer onto the first charge elimination layer, (2) apply a second charge elimination layer onto at least a portion of the sacrificial layer, and (3) deposit a movable layer onto at least a portion of the second charge elimination layer. To form a structure within the movable layer the method may etch the movable layer. The method may then etch the sacrificial layer to release the structure.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 12, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Fang Liu, Kuang L. Yang
  • Patent number: 9030032
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kitahara, Hiroshi Koguma
  • Patent number: 9029968
    Abstract: An optical sensor element is mounted in a package which includes a glass substrate having a cavity, and a glass lid substrate bonded to the other substrate to close the cavity. The glass substrate with the cavity has metalized wiring patterns on front and rear surfaces thereof, and a through hole filled with metal to form a through-electrode interconnecting the wiring patterns on the front and rear surfaces. A metalized wiring pattern on the rear surface of the glass lid substrate is electrically connected to the wiring pattern on the front surface of the other substrate with an adhesive containing conductive particles. The glass lid substrate is made either of glass having a filter function or glass having a light shielding property with an opening therethrough filled with glass having a filter function.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: May 12, 2015
    Assignee: Seiko Instruments Inc.
    Inventors: Koji Tsukagoshi, Hitoshi Kamamori, Sadao Oku, Hiroyuki Fujita, Keiichiro Hayashi
  • Patent number: 9023689
    Abstract: A top-port, surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a sidewall spacer and a lid with an acoustic port, and the MEMS microphone die is lid-mounted and acoustically coupled to the acoustic port. The substrate, the sidewall spacer, and the lid are joined together to form the MEMS microphone, and the substrate, the sidewall spacer, and the lid cooperate to form an acoustic chamber for the lid-mounted MEMS microphone die.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9024432
    Abstract: A surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a sidewall spacer and a lid, and the MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port in the substrate. The substrate, the sidewall spacer, and the lid are joined together to form the MEMS microphone, and the substrate, the sidewall spacer, and the lid cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9024434
    Abstract: Semiconductor package are provided. In one embodiment, the semiconductor package may include a substrate such as a circuit substrate, a semiconductor chip mounted on the circuit substrate, a molding (or an encapsulant) covering the semiconductor chip and the circuit substrate and including a first temperature control member, and a heat dissipation member covering the molding.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunhyeok Im, Kyol Park, Taeje Cho
  • Patent number: 9018747
    Abstract: An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded. The upper surface of the first portion is positioned lower than an upper surface of the third portion. The second portion has a thin-walled portion positioned to surround the first portion, the thin-walled portion having a thickness thinner than that of the first portion as well as thinner than that of the third portion.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Kyocera Corporation
    Inventor: Michikazu Nagata
  • Patent number: 9018753
    Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics Pte Ltd
    Inventor: Wing Shenq Wong
  • Patent number: 9018755
    Abstract: A joint structure includes: a ceramic member; a metallized layer formed on a surface of the ceramic member; and a metal member joined to the metallized layer via a brazing material. The metal member includes a base part erected on the metallized layer, and an extended part extended from the base part to define a predetermined gap with respect to the metallized layer. The base part includes an end joined to the metallized layer by a brazing material layer including the brazing material, and a side joined to the metallized layer around the base part by a fillet including the brazing material formed on the metallized layer around the base part. The extended part defines a recess at a position facing the metallized layer on which the fillet is formed.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: April 28, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Sadahiro Nishimura, Naoki Tsuda
  • Patent number: 9013034
    Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing copper and a low-melting-point metal such as tin, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 9003637
    Abstract: A method of manufacturing a microphone assembly having an ear set function includes assembling a mike cell unit; obtaining a region for connection with the mike cell unit on a PCB, mounting only a conductive member in the region, and mounting other remaining components outside the region; adhering the mike cell unit to a corresponding region of the PCB; and sealing an adhering portion between the mike cell unit and the PCB. Assembling the mike cell unit includes inserting a mike cell case having a sound hole and a curing portion into a diaphragm assembly; stacking a spacer on the diaphragm assembly; inserting a back electrode plate into an insulating ring base; mounting the insulating ring base on the spacer; mounting a metal ring base on the insulating ring base; and curing or clamping a curing portion of the mike cell case.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 14, 2015
    Assignee: BSE Co., Ltd.
    Inventors: Dong Sun Lee, Hyoung Joo Kim
  • Patent number: 9005736
    Abstract: An electronic component manufacturing method that efficiently grinds a cover layer provided on a substrate even when the substrate is warped includes the step of forming first grooves at intervals in a cover layer provided on a substrate by repeating grinding with a rotary blade at a pitch more than a thickness W of the rotary blade. Next, at least portions provided in the cover layer along the first grooves are removed to reduce the thickness of the cover layer by repeating grinding at a pitch equal to or less than the thickness W of the rotary blade.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hidemasa Kawai
  • Patent number: 9006897
    Abstract: An integrated circuit includes a number of metallization levels separated by an insulating region disposed over a substrate. A housing includes walls formed from metal portions produced in various metallization levels. A metal device is housed in the housing. An aperture is produced in at least one wall of the housing. An external mechanism outside of the housing is configured so as to form an obstacle to diffusion of a fluid out of the housing through the at least one aperture. At least one through-metallization passes through the external mechanism and penetrates into the housing through the aperture in order to make contact with at least one element of the metal device.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Antonio Di-Giacomo
  • Patent number: 9006880
    Abstract: The present invention relates to a surface mount package for a micro-electro-mechanical system (MEMS) microphone die and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components that simplifies manufacturing and lowers costs. The surface mount package features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the MEMS microphone die is mechanically attached, providing an interior surface for making electrical connections between the MEMS microphone die and the package, and providing an exterior surface for surface mounting the microphone package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The microphone package has a substrate with metal pads on its top and bottom surfaces, a sidewall spacer, and a lid.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 14, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9006844
    Abstract: A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: April 14, 2015
    Assignee: DunAn Microstaq, Inc.
    Inventor: Parthiban Arunasalam
  • Patent number: 9000544
    Abstract: A MEMS package structure, including a substrate, an interconnecting structure, an upper metallic layer, a deposition element and a packaging element is provided. The interconnecting structure is disposed on the substrate. The MEMS structure is disposed on the substrate and within a first cavity. The upper metallic layer is disposed above the MEMS structure and the interconnecting structure, so as to form a second cavity located between the upper metallic layer and the interconnecting structure and communicates with the first cavity. The upper metallic layer has at least a first opening located above the interconnecting structure and at least a second opening located above the MEMS structure. Area of the first opening is greater than that of the second opening. The deposition element is disposed above the upper metallic layer to seal the second opening. The packaging element is disposed above the upper metallic layer to seal the first opening.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: April 7, 2015
    Assignee: Pixart Imaging Inc.
    Inventors: Hsin-Hui Hsu, Sheng-Ta Lee, Chuan-Wei Wang
  • Publication number: 20150091153
    Abstract: The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of cavities with different pressures on a wafer package system, and an associated apparatus. In some embodiments, the method is performed by providing a work-piece having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the work-piece in a first ambient environment having a first pressure. The bonding forms a plurality of cavities abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of cavities leading to a gas flow path that could be held at a pressure level different from the first pressure. The one or more openings in the one or more of the plurality of cavities are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of cavities to be held at the different pressure.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Kuei-Sung Chang, Chun-Wen Cheng
  • Patent number: 8994168
    Abstract: A semiconductor package includes a wiring board; a semiconductor chip mounted on the wiring board; and a radiation plate mounted on the semiconductor chip, including an insulating member including a resin that is the same as a resin included in the wiring board, as a main constituent, a first metal foil formed on a first surface of the insulating member, a second metal foil formed on a second surface of the insulating member, the second surface being an opposite to the first surface, the radiation plate being provided with a through hole that penetrates the first metal foil, the insulating member and the second metal foil, and a metal layer formed to cover the inner surface of the through hole to thermally connect the first metal foil and the second metal foil by penetrating the insulating member in a thickness direction.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yukio Sato
  • Publication number: 20150076683
    Abstract: An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device.
    Type: Application
    Filed: March 18, 2013
    Publication date: March 19, 2015
    Applicant: HANA MICRON CO., LTD.
    Inventors: Jae-Sung Lim, Ju-Hyung Kim, Jin-Wook Jeong, Hyun-Joo Kim, Hyouk Lee
  • Publication number: 20150076684
    Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and a fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.
    Type: Application
    Filed: November 25, 2014
    Publication date: March 19, 2015
    Inventors: Makoto Okada, Shuuichi KARIYAZAKI, Wataru SHIROI, Masafumi SUZUHARA, Naoko SERA
  • Patent number: 8981550
    Abstract: A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 17, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Joon Young Park, Jin Suk Jeong, Kyeong Sool Seong, Seo Won Lee
  • Patent number: 8981552
    Abstract: This power converter includes a first substrate, a second substrate, a power conversion element, and a case portion, and the case portion includes a first connection terminal connected to a first conductor pattern arranged on a side of the first substrate closer to the power conversion element and a second connection terminal connected to a second conductor pattern arranged on a side of the second substrate opposite to the power conversion element.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Shoichiro Shimoike, Daisuke Yoshimi
  • Patent number: 8975092
    Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Limited
    Inventors: Chihiro Uchibori, Michael G. Lee
  • Publication number: 20150061107
    Abstract: An insulation sheet made from silicon nitride comprising: a sheet-shaped silicon-nitride substrate which contains ?-silicon-nitride crystal grains as a main phase; and a surface layer which is formed on one face or both front and back faces of surfaces of the silicon-nitride substrate and is formed from a resin or a metal which includes at least one element selected from among In, Sn, Al, Ag, Au, Cu, Ni, Pb, Pd, Sr, Ce, Fe, Nb, Ta, V and Ti. A semiconductor module structure using the insulation sheet made from silicon nitride.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventor: Takayuki NABA
  • Publication number: 20150061105
    Abstract: Aspects of the invention provide a semiconductor module that can be manufactured without using a bending jig for bearing the stress in bending process of the terminal and scarcely generates cracks in the resin parts of the semiconductor module. In some aspects of the invention, a semiconductor module can include a casing made of a resin material accommodating a semiconductor chip, a terminal one end of which is electrically connected to the semiconductor chip and the other end of which is projecting out of the casing and bent and a lid made of a resin material fitted on an opening of the casing, a part of end region of the lid being in contact with the terminal and being a thick part with a thickness thicker than a thickness of other parts of the lid.
    Type: Application
    Filed: August 6, 2014
    Publication date: March 5, 2015
    Inventor: Tomofumi OOSE
  • Publication number: 20150061106
    Abstract: A method (30) of forming a semiconductor package (20) entails applying (56) an adhesive (64) to a portion (66) of a bonding perimeter (50) of a base (22), with a section (68) of the perimeter (50) being without the adhesive (64). A lid (24) is placed on the base (22) so that a bonding perimeter (62) of the lid (24) abuts the bonding perimeter (50) of the base (22). The lid (24) includes a cavity (25) in which dies (38) mounted to the base (22) are located. A gap (70) is formed without the adhesive (64) at the section (68) between the base (22) and the lid (24). The structure vents from the gap (70) as air inside the cavity (25) expands during heat curing (72). Following heat curing (72), another adhesive (80) is dispensed in the section (68) to close the gap (70) and seal the cavity (25).
    Type: Application
    Filed: October 29, 2014
    Publication date: March 5, 2015
    Inventors: STEPHEN R. HOOPER, PHILIP H. BOWLES
  • Publication number: 20150061104
    Abstract: An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other.
    Type: Application
    Filed: July 30, 2014
    Publication date: March 5, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi TAKAHASHI, Shuuichi KARIYAZAKI
  • Patent number: 8970029
    Abstract: A flip chip microelectronic package having a heat spreader is provided. In one embodiment, the microelectronic package comprises a die having a first surface and a second surface, the first surface being coupled to a substrate; a thermal interface material disposed in thermal conductive contact with the second surface of the die; and a heat spreader adapted for dissipating heat from the die, the heat spreader disposed in thermal conductive contact with the thermal interface material. The heat spreader includes a lid having an inner chamber therein defined by a first wall and a second wall, the second wall securely joined to the first wall to seal the chamber, the lid being mounted to the substrate and a wick layer positioned in the chamber.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yao Lin, Wen-Yi Lin