Directly Attached To Semiconductor Device Patents (Class 257/707)
  • Patent number: 10796979
    Abstract: A power module includes: a power chip; a control chip controlling the power chip; a power terminal connected to the power chip; a control terminal connected to the control chip; and a package covering the power chip, the control chip, the power terminal, and the control terminal with mold resin, wherein first and second recesses for attaching a fin are respectively provided on side faces facing each other of the package from which neither the power terminal nor the control terminal protrudes, and the first and second recesses are arranged not at positions opposite to each other but alternately.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 6, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Maki Hasegawa, Shuhei Yokoyama, Shigeru Mori, Hisashi Kawafuji
  • Patent number: 10794561
    Abstract: A vehicle lamp includes a projector lens, a first light source disposed behind the projector lens and configured to emit light for forming a low-beam light distribution pattern, a second light source disposed behind the projector lens and configured to emit light for forming an additional high-beam light distribution pattern, and a metal base member. The base member includes a first surface on which the first light source is disposed and a second surface on which the second light source is disposed. The second surface is inclined with respect to an optical axis such that an emission portion of the light emitting element faces obliquely forward and upward. A plurality of metal plate-shaped fins extending in a left-right direction and an upper-lower direction of the lamp are arranged along a front-rear direction of the lamp on a rear surface of the first and second surfaces.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 6, 2020
    Assignee: KOITO MANUFACTURING CO., LTD.
    Inventors: Takashi Inoue, Kazushi Kawaguchi
  • Patent number: 10741472
    Abstract: A power module includes: a power chip; a control chip controlling the power chip; a power terminal connected to the power chip; a control terminal connected to the control chip; and a package covering the power chip, the control chip, the power terminal, and the control terminal with mold resin, wherein first and second recesses for attaching a fin are respectively provided on side faces facing each other of the package from which neither the power terminal nor the control terminal protrudes, and the first and second recesses are arranged not at positions opposite to each other but alternately.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 11, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Maki Hasegawa, Shuhei Yokoyama, Shigeru Mori, Hisashi Kawafuji
  • Patent number: 10730016
    Abstract: The present invention relates to ultrafiltration. In particular, the present invention provides nanoporous membranes having pores for generating in vitro and in vivo ultrafiltrate, devices and bioartificial organs utilizing such nanoporous membranes, and related methods (e.g., diagnostic methods, research methods, drug screening). The present invention further provides nanoporous membranes configured to avoid protein fouling with, for example, a polyethylene glycol surface coating.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 4, 2020
    Assignees: The Regents of the University of Michigan, The Cleveland Clinic Foundation
    Inventors: William H. Fissell, Shuvo Roy, Aaron Fleischman, Kenneth G. Goldman
  • Patent number: 10714447
    Abstract: An electrode terminal includes a body and a first bonding part. The body includes a first metal material. Then, the first bonding part is bonded to one end of the body, and includes a second metal material which is a clad material other than the first metal material. The first bonding part is ultrasonically bondable to a first bonded member. An elastic part which is elastically deformable is provided between the one end of the body and the other end of the body.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rei Yoneyama, Yoshitaka Kimura, Akihiko Yamashita
  • Patent number: 10682792
    Abstract: The mold device according to the present invention is a mold device to resin-seal the semiconductor device including an insert electrode, and in the semiconductor device, the insert electrode is provided with an insert hole, a nut having a screw hole is disposed in the insert electrode so that the insert hole and the screw hole communicate with each other, the mold device includes a mold body into which resin is injected to resin-seal the semiconductor device, including a side of the insert electrode where the nut is disposed, and a rod-like member that is inserted into the insert hole, and the rod-like member is inserted into the screw hole of the nut through the insert hole of the insert electrode to draw the nut to the side of the insert electrode.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 16, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takatoshi Yasui, Yuki Hata, Shoji Saito, Katsuji Ando, Korehide Okamoto, Ryoji Murai
  • Patent number: 10685901
    Abstract: A boiling cooling device e includes a power semiconductor that is vertically disposed, heat radiating plates provided on both side faces of the power semiconductor, heat receiving jackets provided at both sides of the power semiconductor and covering the heat radiating plates, refrigerant filled in the heat receiving jackets and being in contact with the heat radiating plates, a condenser connected to the heat receiving jackets, and fine longitudinal grooves formed on a heat radiating face of the heat radiating plate and extending in a vertical direction, where creation of air bubbles is promoted by heat generated in the power semiconductor and by the fine longitudinal grooves, the created air bubbles rising and passing through a forward pipe and then reaching the condenser to be liquefied, such that liquid is returned to the heat receiving jacket via a return pipe.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: June 16, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Michiaki Hiyoshi
  • Patent number: 10643943
    Abstract: A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Tin-Hao Kuo
  • Patent number: 10622276
    Abstract: A power module capable of increasing structural stability and reliability at high temperatures includes: an upper substrate having a metal layer; a lower substrate spaced apart from the upper substrate and having a metal layer facing the metal layer of the upper substrate; a semiconductor element configured to be disposed between the upper substrate and the lower substrate; and at least one leg portion formed on at least one of the metal layer of the upper substrate and the metal layer of the lower substrate to make the upper substrate and the lower substrate be spaced apart from each other at a predetermined interval, in which the leg portion may be electrically connect the semiconductor element to the metal layer of the upper substrate or the metal layer of the lower substrate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 14, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Young Seok Kim, Hyun Woo Noh, Kyoung Kook Hong, Su Bin Kang
  • Patent number: 10575448
    Abstract: An apparatus for grounding a heat sink utilizing shape-memory alloy includes a printed circuit board, a logic chip, a heat sink, and a first grounding member, wherein the first grounding member is a shape-memory alloy. The apparatus further includes the logic chip electrically coupled to the printed circuit board and the heat sink disposed on a top surface of the logic chip. The apparatus further includes a first end of the first grounding member electrically coupled to the heat sink, wherein a second end of the grounding first member is disposed on a first ground land of the printed circuit board.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Theron L. Lewis, Timothy P. Younger, David J. Braun, James D. Bielick, Jennifer Bennett, Stephen M. Hugo, John R. Dangler
  • Patent number: 10546844
    Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Choon Kim, Eon-Soo Jang, Eun-Hee Jung, Hyon-Chol Kim, Byeong-Yeon Cho
  • Patent number: 10537044
    Abstract: A heat dissipating component comprising: a main body formed from a first material; a heat dissipating sheet that is formed from a second material having higher thermal conductivity than the first material, that is provided at the main body, and that includes a plurality of fins thermally connected to each other at positions other than apexes and a connecting portion thermally connecting the plurality of fins to an electronic component; and a covering portion that covers at least a portion of a bottom portion of a groove between the plurality of fins.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Suzuki, Kanae Nakagawa
  • Patent number: 10524392
    Abstract: A device can dissipate heat from an electrical component by using a phase change material. A horizontal circuitry layer can have opposing first and second sides. A vertical hole can extend through the horizontal circuitry layer. A vertical channel can include a phase change material positioned in the vertical hole and in thermal contact with the first and second sides of the horizontal circuitry layer. The phase change material can dissipate a first amount of heat from the first side by absorbing the first amount of heat and changing phase from a solid form to a liquid form. The phase change material, when in the liquid form, can dissipate a second amount of heat from the first side by transporting the second amount of heat via convection from the first side of the horizontal circuitry layer to the second side of the horizontal circuitry layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventor: Tsung-Yu Chen
  • Patent number: 10515826
    Abstract: The present invention provides a laminated member that prevents contact of a semiconductor chip and an external leading terminal etc. without increasing the number of components. The laminated member is a laminated member having a three-layer structure, comprising: an upper highly thermally conductive layer; a lower highly thermally conductive layer; and an intermediate layer having a low thermal expansion coefficient, wherein the above-described laminated member is larger than the above-described semiconductor chip in a plan view, and wherein a height position of the above-described first peripheral edge area is located at a certain distance below a height position of the above-described first bonding area, and a height position of the second peripheral edge area of the above-described second bonding area is located at a certain distance above a height position of the above-described second bonding area.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 24, 2019
    Assignee: Sansha Electric Manufacturing Co., Ltd.
    Inventors: Kazunori Inami, Takahiro Maruyama
  • Patent number: 10510634
    Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 10454415
    Abstract: An electrical box includes a first electrical component having an output terminal, and a second electrical component having an input terminal. A jumper is connected to the output terminal of the first electrical component and the input terminal of the second electrical component. The jumper defines a heat flow path between the first and second electrical components. The heat flow path defines a minimum path between the first and second electrical components along the heat flow path. A minimum distance along the minimum heat path between the first and second electrical components is greater than a minimum distance between first and second electrical components.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 22, 2019
    Assignee: Eaton Intelligent Power Limited
    Inventors: Adam Douglas Ledgerwood, Matthew Thomas Pernot, Arkadiusz Oskar Doroz
  • Patent number: 10438932
    Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 8, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jinchang Zhou, Yusheng Lin, Mingjiao Liu
  • Patent number: 10418536
    Abstract: The present disclosure provides a LED metal substrate and a LED module. An insulator is provided to cover an electrode or a side surface of a metal layer in the LED metal substrate, or provided on an original creepage path between the electrode and the metal layer in the LED metal substrate to form a new creepage path with increased creepage distance, in order to increase the breakdown voltage between the electrode and the metal layer. It is possible to avoid a phenomenon that an electric arc is generated between the electrode and the metal layer when a relative high voltage applied by the electrode during a breakdown test. So that the breakdown voltage of the LED metal substrate with an insulator reaches higher than that of a LED metal substrate without the insulator in the same dimension, and a technical problem in the art may be solved.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 17, 2019
    Assignee: KAISTAR LIGHTING (XIAMEN) CO., LTD.
    Inventors: Jingqiong Zhang, Shanshan Yang, Jinqiang Huang
  • Patent number: 10410971
    Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: David Fraser Rae, Hong Bok We, Christopher Healy, Chin-Kwan Kim
  • Patent number: 10403559
    Abstract: In a power semiconductor device, the thickness dimension of a protective film of a semiconductor element is made smaller than that of an upper electrode, so a protective film is not pressed by being pressurized from upward when bonded by a metal sintered body, and the force of tearing off the upper electrode riding on an inclined surface of the protective film does not act, so that no crack of the upper electrode occurs, thus maintaining the soundness of the semiconductor element. Also, a lead bonded by a solder to the upper electrode of the semiconductor element is made of a copper-Invar clad material, the linear expansion coefficient of which is optimized, and thereby it is possible to realize a durability superior to that of a heretofore known wire-bonded aluminum wiring.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 3, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masaru Fuku, Noriyuki Besshi, Ryuichi Ishii, Takayuki Yamada, Takao Mitsui, Komei Hayashi
  • Patent number: 10388639
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10347617
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10325855
    Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Kim, Jie Fu, Changhan Yun, Chin-Kwan Kim, Manuel Aldrete, Chengjie Zuo, Mario Velez, Jonghae Kim
  • Patent number: 10321554
    Abstract: The shape of an abutting portion where a heat sink and an electronic component or the heat sink and a connection wire abut against each other, through the intermediary of an intermediate member, is contrived so that there is provided an electronic control unit that can raise the easiness of production including the intermediate member, while securing the heat radiation performance. There is provided an electric power converter in which an intermediate member having an insulating property and a heat-conductive property is provided in a gap between a heat sink and a connection wire abutting portion or an electronic component, in which the top surface of a maximum heat generating component is a plane, and in which the portion, of the heat sink, that faces the top surface of the maximum heat generating component is part of a basic plane.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: June 11, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshihito Asao, Akihiko Mori
  • Patent number: 10290600
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
  • Patent number: 10290587
    Abstract: A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 14, 2019
    Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
    Inventors: Khai Ngo, Chi-Ming Wang, Han Cui
  • Patent number: 10249563
    Abstract: Provided is a multilayer wiring substrate capable of achieving excellent conduction reliability. The multilayer wiring substrate is formed by laminating an anisotropic conductive member including an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each conductive path has a protrusion protruding from the surface of the insulating base, and a wiring substrate having a substrate and one or more electrodes to be formed on the substrate, and conductive paths which come into contact with the electrode among the plurality of conductive paths are deformed so that adjacent conductive paths come into contact with each other.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Shunji Kurooka, Yoshinori Hotta
  • Patent number: 10186476
    Abstract: The present disclosure relates to a semiconductor package with at least one grounded fence to inhibit dendrites of die-attach materials. The semiconductor package includes a carrier, a die-attach material, and a wire-bonded die. The carrier includes a die pad and a negative carrier contact. The wire-bonded die includes a die body, a negative die contact, a grounded fence, and a bonding wire. A bottom surface of the die body is coupled to the die pad by the die-attach material. The negative die contact and the grounded fence reside over a top surface of the die body. The grounded fence, which has a same DC potential as the die pad, extends between the negative die contact and a periphery of the top surface of the die body. The bonding wire extends from the negative die contact to the negative carrier contact.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 22, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Larry Wall, Christopher Sanabria
  • Patent number: 10174927
    Abstract: An LED illumination device includes an LED device; a base having a concavity for receiving the LED device; a heat sink including a plate coupled to the base and a plurality of fins extending from a surface of the plate opposite the base, the fins extending laterally beyond sides of the plate; a cooling fan for forcing air over the fins; and a casing housing the LED substrate, the base, the heat sink, and the cooling fan.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: January 8, 2019
    Assignees: ACP JAPAN CO., LTD.
    Inventor: Shoichi Nakamura
  • Patent number: 10177067
    Abstract: A manufacturing method including following steps is provided. A substrate that includes a core layer, a first conductive layer, and a second conductive layer is provided. A heat conducting channel is formed in the substrate, and an adhesion layer is formed on the second conductive layer to cover a side of the heat conducting channel. A heat conducting element and a buffer layer are placed into the heat conducting channel, and a gap is formed between either the heat conducting element or the buffer layer and an inner side surface of the heat conducting channel. The gap is filled with a first insulant material, and the adhesion layer and the buffer layer are removed to form a cavity and expose the heat conducting element. The first conductive layer and the second conductive layer are patterned to form a first patterned circuit layer and a second patterned circuit layer, respectively.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: January 8, 2019
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chin-Sheng Wang, Chih-Hsien Cheng, Shih-Hao Sun
  • Patent number: 10143092
    Abstract: A circuit substrate includes a core substrate having a cavity penetrating through the substrate, a metal block accommodated in the cavity of the substrate, a first build-up layer laminated on first side of the substrate and including insulating resin layers such that the first build-up layer is covering first surface of the block from the first side, and a second build-up layer laminated on second side of the substrate and including insulating resin layers such that the second build-up layer is covering second surface of the block from the second side. The first build-up layer includes an electronic component mounting structure formed on outermost portion of the first build-up layer, and the block is formed such that the first and second surfaces have roughened surfaces, respectively, and that the roughened surface of the first surface has surface roughness different from surface roughness of the roughened surface of the second surface.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: November 27, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Yukinobu Mikado, Mitsuhiro Tomikawa, Koji Asano, Kotaro Takagi
  • Patent number: 10130013
    Abstract: A data center cooling system includes an outer container that defines a first volume; an inner container that defines a second volume and is positioned within the first volume, the inner container including an air outlet that includes an airflow path between the first and second volumes; a liquid seal to fluidly isolate a liquid phase of a non-conductive coolant that fills at least a portion of the first and second volumes from an ambient environment; and a plurality of electronic heat-generating devices at least partially immersed in the liquid phase of the non-conductive coolant to transfer a heat load to the non-conductive coolant.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: November 13, 2018
    Assignee: Google LLC
    Inventors: Madhu Krishnan Iyengar, Christopher G. Malone, Gregory P. Imwalle
  • Patent number: 10121723
    Abstract: According to an embodiment of a method, the method includes forming a first thermally conductive layer on an outer surface of a semiconductor package. The first thermally conductive layer formed on the outer surface of the semiconductor package is configured to be mounted to an external heat sink.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: November 6, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Kok Tee Lau, Jayaganasan Narayanasamy
  • Patent number: 10083912
    Abstract: A package substrate having an opening and through-substrate interconnect structures is attached to a temporary carrier such as an adhesive film. The active surface of an IC die is placed in contact with the carrier substrate within the opening, to temporarily attach the die to the carrier substrate. Another die is attached to the side of the first die furthest from the carrier substrate. In one embodiment, the dies are attached to each other using an epoxy so that their respective non-active surfaces face each other. Bond wires are connected between interconnects at the active surface of the second die and the substrate. The wires are then encapsulated. After removal of the carrier substrate, a build-up interconnect structure is formed that includes external interconnects of the package substrate, such as solder balls of a ball grid array package.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: September 25, 2018
    Assignee: NXP USA, INC.
    Inventors: Zhiwei Gong, Wei Gao
  • Patent number: 10083919
    Abstract: Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shidong Li
  • Patent number: 10032648
    Abstract: A maximum length of a heat sink is set as “L” and a warp amount of the heat sink is set as “Z”; the warp amount “Z” is set as a positive value if a bonded surface of the heat sink to a metal layer is deformed to be concave or the warp amount “Z” is set as a negative value if the bonded surface is deformed to be convex; a ratio Z/L of the maximum length “L” and the warp amount “Z” measured at 25° C. is in a range not smaller than ?0.005 and not larger than 0.005, and the ratio Z/L is in the range not smaller than ?0.005 and not larger than 0.005 even when it is heated to 280° C. and then cooled to 25° C.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: July 24, 2018
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Tomoya Oohiraki, Sotaro Oi
  • Patent number: 10026672
    Abstract: A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 17, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Florian G. Herrault, Miroslav Micovic
  • Patent number: 10012803
    Abstract: This optical fiber connection structure connects a multicore fiber and a bundle structure bundling a plurality of optical fibers. The multicore fiber has a plurality of cores arranged in a lattice. The bundle structure includes closely packed optical fibers of the same diameter. The bundle structure is configured such that signal light optical fiber groups including signal light optical fibers and a dummy fiber group including dummy optical fibers are stacked in multiple layers. The signal light optical fiber groups are configured with the signal light optical fibers aligned in the mutually contacting direction. The signal light optical fiber groups and the dummy fiber group are stacked orthogonal to the alignment direction of the optical fibers constituting the respective fiber groups.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: July 3, 2018
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kengo Watanabe, Tsunetoshi Saito
  • Patent number: 9992912
    Abstract: The present invention provides a heat dissipating device combined structure, which consists of a heat sink and a clasp member. At least one expanded portion extends from the heat sink, and a side extends from each of the two sides of a base of the clasp member to form a conduit. The heat sink and a circuit board are disposed inside the conduit, and at least one ledge portion is formed on the sides. Moreover, a slanting portion extends from and is provided on air foils configured on the sides, and the ends of the slanting portions respectively clasp the expanded portions. Accordingly, the circuit board is mounted on the ledge portions, and electronic components on the circuit board are attached to the bottom portion of the aforementioned heat sink.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 5, 2018
    Assignee: LIANCHUN INDUSTRIAL CO., LTD.
    Inventor: Chun-Chieh Wang
  • Patent number: 9953903
    Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: April 24, 2018
    Assignee: NXP B.V.
    Inventors: Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis, Rintje van der Meulen, Emil Casey Israel
  • Patent number: 9955591
    Abstract: A circuit substrate includes a core substrate having a cavity penetrating through the substrate, a combined component accommodated in the cavity of the substrate, a first build-up layer laminated on first surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, a second build-up layer laminated on second surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, and a filling resin filling gap formed between the cavity and combined component accommodated in the cavity of the substrate. The combined component includes an electronic component and a metal block, the electronic component has terminal surface on side facing the first surface of the substrate, and the metal block is superposed to surface of the electronic component on the opposite side of the electronic component with respect to the terminal surface.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: April 24, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Mitsuhiro Tomikawa, Koji Asano
  • Patent number: 9865528
    Abstract: A cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the method comprises attaching a metal heat sink to a leadframe using an intermediate structure that is thermally conductive and electrically insulating; molding a plastic body around the heat sink and exposed leads of the leadframe to form a cavity, with partially and selectively exposed lead top surfaces, heat sink top surface, and heat sink bottom surface; attaching a semiconductor device die within cavity on to the exposed top surface of the heat sink using a thermal conductive material; wire bonding respective wire bond pads of the semiconductor device die to the exposed lead top surfaces and to the heat sink for grounding; and attaching a lid to the plastic molded body to protect the wire bonded device within cavity.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 9, 2018
    Assignee: UBOTIC COMPANY LIMITED
    Inventors: Zhang Xiao Ping, Sin Chi Wai
  • Patent number: 9837394
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: December 5, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 9806001
    Abstract: A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 31, 2017
    Assignee: Volterra Semiconductor LLC
    Inventors: Mihalis Michael, Ilija Jergovic
  • Patent number: 9791899
    Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Gong Ouyang, Kai Xiao, Lu-Vong Phan
  • Patent number: 9769361
    Abstract: An assembly structure for industrial camera has a camera module including an electric circuit board and a sensor component configured on the electric circuit board, a base of a camera seat combined onto the electric circuit board, a protrusive and hollow engaging portion installed on the surface of the base, an installation hole combined with a predetermined lens installed in the engaging portion, and a lens hole creating a closure state configured at the bottom of the installation hole.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 19, 2017
    Assignee: Adlink Technology Inc.
    Inventor: Chie-Ta Lee
  • Patent number: 9741635
    Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, means for a spreading heat in directions substantially parallel to a major surface of the one or more semiconductor dice embedded in a second dielectric layer and means for dissipating heat in directions substantially perpendicular to the major surface of the one or more semiconductor dice.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 9728487
    Abstract: An object of the present invention is to improve the reliability of a semiconductor device having an imaging function. A semiconductor device includes a package having a cavity and terminals (TE1), a semiconductor chip that has an imaging unit and is arranged in the cavity, and a cap material with which the cavity is sealed and which has translucency. In addition, the semiconductor device includes a mounting board that has a through-hole and terminals (TE2) and is arranged so as to electrically couple the terminals (TE1) to the terminals (TE2), a heat transfer member that is inserted into the through-hole and is coupled to the package, and a heat sink coupled to the heat transfer member.
    Type: Grant
    Filed: April 9, 2016
    Date of Patent: August 8, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Karashima, Yumi Imamura, Yosuke Imazeki
  • Patent number: 9716051
    Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: July 25, 2017
    Assignee: NVIDIA Corporation
    Inventors: Leilei Zhang, Ron Boja, Abraham Yee, Zuhair Bokharey
  • Patent number: 9698783
    Abstract: Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: July 4, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Wen Li, Norio Chujo, Masami Makuuchi, Takehito Kamimura