Directly Attached To Semiconductor Device Patents (Class 257/707)
  • Patent number: 11456249
    Abstract: A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Tin-Hao Kuo
  • Patent number: 11319207
    Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 3, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Il Kwon Shim
  • Patent number: 11309231
    Abstract: A semiconductor device includes a heat sink, a semiconductor chip and a circuit board that are fixed to the heat sink with a fixing material, plural leads connected to the semiconductor chip and the circuit board via wires, and mold resin provided on the heat sink. The mold resin covers parts of the leads, the wires, and the semiconductor chip, and exposes remainders of the leads. The surfaces of the leads and the heat sink are provided with roughened plating having a surface roughness RMS=150 nm or more. The fixing material is solder or sintered silver. The water absorption rate of the mold resin is 0.24% or less.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 19, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroaki Ichinohe, Katsumi Miyawaki, Takao Moriwaki
  • Patent number: 11302657
    Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 12, 2022
    Assignee: MediaTek Inc.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • Patent number: 11304312
    Abstract: A method for manufacturing a circuit board comprises: a first single-sided board and an insulating structure are provided. The first single-sided board is pressed to the insulating structure and covers opposite side surfaces of the insulating structure to form a first laminated board. A second single-sided board and a third single-sided board are provided. The second single-sided board is pressed to the third single-sided board and covers opposite side walls of the third single-sided board to form a second laminated board. An inner wiring layer is formed by the second laminated board. The second laminated board with the inner wiring layer and the first laminated board are pressed to form an intermediate structure. Outer wiring layers are formed by the intermediate structure. Covering films are formed on surfaces of the outer wiring layers. Electromagnetic interference shielding layers are formed on the covering films.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 12, 2022
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Hao-Yi Wei, Yan-Lu Li
  • Patent number: 11289425
    Abstract: Various embodiments include a semiconductor component comprising: a first carrier part; a second carrier part arranged opposite the first carrier part; a semiconductor element arranged between the first carrier part and the second carrier part; a contact surface arranged on one of the parts; a contact sleeve arranged on one of the carrier parts opposite the contact surface; and a contact pin with, at one axial end, an end face providing an electrical contact connection of the contact surface and, in a region averted from said axial end, a connection region for the connection of the contact pin with the contact sleeve by means of press fitting. At least one of the first carrier part or the second carrier part comprises a printed conductor connected to the contact surface and/or to the contact sleeve.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 29, 2022
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Rene Blank, Martin Franke, Peter Frühauf, Rüdiger Knofe, Bernd Müller, Stefan Nerreter, Jörg Strogies, Klaus Wilke
  • Patent number: 11289982
    Abstract: A circuit board includes a circuit board main body including a first through hole and a second through hole, a first inlay member inserted into the first through hole, and a second inlay member inserted into the second through hole. A first end surface of the first inlay member includes a first end portion on the side of the second inlay member, a second end portion on the opposite side of the second inlay member, a first area including the first end portion, and a second area including the second end portion. A first end surface of the second inlay member includes a third end portion on the side of the first inlay member, a fourth end portion on the opposite side of the first inlay member, a third area including the third end portion, and a fourth area including the fourth end portion. The circuit board further includes a first resist provided in the second area, and a second resist provided in the fourth area.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 29, 2022
    Assignee: NIDEC CORPORATION
    Inventor: Naoki Iwagami
  • Patent number: 11284501
    Abstract: A circuit board includes a circuit board main body including a first through hole, and a first inlay member inserted into the first through hole. The first inlay member includes a first end surface, one surface of the circuit board main body includes a first through hole peripheral portion located around the first through hole, a first conductive pattern is located around the first through hole peripheral portion, the first through hole peripheral portion includes a first pattern exposed area where the first conductive pattern is exposed, and a first pattern non-exposed area where the first conductive pattern is covered with a resist, and the first end surface and the first pattern exposed area are a first mount pad to which a first terminal of an electronic component is connected.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 22, 2022
    Assignee: NIDEC CORPORATION
    Inventor: Naoki Iwagami
  • Patent number: 11268004
    Abstract: A boron nitride powder includes boron nitride aggregated grains that are formed by aggregation of scaly hexagonal boron nitride primary particles, the boron nitride powder having the following characteristic properties (A) to (C): (A) the primary particles of the scaly hexagonal boron nitride have an average long side length of 1.5 ?m or more and 3.5 ?m or less and a standard deviation of 1.2 ?m or less; (B) the boron nitride aggregated grains have a grain strength of 8.0 MPa or more at a cumulative breakdown rate of 63.2% and a grain strength of 4.5 MPa or more at a cumulative breakdown rate of 20.0%; and (C) the boron nitride powder has an average particle diameter of 20 ?m or more and 100 ?m or less. Also provided are a method for producing the same and a thermally conductive resin composition including the same.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 8, 2022
    Assignee: DENKA COMPANY LIMITED
    Inventors: Go Takeda, Yoshitaka Taniguchi
  • Patent number: 11251107
    Abstract: A semiconductor device includes a heat sink, a semiconductor chip and a circuit board that are fixed to the heat sink with a fixing material, plural leads connected to the semiconductor chip and the circuit board via wires, and mold resin provided on the heat sink. The mold resin covers parts of the leads, the wires, and the semiconductor chip, and exposes remainders of the leads. The surfaces of the leads and the heat sink are provided with roughened plating having a surface roughness RMS=150 nm or more. The fixing material is solder or sintered silver. The water absorption rate of the mold resin is 0.24% or less.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroaki Ichinohe, Katsumi Miyawaki, Takao Moriwaki
  • Patent number: 11211551
    Abstract: A current sensor package, comprises a current path and a sensing device. The sensing device is spaced from the current path, and the sensing device is configured for sensing a magnetic field generated by a current flowing through the current path. Further, the sensing device comprises a sensor element. The sensing device is electrically connected to a conductive trace. An encapsulant extends continuously between the current path and the sensing device.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Rainer Markus Schaller, Volker Strutz
  • Patent number: 11166366
    Abstract: A heat dissipating circuit board assembly includes a heat sink having a first wall, a second wall spaced from the first wall, and an end wall extending between the first and second walls. The first wall, the second wall, and the end wall collectively define a cavity. The assembly additionally includes a printed circuit board having a first face and a second face opposite the first face. The printed circuit board is located within the cavity such that the first wall of the heat sink extends over the first face and the second wall of the heat sink extends over the second face to allow heat to be transferred from the printed circuit board to the heat sink. The heat sink is configured to interface with a connector socket when the circuit board is connected to the connector socket for stabilizing the printed circuit board.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 2, 2021
    Assignee: TRI-Tech International
    Inventor: Richard P. Zirretta
  • Patent number: 11024559
    Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a shielding structure can serve as an enclosure formed by conductive material or by a mesh of such material that can be used to block electric fields emanating from one or more electronic components enclosed by the shielding structure at a global package level or local and/or compartment package level for semiconductor packages. In one embodiment, wire and/or ribbon bonding can be used to fabricate the shielding structure. For example, one or more wire and/or ribbon bonds can go from a connecting ground pad on one side of the package to a connecting ground pad on the other side of the package. This can be repeated multiple times at a pre-determined pitch necessary to meet the electrical requirements for shielding, e.g. less than or equal to approximately one half the wavelength of radiation generated by the electronic components being shielded.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Joshua Heppner, Mitul Modi
  • Patent number: 11011454
    Abstract: A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device comprising a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 18, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Katsuhiko Yoshihara, Masao Saito
  • Patent number: 11011447
    Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hua Wang, Po-Yao Lin, Feng-Cheng Hsu, Shin-Puu Jeng, Wen-Yi Lin, Shu-Shen Yeh
  • Patent number: 11004777
    Abstract: In one general aspect, an apparatus can include a leadframe including a plurality of leads configured to provide electrical connections for the apparatus. The apparatus can also include a semiconductor die disposed on the leadframe and a conductive clip electrically coupling the semiconductor die with the leadframe. The apparatus can further include a heat slug disposed on the conductive clip. The heat slug can include a thermally conductive and electrically insulative material.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jerome Teysseyre, Chung-Lin Wu, Bigildis Dosdos
  • Patent number: 10973113
    Abstract: A component carrier with a stack including a plurality of electrically conductive layer structures and/or electrically insulating layer structures, and a first transistor component and a second transistor component embedded side-by-side in the stack.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 6, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gerald Weis, Christian Vockenberger
  • Patent number: 10873244
    Abstract: An electronic module is provided for a power tool having an electric motor. The module includes a printed circuit board (PCB) having a first surface and a second surface; first set of power switches mounted on the first surface of the PCB; second set of power switches mounted on the PCB and electrically coupled to the first power switches forming an inverter bridge circuit for driving the electric motor; a first heat sink surface-mounted on the first surface of the PCB and having a planar main body disposed over the first power switches; a module housing arranged to receive the PCB therein; and a second heat sink secured to the module housing in thermal communication with the first heat sink to transfer heat from the first power switches.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: December 22, 2020
    Assignee: Black & Decker Inc.
    Inventors: Madhur M. Purohit, Joshua M. Lewis, Marcell E. Coates, Michael D. Grove, Victor A. Dorado
  • Patent number: 10861801
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu
  • Patent number: 10849225
    Abstract: A printed circuit board includes a first insulating layer, an embedded pattern embedded in one surface of the first insulating layer, a pad formed on the one surface of the first insulating layer, and a post, wherein the center of a side surface of the post is in contact with the one surface of the first insulating layer.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 24, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young-Kuk Ko, Yoong Oh, Sang-Hoon Kim, Gyu-Mook Kim, Yong-Soon Jang, Hea-Sung Kim
  • Patent number: 10840165
    Abstract: An electronics package includes a thermal lid over a flip chip component such that the thermal lid is in contact with a surface of a flip chip component and one or more thermal vias in a substrate on which the flip chip component is mounted. The thermal lid dissipates heat from the flip chip component by way of the thermal vias to improve the thermal performance of the electronics package.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: November 17, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Jonathan J. Fain, Mark C. Woods
  • Patent number: 10794561
    Abstract: A vehicle lamp includes a projector lens, a first light source disposed behind the projector lens and configured to emit light for forming a low-beam light distribution pattern, a second light source disposed behind the projector lens and configured to emit light for forming an additional high-beam light distribution pattern, and a metal base member. The base member includes a first surface on which the first light source is disposed and a second surface on which the second light source is disposed. The second surface is inclined with respect to an optical axis such that an emission portion of the light emitting element faces obliquely forward and upward. A plurality of metal plate-shaped fins extending in a left-right direction and an upper-lower direction of the lamp are arranged along a front-rear direction of the lamp on a rear surface of the first and second surfaces.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 6, 2020
    Assignee: KOITO MANUFACTURING CO., LTD.
    Inventors: Takashi Inoue, Kazushi Kawaguchi
  • Patent number: 10796979
    Abstract: A power module includes: a power chip; a control chip controlling the power chip; a power terminal connected to the power chip; a control terminal connected to the control chip; and a package covering the power chip, the control chip, the power terminal, and the control terminal with mold resin, wherein first and second recesses for attaching a fin are respectively provided on side faces facing each other of the package from which neither the power terminal nor the control terminal protrudes, and the first and second recesses are arranged not at positions opposite to each other but alternately.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 6, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Maki Hasegawa, Shuhei Yokoyama, Shigeru Mori, Hisashi Kawafuji
  • Patent number: 10741472
    Abstract: A power module includes: a power chip; a control chip controlling the power chip; a power terminal connected to the power chip; a control terminal connected to the control chip; and a package covering the power chip, the control chip, the power terminal, and the control terminal with mold resin, wherein first and second recesses for attaching a fin are respectively provided on side faces facing each other of the package from which neither the power terminal nor the control terminal protrudes, and the first and second recesses are arranged not at positions opposite to each other but alternately.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 11, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Maki Hasegawa, Shuhei Yokoyama, Shigeru Mori, Hisashi Kawafuji
  • Patent number: 10730016
    Abstract: The present invention relates to ultrafiltration. In particular, the present invention provides nanoporous membranes having pores for generating in vitro and in vivo ultrafiltrate, devices and bioartificial organs utilizing such nanoporous membranes, and related methods (e.g., diagnostic methods, research methods, drug screening). The present invention further provides nanoporous membranes configured to avoid protein fouling with, for example, a polyethylene glycol surface coating.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 4, 2020
    Assignees: The Regents of the University of Michigan, The Cleveland Clinic Foundation
    Inventors: William H. Fissell, Shuvo Roy, Aaron Fleischman, Kenneth G. Goldman
  • Patent number: 10714447
    Abstract: An electrode terminal includes a body and a first bonding part. The body includes a first metal material. Then, the first bonding part is bonded to one end of the body, and includes a second metal material which is a clad material other than the first metal material. The first bonding part is ultrasonically bondable to a first bonded member. An elastic part which is elastically deformable is provided between the one end of the body and the other end of the body.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rei Yoneyama, Yoshitaka Kimura, Akihiko Yamashita
  • Patent number: 10682792
    Abstract: The mold device according to the present invention is a mold device to resin-seal the semiconductor device including an insert electrode, and in the semiconductor device, the insert electrode is provided with an insert hole, a nut having a screw hole is disposed in the insert electrode so that the insert hole and the screw hole communicate with each other, the mold device includes a mold body into which resin is injected to resin-seal the semiconductor device, including a side of the insert electrode where the nut is disposed, and a rod-like member that is inserted into the insert hole, and the rod-like member is inserted into the screw hole of the nut through the insert hole of the insert electrode to draw the nut to the side of the insert electrode.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 16, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takatoshi Yasui, Yuki Hata, Shoji Saito, Katsuji Ando, Korehide Okamoto, Ryoji Murai
  • Patent number: 10685901
    Abstract: A boiling cooling device e includes a power semiconductor that is vertically disposed, heat radiating plates provided on both side faces of the power semiconductor, heat receiving jackets provided at both sides of the power semiconductor and covering the heat radiating plates, refrigerant filled in the heat receiving jackets and being in contact with the heat radiating plates, a condenser connected to the heat receiving jackets, and fine longitudinal grooves formed on a heat radiating face of the heat radiating plate and extending in a vertical direction, where creation of air bubbles is promoted by heat generated in the power semiconductor and by the fine longitudinal grooves, the created air bubbles rising and passing through a forward pipe and then reaching the condenser to be liquefied, such that liquid is returned to the heat receiving jacket via a return pipe.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: June 16, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Michiaki Hiyoshi
  • Patent number: 10643943
    Abstract: A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Tin-Hao Kuo
  • Patent number: 10622276
    Abstract: A power module capable of increasing structural stability and reliability at high temperatures includes: an upper substrate having a metal layer; a lower substrate spaced apart from the upper substrate and having a metal layer facing the metal layer of the upper substrate; a semiconductor element configured to be disposed between the upper substrate and the lower substrate; and at least one leg portion formed on at least one of the metal layer of the upper substrate and the metal layer of the lower substrate to make the upper substrate and the lower substrate be spaced apart from each other at a predetermined interval, in which the leg portion may be electrically connect the semiconductor element to the metal layer of the upper substrate or the metal layer of the lower substrate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 14, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Young Seok Kim, Hyun Woo Noh, Kyoung Kook Hong, Su Bin Kang
  • Patent number: 10575448
    Abstract: An apparatus for grounding a heat sink utilizing shape-memory alloy includes a printed circuit board, a logic chip, a heat sink, and a first grounding member, wherein the first grounding member is a shape-memory alloy. The apparatus further includes the logic chip electrically coupled to the printed circuit board and the heat sink disposed on a top surface of the logic chip. The apparatus further includes a first end of the first grounding member electrically coupled to the heat sink, wherein a second end of the grounding first member is disposed on a first ground land of the printed circuit board.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Theron L. Lewis, Timothy P. Younger, David J. Braun, James D. Bielick, Jennifer Bennett, Stephen M. Hugo, John R. Dangler
  • Patent number: 10546844
    Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Choon Kim, Eon-Soo Jang, Eun-Hee Jung, Hyon-Chol Kim, Byeong-Yeon Cho
  • Patent number: 10537044
    Abstract: A heat dissipating component comprising: a main body formed from a first material; a heat dissipating sheet that is formed from a second material having higher thermal conductivity than the first material, that is provided at the main body, and that includes a plurality of fins thermally connected to each other at positions other than apexes and a connecting portion thermally connecting the plurality of fins to an electronic component; and a covering portion that covers at least a portion of a bottom portion of a groove between the plurality of fins.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Suzuki, Kanae Nakagawa
  • Patent number: 10524392
    Abstract: A device can dissipate heat from an electrical component by using a phase change material. A horizontal circuitry layer can have opposing first and second sides. A vertical hole can extend through the horizontal circuitry layer. A vertical channel can include a phase change material positioned in the vertical hole and in thermal contact with the first and second sides of the horizontal circuitry layer. The phase change material can dissipate a first amount of heat from the first side by absorbing the first amount of heat and changing phase from a solid form to a liquid form. The phase change material, when in the liquid form, can dissipate a second amount of heat from the first side by transporting the second amount of heat via convection from the first side of the horizontal circuitry layer to the second side of the horizontal circuitry layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventor: Tsung-Yu Chen
  • Patent number: 10515826
    Abstract: The present invention provides a laminated member that prevents contact of a semiconductor chip and an external leading terminal etc. without increasing the number of components. The laminated member is a laminated member having a three-layer structure, comprising: an upper highly thermally conductive layer; a lower highly thermally conductive layer; and an intermediate layer having a low thermal expansion coefficient, wherein the above-described laminated member is larger than the above-described semiconductor chip in a plan view, and wherein a height position of the above-described first peripheral edge area is located at a certain distance below a height position of the above-described first bonding area, and a height position of the second peripheral edge area of the above-described second bonding area is located at a certain distance above a height position of the above-described second bonding area.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 24, 2019
    Assignee: Sansha Electric Manufacturing Co., Ltd.
    Inventors: Kazunori Inami, Takahiro Maruyama
  • Patent number: 10510634
    Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 10454415
    Abstract: An electrical box includes a first electrical component having an output terminal, and a second electrical component having an input terminal. A jumper is connected to the output terminal of the first electrical component and the input terminal of the second electrical component. The jumper defines a heat flow path between the first and second electrical components. The heat flow path defines a minimum path between the first and second electrical components along the heat flow path. A minimum distance along the minimum heat path between the first and second electrical components is greater than a minimum distance between first and second electrical components.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 22, 2019
    Assignee: Eaton Intelligent Power Limited
    Inventors: Adam Douglas Ledgerwood, Matthew Thomas Pernot, Arkadiusz Oskar Doroz
  • Patent number: 10438932
    Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 8, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jinchang Zhou, Yusheng Lin, Mingjiao Liu
  • Patent number: 10418536
    Abstract: The present disclosure provides a LED metal substrate and a LED module. An insulator is provided to cover an electrode or a side surface of a metal layer in the LED metal substrate, or provided on an original creepage path between the electrode and the metal layer in the LED metal substrate to form a new creepage path with increased creepage distance, in order to increase the breakdown voltage between the electrode and the metal layer. It is possible to avoid a phenomenon that an electric arc is generated between the electrode and the metal layer when a relative high voltage applied by the electrode during a breakdown test. So that the breakdown voltage of the LED metal substrate with an insulator reaches higher than that of a LED metal substrate without the insulator in the same dimension, and a technical problem in the art may be solved.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 17, 2019
    Assignee: KAISTAR LIGHTING (XIAMEN) CO., LTD.
    Inventors: Jingqiong Zhang, Shanshan Yang, Jinqiang Huang
  • Patent number: 10410971
    Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: David Fraser Rae, Hong Bok We, Christopher Healy, Chin-Kwan Kim
  • Patent number: 10403559
    Abstract: In a power semiconductor device, the thickness dimension of a protective film of a semiconductor element is made smaller than that of an upper electrode, so a protective film is not pressed by being pressurized from upward when bonded by a metal sintered body, and the force of tearing off the upper electrode riding on an inclined surface of the protective film does not act, so that no crack of the upper electrode occurs, thus maintaining the soundness of the semiconductor element. Also, a lead bonded by a solder to the upper electrode of the semiconductor element is made of a copper-Invar clad material, the linear expansion coefficient of which is optimized, and thereby it is possible to realize a durability superior to that of a heretofore known wire-bonded aluminum wiring.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 3, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masaru Fuku, Noriyuki Besshi, Ryuichi Ishii, Takayuki Yamada, Takao Mitsui, Komei Hayashi
  • Patent number: 10388639
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10347617
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10325855
    Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Kim, Jie Fu, Changhan Yun, Chin-Kwan Kim, Manuel Aldrete, Chengjie Zuo, Mario Velez, Jonghae Kim
  • Patent number: 10321554
    Abstract: The shape of an abutting portion where a heat sink and an electronic component or the heat sink and a connection wire abut against each other, through the intermediary of an intermediate member, is contrived so that there is provided an electronic control unit that can raise the easiness of production including the intermediate member, while securing the heat radiation performance. There is provided an electric power converter in which an intermediate member having an insulating property and a heat-conductive property is provided in a gap between a heat sink and a connection wire abutting portion or an electronic component, in which the top surface of a maximum heat generating component is a plane, and in which the portion, of the heat sink, that faces the top surface of the maximum heat generating component is part of a basic plane.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: June 11, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshihito Asao, Akihiko Mori
  • Patent number: 10290587
    Abstract: A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 14, 2019
    Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
    Inventors: Khai Ngo, Chi-Ming Wang, Han Cui
  • Patent number: 10290600
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
  • Patent number: 10249563
    Abstract: Provided is a multilayer wiring substrate capable of achieving excellent conduction reliability. The multilayer wiring substrate is formed by laminating an anisotropic conductive member including an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each conductive path has a protrusion protruding from the surface of the insulating base, and a wiring substrate having a substrate and one or more electrodes to be formed on the substrate, and conductive paths which come into contact with the electrode among the plurality of conductive paths are deformed so that adjacent conductive paths come into contact with each other.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Shunji Kurooka, Yoshinori Hotta
  • Patent number: 10186476
    Abstract: The present disclosure relates to a semiconductor package with at least one grounded fence to inhibit dendrites of die-attach materials. The semiconductor package includes a carrier, a die-attach material, and a wire-bonded die. The carrier includes a die pad and a negative carrier contact. The wire-bonded die includes a die body, a negative die contact, a grounded fence, and a bonding wire. A bottom surface of the die body is coupled to the die pad by the die-attach material. The negative die contact and the grounded fence reside over a top surface of the die body. The grounded fence, which has a same DC potential as the die pad, extends between the negative die contact and a periphery of the top surface of the die body. The bonding wire extends from the negative die contact to the negative carrier contact.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 22, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Larry Wall, Christopher Sanabria
  • Patent number: 10174927
    Abstract: An LED illumination device includes an LED device; a base having a concavity for receiving the LED device; a heat sink including a plate coupled to the base and a plurality of fins extending from a surface of the plate opposite the base, the fins extending laterally beyond sides of the plate; a cooling fan for forcing air over the fins; and a casing housing the LED substrate, the base, the heat sink, and the cooling fan.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: January 8, 2019
    Assignees: ACP JAPAN CO., LTD.
    Inventor: Shoichi Nakamura