Directly Attached To Semiconductor Device Patents (Class 257/707)
  • Patent number: 10347617
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10325855
    Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Kim, Jie Fu, Changhan Yun, Chin-Kwan Kim, Manuel Aldrete, Chengjie Zuo, Mario Velez, Jonghae Kim
  • Patent number: 10321554
    Abstract: The shape of an abutting portion where a heat sink and an electronic component or the heat sink and a connection wire abut against each other, through the intermediary of an intermediate member, is contrived so that there is provided an electronic control unit that can raise the easiness of production including the intermediate member, while securing the heat radiation performance. There is provided an electric power converter in which an intermediate member having an insulating property and a heat-conductive property is provided in a gap between a heat sink and a connection wire abutting portion or an electronic component, in which the top surface of a maximum heat generating component is a plane, and in which the portion, of the heat sink, that faces the top surface of the maximum heat generating component is part of a basic plane.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: June 11, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshihito Asao, Akihiko Mori
  • Patent number: 10290600
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
  • Patent number: 10290587
    Abstract: A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 14, 2019
    Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
    Inventors: Khai Ngo, Chi-Ming Wang, Han Cui
  • Patent number: 10249563
    Abstract: Provided is a multilayer wiring substrate capable of achieving excellent conduction reliability. The multilayer wiring substrate is formed by laminating an anisotropic conductive member including an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each conductive path has a protrusion protruding from the surface of the insulating base, and a wiring substrate having a substrate and one or more electrodes to be formed on the substrate, and conductive paths which come into contact with the electrode among the plurality of conductive paths are deformed so that adjacent conductive paths come into contact with each other.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Shunji Kurooka, Yoshinori Hotta
  • Patent number: 10186476
    Abstract: The present disclosure relates to a semiconductor package with at least one grounded fence to inhibit dendrites of die-attach materials. The semiconductor package includes a carrier, a die-attach material, and a wire-bonded die. The carrier includes a die pad and a negative carrier contact. The wire-bonded die includes a die body, a negative die contact, a grounded fence, and a bonding wire. A bottom surface of the die body is coupled to the die pad by the die-attach material. The negative die contact and the grounded fence reside over a top surface of the die body. The grounded fence, which has a same DC potential as the die pad, extends between the negative die contact and a periphery of the top surface of the die body. The bonding wire extends from the negative die contact to the negative carrier contact.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 22, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Larry Wall, Christopher Sanabria
  • Patent number: 10174927
    Abstract: An LED illumination device includes an LED device; a base having a concavity for receiving the LED device; a heat sink including a plate coupled to the base and a plurality of fins extending from a surface of the plate opposite the base, the fins extending laterally beyond sides of the plate; a cooling fan for forcing air over the fins; and a casing housing the LED substrate, the base, the heat sink, and the cooling fan.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: January 8, 2019
    Assignees: ACP JAPAN CO., LTD.
    Inventor: Shoichi Nakamura
  • Patent number: 10177067
    Abstract: A manufacturing method including following steps is provided. A substrate that includes a core layer, a first conductive layer, and a second conductive layer is provided. A heat conducting channel is formed in the substrate, and an adhesion layer is formed on the second conductive layer to cover a side of the heat conducting channel. A heat conducting element and a buffer layer are placed into the heat conducting channel, and a gap is formed between either the heat conducting element or the buffer layer and an inner side surface of the heat conducting channel. The gap is filled with a first insulant material, and the adhesion layer and the buffer layer are removed to form a cavity and expose the heat conducting element. The first conductive layer and the second conductive layer are patterned to form a first patterned circuit layer and a second patterned circuit layer, respectively.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: January 8, 2019
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chin-Sheng Wang, Chih-Hsien Cheng, Shih-Hao Sun
  • Patent number: 10143092
    Abstract: A circuit substrate includes a core substrate having a cavity penetrating through the substrate, a metal block accommodated in the cavity of the substrate, a first build-up layer laminated on first side of the substrate and including insulating resin layers such that the first build-up layer is covering first surface of the block from the first side, and a second build-up layer laminated on second side of the substrate and including insulating resin layers such that the second build-up layer is covering second surface of the block from the second side. The first build-up layer includes an electronic component mounting structure formed on outermost portion of the first build-up layer, and the block is formed such that the first and second surfaces have roughened surfaces, respectively, and that the roughened surface of the first surface has surface roughness different from surface roughness of the roughened surface of the second surface.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: November 27, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Yukinobu Mikado, Mitsuhiro Tomikawa, Koji Asano, Kotaro Takagi
  • Patent number: 10130013
    Abstract: A data center cooling system includes an outer container that defines a first volume; an inner container that defines a second volume and is positioned within the first volume, the inner container including an air outlet that includes an airflow path between the first and second volumes; a liquid seal to fluidly isolate a liquid phase of a non-conductive coolant that fills at least a portion of the first and second volumes from an ambient environment; and a plurality of electronic heat-generating devices at least partially immersed in the liquid phase of the non-conductive coolant to transfer a heat load to the non-conductive coolant.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: November 13, 2018
    Assignee: Google LLC
    Inventors: Madhu Krishnan Iyengar, Christopher G. Malone, Gregory P. Imwalle
  • Patent number: 10121723
    Abstract: According to an embodiment of a method, the method includes forming a first thermally conductive layer on an outer surface of a semiconductor package. The first thermally conductive layer formed on the outer surface of the semiconductor package is configured to be mounted to an external heat sink.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: November 6, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Kok Tee Lau, Jayaganasan Narayanasamy
  • Patent number: 10083912
    Abstract: A package substrate having an opening and through-substrate interconnect structures is attached to a temporary carrier such as an adhesive film. The active surface of an IC die is placed in contact with the carrier substrate within the opening, to temporarily attach the die to the carrier substrate. Another die is attached to the side of the first die furthest from the carrier substrate. In one embodiment, the dies are attached to each other using an epoxy so that their respective non-active surfaces face each other. Bond wires are connected between interconnects at the active surface of the second die and the substrate. The wires are then encapsulated. After removal of the carrier substrate, a build-up interconnect structure is formed that includes external interconnects of the package substrate, such as solder balls of a ball grid array package.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: September 25, 2018
    Assignee: NXP USA, INC.
    Inventors: Zhiwei Gong, Wei Gao
  • Patent number: 10083919
    Abstract: Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shidong Li
  • Patent number: 10032648
    Abstract: A maximum length of a heat sink is set as “L” and a warp amount of the heat sink is set as “Z”; the warp amount “Z” is set as a positive value if a bonded surface of the heat sink to a metal layer is deformed to be concave or the warp amount “Z” is set as a negative value if the bonded surface is deformed to be convex; a ratio Z/L of the maximum length “L” and the warp amount “Z” measured at 25° C. is in a range not smaller than ?0.005 and not larger than 0.005, and the ratio Z/L is in the range not smaller than ?0.005 and not larger than 0.005 even when it is heated to 280° C. and then cooled to 25° C.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: July 24, 2018
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Tomoya Oohiraki, Sotaro Oi
  • Patent number: 10026672
    Abstract: A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 17, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Florian G. Herrault, Miroslav Micovic
  • Patent number: 10012803
    Abstract: This optical fiber connection structure connects a multicore fiber and a bundle structure bundling a plurality of optical fibers. The multicore fiber has a plurality of cores arranged in a lattice. The bundle structure includes closely packed optical fibers of the same diameter. The bundle structure is configured such that signal light optical fiber groups including signal light optical fibers and a dummy fiber group including dummy optical fibers are stacked in multiple layers. The signal light optical fiber groups are configured with the signal light optical fibers aligned in the mutually contacting direction. The signal light optical fiber groups and the dummy fiber group are stacked orthogonal to the alignment direction of the optical fibers constituting the respective fiber groups.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: July 3, 2018
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kengo Watanabe, Tsunetoshi Saito
  • Patent number: 9992912
    Abstract: The present invention provides a heat dissipating device combined structure, which consists of a heat sink and a clasp member. At least one expanded portion extends from the heat sink, and a side extends from each of the two sides of a base of the clasp member to form a conduit. The heat sink and a circuit board are disposed inside the conduit, and at least one ledge portion is formed on the sides. Moreover, a slanting portion extends from and is provided on air foils configured on the sides, and the ends of the slanting portions respectively clasp the expanded portions. Accordingly, the circuit board is mounted on the ledge portions, and electronic components on the circuit board are attached to the bottom portion of the aforementioned heat sink.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 5, 2018
    Assignee: LIANCHUN INDUSTRIAL CO., LTD.
    Inventor: Chun-Chieh Wang
  • Patent number: 9953903
    Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: April 24, 2018
    Assignee: NXP B.V.
    Inventors: Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis, Rintje van der Meulen, Emil Casey Israel
  • Patent number: 9955591
    Abstract: A circuit substrate includes a core substrate having a cavity penetrating through the substrate, a combined component accommodated in the cavity of the substrate, a first build-up layer laminated on first surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, a second build-up layer laminated on second surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, and a filling resin filling gap formed between the cavity and combined component accommodated in the cavity of the substrate. The combined component includes an electronic component and a metal block, the electronic component has terminal surface on side facing the first surface of the substrate, and the metal block is superposed to surface of the electronic component on the opposite side of the electronic component with respect to the terminal surface.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: April 24, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Mitsuhiro Tomikawa, Koji Asano
  • Patent number: 9865528
    Abstract: A cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the method comprises attaching a metal heat sink to a leadframe using an intermediate structure that is thermally conductive and electrically insulating; molding a plastic body around the heat sink and exposed leads of the leadframe to form a cavity, with partially and selectively exposed lead top surfaces, heat sink top surface, and heat sink bottom surface; attaching a semiconductor device die within cavity on to the exposed top surface of the heat sink using a thermal conductive material; wire bonding respective wire bond pads of the semiconductor device die to the exposed lead top surfaces and to the heat sink for grounding; and attaching a lid to the plastic molded body to protect the wire bonded device within cavity.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 9, 2018
    Assignee: UBOTIC COMPANY LIMITED
    Inventors: Zhang Xiao Ping, Sin Chi Wai
  • Patent number: 9837394
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: December 5, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 9806001
    Abstract: A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 31, 2017
    Assignee: Volterra Semiconductor LLC
    Inventors: Mihalis Michael, Ilija Jergovic
  • Patent number: 9791899
    Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Gong Ouyang, Kai Xiao, Lu-Vong Phan
  • Patent number: 9769361
    Abstract: An assembly structure for industrial camera has a camera module including an electric circuit board and a sensor component configured on the electric circuit board, a base of a camera seat combined onto the electric circuit board, a protrusive and hollow engaging portion installed on the surface of the base, an installation hole combined with a predetermined lens installed in the engaging portion, and a lens hole creating a closure state configured at the bottom of the installation hole.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 19, 2017
    Assignee: Adlink Technology Inc.
    Inventor: Chie-Ta Lee
  • Patent number: 9741635
    Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, means for a spreading heat in directions substantially parallel to a major surface of the one or more semiconductor dice embedded in a second dielectric layer and means for dissipating heat in directions substantially perpendicular to the major surface of the one or more semiconductor dice.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 9728487
    Abstract: An object of the present invention is to improve the reliability of a semiconductor device having an imaging function. A semiconductor device includes a package having a cavity and terminals (TE1), a semiconductor chip that has an imaging unit and is arranged in the cavity, and a cap material with which the cavity is sealed and which has translucency. In addition, the semiconductor device includes a mounting board that has a through-hole and terminals (TE2) and is arranged so as to electrically couple the terminals (TE1) to the terminals (TE2), a heat transfer member that is inserted into the through-hole and is coupled to the package, and a heat sink coupled to the heat transfer member.
    Type: Grant
    Filed: April 9, 2016
    Date of Patent: August 8, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Karashima, Yumi Imamura, Yosuke Imazeki
  • Patent number: 9716051
    Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: July 25, 2017
    Assignee: NVIDIA Corporation
    Inventors: Leilei Zhang, Ron Boja, Abraham Yee, Zuhair Bokharey
  • Patent number: 9698783
    Abstract: Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: July 4, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Wen Li, Norio Chujo, Masami Makuuchi, Takehito Kamimura
  • Patent number: 9673129
    Abstract: In a semiconductor device, an insulated substrate is bonded with a cooling body with lowered thermal resistance without a holding unit. The semiconductor device includes an insulated substrate where a wiring pattern copper plate unit for forming a plurality of wiring patterns is disposed on one side of an insulating plate unit, and a heat radiation copper plate unit disposed on the other side of the insulating plate unit; a semiconductor chip mounted on the wiring pattern copper plate unit; a cooling body contacted with the heat radiation copper plate unit; and a wiring conductor plate connected between the semiconductor chip and the wiring pattern copper plate unit. The heat radiation copper plate unit and the cooling body are bonded with a metal sintered material, and thicknesses of the wiring pattern copper plate unit and the heat radiation copper plate unit are set to such thermal stress is relaxed.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: June 6, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshikazu Takahashi, Yoshitaka Nishimura, Yoshinari Ikeda, Hiromichi Gohara
  • Patent number: 9638596
    Abstract: A cavity-down pressure sensor device has a pressure-sensing die that is electrically connected to a master control unit (MCU) using face-to-face bonding. Connecting the pressure-sensing die in this manner avoids the need to wire bond the pressure-sensing die to the master control unit.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: May 2, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Wai Yew Lo
  • Patent number: 9627293
    Abstract: In a conventional semiconductor device, a pattern serving as a heat dissipating material is formed by applying a phase transition material. Provided is a semiconductor device that can reduce collapse of a pattern shape even if a shock is applied to the pattern formed with the phase transition material that is liquefied when the environmental temperature is not sufficiently controlled. The semiconductor device includes semiconductor elements mounted inside a semiconductor module (10); a heat radiating surface (13), formed in the semiconductor module (10), dissipating heat generated in the semiconductor elements to a heat radiator; a pattern (14) formed on the heat radiating surface and made from a phase transition material; and a film (15) serving as a first film that covers the pattern (14).
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 18, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rei Yoneyama, Kozo Harada, Isao Oshima, Yoshitaka Otsubo, Rena Kawahara
  • Patent number: 9625186
    Abstract: A system and method of cooling a three dimensional integrated circuit (3D IC) using at least one thermoelectric cooler which is connected to the 3D IC by a plurality of conductive pillars. In some embodiments a controller controls power supply to the thermoelectric cooler, and a temperature monitor provides a temperature input to the controller. In some embodiments the controller maintains a temperature of a 3D IC within a predetermined range by cycling power to the thermoelectric cooler.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Cheng Chou, Po-Hao Lee, Jonathan Tehan Chen
  • Patent number: 9601407
    Abstract: A system-in-package (SiP) module is disclosed. The SiP module includes a substrate and a dam on the substrate. The dam defines a cavity. At least one chip is on the substrate inside the cavity. A printed circuit board (PCB) is bonded to the dam and covers the cavity. A thermal conductive sheet is in the cavity and is disposed between the chip and the PCB. The chip is in thermal contact with the PCB through the thermal conductive sheet. The disclosure also provides a method for manufacturing the SiP module.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: March 21, 2017
    Assignee: QUANTA COMPUTER INC.
    Inventor: Li-Cheng Shen
  • Patent number: 9589860
    Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9583409
    Abstract: A resin-sealed module is provided which reduces the warpage of a substrate and the detachment between a sealing resin and the substrate which occur during re-reflow, has the excellent flatness of the top and bottom surfaces, and reduces the occurrence of the short failures. A resin layer made of a thermoplastic resin is arranged on top of a substrate, and a resin layer made of a thermosetting resin is arranged on top of this resin layer, thereby reducing the warpage of the substrate and the detachment between the sealing resin and the substrate which occur during re-reflow.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: February 28, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuo Yokoyama, Tetsuya Kitaichi
  • Patent number: 9559034
    Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: January 31, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Tarak A. Railkar, Deep C. Dumka
  • Patent number: 9548285
    Abstract: Reliability of a semiconductor device is improved. A method of manufacturing the semiconductor device includes a step of cutting a tab suspension lead from a tab suspension lead support portion connected to an outer frame of a lead frame by inserting a jig between two adjacent sealing bodies, the jig having almost the same width as a gap between the adjacent sealing bodies. And, a notch is formed in the tab suspension lead, and the notch is arranged at a position intersecting a side of a sealing body, so that the tab suspension lead is cut at a part of the notch in the step of cutting the tab suspension lead.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 17, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Ryoichi Shigematsu
  • Patent number: 9508700
    Abstract: The present invention relates to a semiconductor device used in power equipment. The semiconductor device includes: a base plate; an insulating substrate mounted on the base plate; a power switching element bonded to the insulating substrate with a solder layer; and the base plate, the insulating substrate, and the power switching element forming a module, a control substrate located above the module. The control substrate includes a variable gate voltage circuit measuring a collector-emitter voltage of the power switching element and changing a gate voltage such that the power switching element is supplied with given target power determined by a product of the collector-emitter voltage and a collector current.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideo Komo, Takeshi Omaru, Shoji Saito
  • Patent number: 9484279
    Abstract: A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: November 1, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Flynn Carson, Seung Uk Yoon
  • Patent number: 9485878
    Abstract: The present invention relates to a substrate structure having electronic components and a method of manufacturing a substrate structure having electronic components and can reduce signal loss and internal resistance and improve process efficiency by bringing a first terminal of a first electronic component and a second terminal of a second electronic component in direct contact with each other or in direct contact with each other by solder to minimize a path between the electronic components.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 1, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jae Soo Lee
  • Patent number: 9478478
    Abstract: Electronic device assemblies employing dual phase change materials and vehicles incorporating the same are disclosed. In one embodiment, an electronic device assembly includes a semiconductor device having a surface, wherein the semiconductor device operates in a transient heat flux state and a normal heat flux state, a coolant fluid thermally coupled to the surface of the semiconductor device, and a phase change material thermally coupled to the surface of the semiconductor device. The phase change material has a phase change temperature at which the phase change material changes from a first phase to a second phase. The phase change material absorbs heat flux at least when the semiconductor device operates in the transient heat flux state.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 25, 2016
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Ercan Mehmet Dede
  • Patent number: 9460979
    Abstract: An electronic device includes a semiconductor module, a wiring substrate, a case member and a heat conducting member. The heat conducting member thermally connects predetermined portions of wiring patterns and a heat conducting pattern of the wiring substrate to a predetermined heat conduction region of a surface of the case member opposing to the wiring substrate. The predetermined heat conduction region is located further from the wiring substrate than a surface of a body portion opposing to the case member. As a result, heat can be radiated and a short can be restricted with the case member having a simple shape. The heat conducting pattern is disposed adjacent to at least one of non-terminal projecting surfaces of the body portion on a surface of the wiring substrate. As a result, an area of a heat conducting passage increases and heat radiation performance can be increased.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 4, 2016
    Assignee: DENSO CORPORATION
    Inventor: Seiji Morino
  • Patent number: 9425123
    Abstract: An electronic device includes a semiconductor module, a wiring substrate, a case member and a heat conducting member. The heat conducting member thermally connects predetermined portions of wiring patterns and a heat conducting pattern of the wiring substrate to a predetermined heat conduction region of a surface of the case member opposing to the wiring substrate. The predetermined heat conduction region is located further from the wiring substrate than a surface of a body portion opposing to the case member. The heat conducting pattern is disposed adjacent to at least one of non-terminal projecting surfaces of the body portion on a surface of the wiring substrate. The heat conducting pattern has a surface that is not covered with solder resist at least at a part. As a result, an area of a heat conducting passage increases and heat radiation performance can be increased.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 23, 2016
    Assignee: DENSO CORPORATION
    Inventor: Seiji Morino
  • Patent number: 9412685
    Abstract: A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically connected to the plurality of external terminals on a front surface, a semiconductor chip mounted on the front surface of the substrate, a surface of the chip including a plurality of bonding pads, a plurality of bonding wires connecting between the plurality of bonding pads or between the plurality of bonding terminals and the plurality of bonding wires respectively, a first sealing layer sealing the front surface of the substrate, the plurality of bonding wires and the semiconductor chip, and a second sealing layer comprised of the same material as the first sealing, the second sealing layer being formed above the first sealing layer.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: August 9, 2016
    Assignee: J-DEVICES CORPORATION
    Inventors: Yoshiyuki Tomonaga, Mitsuru Ooida, Katsumi Watanabe, Hidenari Sato
  • Patent number: 9406619
    Abstract: A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Dioscoro A. Merilo
  • Patent number: 9406650
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Wen-Chih Chiou, Tu-Hao Yu, Hung-Jung Tu, Yu-Liang Lin, Shih-Hui Wang
  • Patent number: 9401315
    Abstract: A semiconductor device package which includes a semiconductor package, a semiconductor device joined to the semiconductor package; and a lid to be placed over the semiconductor device and joined to the semiconductor package. The lid includes: a block of a first material having a first surface and a second surface, the second surface facing the semiconductor device, the block having perforations extending between the first surface and the second surface; inserts for filling the perforations, each of the inserts being made of a second material, at least one of the inserts protrudes beyond the second surface towards the semiconductor device; and a bonding material to bond the inserts to the block so that the at least one of the inserts protrudes beyond the second surface towards the semiconductor device. Also included is a method of assembling a semiconductor device package.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: July 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Paul F. Bodenweber, Taryn J. Davis, Marcus E. Interrante, Chenzhou Lian, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Hilton T. Toy
  • Patent number: 9355952
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Patent number: 9331053
    Abstract: Various stacked semiconductor chip arrangements and methods of manufacturing the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip, a second semiconductor chip mounted on the first semiconductor chip, and a first portion of a phase change material positioned in a first pocket associated with the first semiconductor chip or the second semiconductor chip to store heat generated by one or both of the first and second semiconductor chips.
    Type: Grant
    Filed: August 31, 2013
    Date of Patent: May 3, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manish Arora, Nuwan Jayasena, Gabriel H. Loh, Michael J. Schulte