Directly Attached To Semiconductor Device Patents (Class 257/707)
  • Publication number: 20140239481
    Abstract: Provided herein are electronic devices assembled with thermally insulating layers.
    Type: Application
    Filed: May 1, 2014
    Publication date: August 28, 2014
    Applicants: Henkel IP & Holding GmbH, Henkel AG & Co. KGaA
    Inventors: My Nhu Nguyen, Emilie Barriau, Martin Renkel, Matthew J. Holloway, Jason Brandi
  • Patent number: 8815646
    Abstract: A semiconductor device is formed by molding using a resin with a semiconductor element and one or two heat dissipating plates contained therein, said one or two heat dissipating plates being disposed to face one surface or both the surfaces of the semiconductor element. An intermediate layer is formed by spraying a metal powder to the semiconductor element and to one of or both of the heat dissipating plates using a cold spray method, and the semiconductor element and the heat dissipating plate are bonded together using a solder with the intermediate layer therebetween.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hirotaka Ohno
  • Patent number: 8806749
    Abstract: Cooling apparatuses, cooled electronic modules and methods of fabrication are provided for fluid immersion-cooling of an electronic component(s). The method includes, for instance: securing a housing about an electronic component to be cooled, the housing at least partially surrounding and forming a compartment about the electronic component to be cooled; disposing a fluid within the compartment, wherein the electronic component to be cooled is at least partially immersed within the fluid, and wherein the fluid comprises water; and providing a deionizing structure within the compartment, the deionizing structure comprising deionizing material, the deionizing material ensuring deionization of the fluid within the compartment, wherein the deionizing structure is configured to accommodate boiling of the fluid within the compartment.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Levi A. Campbell, Richard C. Chu, Milnes P. David, Michael J. Ellsworth, Madhusudan K. Iyengar, Robert E. Simons, Prabjit Singh
  • Patent number: 8803313
    Abstract: A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: August 12, 2014
    Assignee: Cree, Inc.
    Inventors: Umesh Mishra, Primit Parikh, Yifeng Wu
  • Patent number: 8796843
    Abstract: High-power and high-frequency semiconductor devices require high signal integrity and high thermal conductance assembly technologies and packages. In particular, wide-gap-semiconductor devices on diamond benefit from spatially separate electrical and thermal connections. This application discloses assembly and package architectures that offer high signal integrity and high thermal conductance.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: August 5, 2014
    Assignee: Element Six Technologies US Corporation
    Inventors: Dubravko I. Babic, Quentin E. Diduck, Alex Schreiber
  • Patent number: 8796840
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8791564
    Abstract: In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: July 29, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hiroki Mizuno
  • Patent number: 8786077
    Abstract: Certain embodiments provide a semiconductor device including a first substrate, a circuit element, a second substrate, a metal layer, and a radiation plate. The circuit element is formed on a front surface of the first substrate and has an electrode. The second substrate has a first face, and is laminated on the first substrate so that the first face of the second substrate faces a front surface of the first substrate. The second substrate has a via hole arranged on the electrode. The metal layer is formed inside of the via hole. The radiation plate is formed on a second face of the second substrate, and is connected to the metal layer.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jeoungchill Shim
  • Patent number: 8785974
    Abstract: A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: July 22, 2014
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao
  • Patent number: 8786076
    Abstract: A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 22, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: OhHan Kim, YongHee Kang, KyungHoon Lee
  • Patent number: 8779603
    Abstract: Provided is a stacked semiconductor device (50) in which a semiconductor package (5) is stacked via connection terminals (8) on a semiconductor package (1), including a heat dissipating member (10) which is disposed between the semiconductor packages (1, 5), is brought into thermal contact with both of the packages (1, 5), and hangs over whole outer peripheral portions of the package (5). Such a structure causes heat generated from the package (5) to be released by heat dissipation into air above the package (5), heat dissipation into the air below the semiconductor package (5), heat transfer via the heat dissipating member (10) and a semiconductor element (3) to a first wiring substrate (2), heat transfer via the connection terminals (8) to the first wiring substrate (2), and heat dissipation via the heat dissipating member (10) into the air, thereby enhancing a temperature reduction effect of the semiconductor element.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takehiro Suzuki
  • Patent number: 8779444
    Abstract: An L.E.D. lamp assembly (20) includes an electrically insulative coating (24) disposed on a thermally conductive substrate (22). A plurality of light emitting diodes (26) are secured to the coating (24) and a circuit (40) is adhesively secured to the coating (24) in predetermined spaced lengths (42) along the coating (24) to establish discrete and electrically conductive spaced lengths (42) with the light emitting diodes (26) disposed between the spaced lengths (42). LED electrical leads (32) are secured to the spaced lengths (42) of the circuit (40) to electrically interconnect the light emitting diodes (26). The circuit (40) includes a foil tape (46) having an electrically conductive tape portion (48) and a coupling portion (50) disposed on the tape portion (48) for securing the foil tape (46) to the insulated substrate (22).
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: July 15, 2014
    Assignee: Relume Technologies, Inc.
    Inventor: Peter A. Hochstein
  • Patent number: 8779580
    Abstract: An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: July 15, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Joon-Seok Kang, Sung Yi, Jae-Cheon Doh, Do-Jae Yoo, Sun-Kyong Kim, Jong-Hwan Baek
  • Patent number: 8773857
    Abstract: A heat sink mounting device includes a touching plate and a mounting member. The touching plate defines a locking hole. The mounting member includes a locking post. The locking post includes a body and two protrusions protruding from the body. An inner surface of the locking hole defines two cutouts. The touching plate includes two blocking blocks extending from an edge of the locking hole on a bottom surface of the touching plate. The two protrusions extend out of the two cutouts and abut the bottom surface of the touching plate. One of the two protrusions is located between the two blocking blocks, to prevent the body from rotating freely in the locking hole.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: July 8, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Chih-Hao Yang, Xiang-Kun Zeng, Bao-Quan Shi, Jing-Jun Ni
  • Patent number: 8772927
    Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Raschid Jose Bezama, Evan George Colgan, Michael Gaynes, John Harold Magerlein, Kenneth C. Marston, Xiaojin Wei
  • Patent number: 8766416
    Abstract: A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Tsung-Hsien Hsu, Hao-Ju Fang, Hsin-Lung Chung
  • Patent number: 8767402
    Abstract: An electrical equipment casing includes a circuit board on which many electrical parts are mounted and a heat sink to which the circuit board is fixed. The heat sink is provided with a reactor housing dent that opens in a surface on which the circuit board is placed and radiator fins that reach a bottom portion of the reactor housing dent on a surface opposite to the surface on which the circuit board is placed at a position surrounding an outer circumference of the reactor housing dent. The reactor is housed in the reactor housing dent and a terminal thereof is electrically connected to the circuit board. This structure of the electrical equipment casing can contribute to an achievement of both of a size reduction of the overall casing and enhanced heat dissipation of the reactor.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: July 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mitsuo Sone, Nobuhiro Kihara, Naoki Itoi, Fumito Uemura
  • Patent number: 8749051
    Abstract: A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 10, 2014
    Assignee: ABB Research Ltd
    Inventors: Slavo Kicin, Nicola Schulz, Munaf Rahimo, Raffael Schnell
  • Patent number: 8746308
    Abstract: In a manufacturing method of a package carrier, a substrate including a first metal layer, a second metal layer having a top surface and a bottom surface opposite to each other, and an insulating layer between the first and second metal layers is provided. The second metal layer has a greater thickness than the first metal layer. A first opening passing through the first metal layer and the insulating layer and exposing a portion of the top surface of the second metal layer is formed. The first metal layer is patterned to form a patterned conductive layer. Second openings are formed on the bottom surface of the second metal layer. The second metal layer is divided into thermal conductive blocks by the second openings that do not connect the first opening. A surface passivation layer is formed on the patterned conductive layer and the exposed portion of the top surface.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: June 10, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Shih-Hao Sun
  • Patent number: 8749977
    Abstract: A power semiconductor module includes: a first metal substrate on which a power semiconductor device is mounted; a second metal substrate on which a power semiconductor device is not mounted; and an electrically insulating resin package which seals the first metal substrate and the second metal substrate. The back surface of the first metal substrate on the side opposite to the mounting surface of the power semiconductor device is made to expose outside the resin package to form a heat dissipation surface.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinsuke Asada, Yuetsu Watanabe, Yoshihito Asao, Kenjiro Nagao
  • Patent number: 8736047
    Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Hideaki Yoshimi, Mitsuo Umemoto, Kazumi Onda, Kazumi Horinaka
  • Patent number: 8736048
    Abstract: A multi-chip module (MCM) structure comprises more than one semiconductor chip lying in a horizontal plane, the MCM having individual chip contact patches on the chips and a flexible heat sink having lateral compliance and extending in a plane in the MCM and secured in a heat exchange relation to the chips through the contact patches. The MCM has a mismatch between the coefficient of thermal expansion of the heat sink and the MCM and also has chip tilt and chip height mismatches. The flexible heat sink with lateral compliance minimizes or eliminates shear stress and shear strain developed in the horizontal direction at the interface between the heat sink and the chip contact patches by allowing for horizontal expansion and contraction of the heat sink relative to the MCM without moving the individual chip contact patches in a horizontal direction.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventor: Mark D. Schultz
  • Patent number: 8736044
    Abstract: To minimize the warpage of an organic substrate that supports at least one electrical hardware component (e.g., a system-in-package module), a bottom surface of a lid is attached to a top surface of the electrical hardware component. The lid includes a leg that extends from the bottom surface of the lid towards a top surface of the substrate. A portion of the leg closest to the substrate may move relative to the substrate. As the lid warps, the lid does not also cause distortion of the substrate. The leg may be a flange that extends at least a portion of the width or at least a portion of the length of the lid, may be a post located at the perimeter of the lid, or may be any other portion extending from above the electrical component towards the substrate.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: May 27, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Mudasir Ahmad, Kuo-Chuan Liu, Mohan Nagar, Bangalore Shanker
  • Patent number: 8730676
    Abstract: A composite component includes a first joining partner, at least one second joining partner and a first joining layer situated between the first joining partner and the second joining partner. In addition to the first joining layer, at least one second joining layer is provided between the first and the second joining partner; and at least one intermediate layer is situated between the first and the second joining layer.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: May 20, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Michele Hirsch, Michael Guenther
  • Patent number: 8723311
    Abstract: A device includes a first switch and a second switch, each switch being integrated on a chip having a back surface and an opposite front surface. Each chip includes a first conduction terminal and a control terminal on the front surface, while a second conduction terminal of the switch is located on the back surface. The first switch and the second switch are connected in a half-bridge configuration with the first switch's second conduction terminal electrically connected to the second switch's first conduction terminal. The chips are installed in a common package comprising an insulating body with an embedded heat sink. The chips of the switches are mounted on the heat sink such that the second conduction terminal of the first switch and the first conduction terminal of the second switch are in contact with the heat sink, with the heat sink providing the electrical connection between the two switches.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 13, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventor: Cristiano Gianluca Stella
  • Patent number: 8723317
    Abstract: A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 13, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8717766
    Abstract: A resin-sealed electronic controller obtained by bonding and fixing a circuit board to a thermally-conductive base plate, and integrating circuit components with a molding resin so as to reduce the size. A base plate includes a first exposed portion, a second exposed portion, and an adjacent flat portion adjacent to a central window hole. First circuit components which are low-heat-generating components with large height are located in the central window hole. Second circuit components which are high-heat-generating components with small height are provided on an area corresponding to the adjacent flat portion. A height dimension of the first circuit components at least partially overlaps a thickness dimension of the base plate, to reduce a total thickness dimension. The high-heat-generating components and the low-heat-generating components being provided separately from each other permits increased mounting density of low-heat-generating components, reducing an area of the circuit board.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 6, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Fumiaki Arimai, Hiroyoshi Nishizaki, Shozo Kanzaki
  • Patent number: 8710640
    Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 29, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: DaeSik Choi, JoungIn Yang, MinJung Kim, KyungEun Kim
  • Patent number: 8709197
    Abstract: A bonding material is placed on an electronic component. a heat conductive member is superposed on the surface of the bonding material so that a thermosetting adhesive is interposed between the heat conductive member and a substrate. The thermosetting adhesive is then cured at a temperature lower than the melting point of the bonding material. The bonding material melts after the thermosetting adhesive has cured. While a distance is maintained between the heat conductive member and the substrate, the thermosetting adhesive is cured. The heat conductive member is thus reliably prevented from a downward movement regardless of the melting of the bonding material. A space is maintained between the heat conductive member and the electronic component. The cured bonding material is reliably prevented from suffering from a reduction in the thickness.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Limited
    Inventor: Tsuyoshi So
  • Patent number: 8703286
    Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
  • Patent number: 8705239
    Abstract: A heat dissipation system for use with an electronic module is provided. The electronic module includes a first side with a first plurality of electronic components mounted thereon and a second side with a second plurality of electronic components mounted thereon. The heat dissipation system includes a first segment mountable on the module to be in thermal communication with at least one electronic component of the first plurality of electronic components. The system further includes a second segment mountable on the module to be in thermal communication with at least one electronic component of the second plurality of electronic components. The system includes a third segment mountable on the module to be in thermal communication with the first segment and with the second segment, the third segment providing a path through which heat flows from the first segment to the second segment.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: April 22, 2014
    Assignee: Netlist, Inc.
    Inventors: Enchao Yu, Zhiyong An
  • Patent number: 8692281
    Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: April 8, 2014
    Assignee: DiCon Fiberoptics Inc.
    Inventors: Wen-Herng Su, Junying Lu, Ho-Shang Lee
  • Patent number: 8686556
    Abstract: A process for forming a heat sink on a semiconductor package at the wafer level stage of manufacture is disclosed. A semiconductor component wafer, prior to separation into separate component packages, is covered on one side with a resin metal foil layer. The resin foil layer is patterned by laser ablation to define the heat sink locations, and then a thermal paste is applied over the patterned layer. The thermal conductive paste is hardened to form the heat sinks. The wafer can then be separated into packages.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: April 1, 2014
    Assignee: FlipChip International, LLC
    Inventors: David Clark, Theodore G. Tessier
  • Patent number: 8680666
    Abstract: A wire bond free power module assembly consists of a plurality of individual thin packages each consisting of two DBC wafers which sandwich one or more semiconductor die. The die electrodes and terminals extend through one insulation covered end of the wafer sandwich and the outer sides of the sandwiches are the outer copper plates of the DBC wafers which are in good thermal communication with the semiconductor die but are electrically insulated therefrom. The plural packages may be connected in parallel by lead frames on the terminals and the packages are stacked with a space between them to expose both sides of all packages to a cooling medium, either the fingers of a conductive comb or a fluid heat exchange medium.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: March 25, 2014
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 8674395
    Abstract: System and method for LED packaging. The present invention is directed to optical devices. More specifically, embodiments of the presentation provide LED packaging having one or more reflector surfaces. In certain embodiments, the present invention provides LED packages that include thermal pad structures for dissipating heat generated by LED devices. In particular, thermal pad structures with large surface areas are used to allow heat to transfer. In certain embodiments, thick thermally conductive material is used to improve overall thermal conductivity of an LED package, thereby allowing heat generated by LED devices to dissipate quickly. Depending on the application, thermal pad structure, thick thermal conductive layer, and reflective surface may be individually adapted in LED packages or used in combinations. There are other embodiments as well.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 18, 2014
    Assignee: Soraa, Inc.
    Inventor: Frank Tin Chung Shum
  • Patent number: 8674499
    Abstract: A heat radiation component configured to be provided through a thermal interface material on a semiconductor device mounted on a board includes a first layer to be positioned on a first side and a second layer stacked on the first layer to be positioned on a second side farther from the semiconductor device than the first side. The coefficient of thermal expansion of the second layer is lower than the coefficient of thermal expansion of the first layer.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: March 18, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Shigeaki Suganuma, Masakuni Kitajima, Ryuichi Matsuki, Hiroyuki Miyajima
  • Patent number: 8674492
    Abstract: A power module according to the present invention is a power module configured such that a power device chip is arranged within an outer casing and an electrode of the power device chip is connected to an external electrode that is integrated with the outer casing. The power module includes: a heat spreader fixed inside the outer casing; the power device chip solder-bonded on the heat spreader; an insulating dam formed on the heat spreader so as to surround the power device chip; and an internal main electrode having one end thereof solder-bonded to the electrode of the power device chip and the other end thereof fixed to an upper surface of the dam. The external electrode and the other end of the internal main electrode are electrically connected to each other by wire bonding.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: March 18, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuo Ota, Toshiaki Shinohara, Mamoru Terai, Hiroya Ikuta
  • Patent number: 8669646
    Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: March 11, 2014
    Assignee: Broadcom Corporation
    Inventors: Mohammad Tabatabai, Abbas Amirichimeh, Lorenzo Longo
  • Patent number: 8661660
    Abstract: A method for manufacturing an LED lamp assembly includes anodizing at least a portion of a surface of an electrically and thermally conductive base, such as an aluminum or aluminum alloy base, so as to form an electrically insulating coating. The base may form a heat sink or be coupled to a heat sink. The anodized surface is chemically etched and circuit traces that include an LED landing are formed on the etched anodized surface. LEDs are electrically and mechanically attached to the LED landing by way of conductive metallic solder such that heat generated from the LED is transferred efficiently through the solder and LED landing to the base and heat sink through a metal-to-metal contact pathway.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: March 4, 2014
    Assignee: The Artak Ter-Hovhanissian Patent Trust
    Inventor: Artak Ter-Hovhannissian
  • Patent number: 8659130
    Abstract: A power module includes: a sealing body including a semiconductor element having a plurality of electrode surfaces, a first conductor plate connected to one electrode surface of the semiconductor element via solder, and a sealing material for sealing the semiconductor element and the first conductor plate, the sealing body having at least a first surface and a second surface on the opposite side of the first surface; and a case for housing the sealing body. The case is configured by a first heat radiation plate opposed to the first surface of the sealing body, a second heat radiation plate opposed to the second surface of the sealing body, and an intermediate member that connects the first heat radiation plate and the second heat radiation plate. The intermediate member has a first thin section having thickness smaller than the thickness of the first heat radiation plate, more easily elastically deformed than the first heat radiation plate, and formed to surround the first heat radiation plate.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: February 25, 2014
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Yusuke Takagi, Kaoru Uchiyama, Tokihito Suwa, Kinya Nakatsu, Takeshi Tokuyama, Shinji Hiramitsu
  • Patent number: 8659047
    Abstract: A light emitting device includes a substrate having an element mounting area in a principal surface thereof. The light emitting device also includes at least one light emitting element mounted in the element mounting area of the substrate. The light emitting device also includes a heat transfer member provided on the substrate. The heat transfer member has a thermal conductivity different from thermal conductivity of the substrate so as to form uneven thermal resistance distribution in the element mounting area. Thermal resistance in a heat radiation path through the substrate for release of heat emitted from the light emitting element changes with the mounting position of the light emitting element.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: February 25, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Ryosuke Kondo
  • Patent number: 8653647
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: February 18, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 8653651
    Abstract: According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: February 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Uchida, Takashi Togasaki, Satoru Hara, Kentaro Suga
  • Patent number: 8648478
    Abstract: A heat sink includes a first adhesive layer, and a heat dissipation layer disposed on the first adhesive layer, and has ventilation ports that extend therethrough including through the first adhesive layer and the heat dissipation layer. The heat sink forms an outermost part of a semiconductor package. Thus, when the heat sink is bonded via its adhesive layer to underlying structure during a manufacturing process, the ventilation ports allow air to pass therethrough. As a result, air is not trapped in the form of bubbles between the heat sink and the underlying structure.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Wook Yoo, Kyoung-Sei Choi, Eun-Seok Cho, Mi-Na Choi, Hee-Jung Hwang, Se-Ran Bae
  • Patent number: 8643171
    Abstract: A power semiconductor device includes: a mold unit that includes a power semiconductor element, a base plate, and a mold unit, the power semiconductor element being mounted on one surface of the base plate, a convex portion being formed on an other surface of the base plate, the convex portion including a plurality of grooves, the mold unit having a mold resin with which the power semiconductor element is sealed in such a manner as to expose the convex portion; a plurality of radiation fins inserted into the grooves, respectively, and fixedly attached to the base plate by swaging; and a metal plate that includes a opening into which the convex portion is inserted, the metal plate being arranged between the mold unit and the radiation fins with the convex portion inserted into the opening, wherein the metal plate includes a protrusion that protrudes from an edge of the opening and that digs into a side surface of the convex portion when the convex portion is inserted into the opening.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: February 4, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeyuki Nakazato, Yoichi Goto, Kiyofumi Kitai, Toru Kimura
  • Patent number: 8643170
    Abstract: Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Junhua Luo, Jinzhong Yao, Baoguan Yin
  • Patent number: 8623707
    Abstract: To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: January 7, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Andrew V. Kearney, Peng Su
  • Patent number: 8604606
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 10, 2013
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
  • Patent number: 8604608
    Abstract: A semiconductor module is disclosed that includes a semiconductor element, a capacitor configured to be electrically connected to the semiconductor element and a heat sink, wherein the semiconductor and the capacitor are stacked with each other via the heat sink, and wherein the semiconductor element is disposed in a position overlapping with the capacitor as viewed from a stack direction.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: December 10, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Jiro Tsuchiya, Torahiko Sasaki, Makoto Imai, Hideki Tojima, Tadakazu Harada, Tomoaki Mitsunaga
  • Patent number: 8598701
    Abstract: A semiconductor device has high reliability which suppresses a temperature rise of a set housing within an allowable range, and avoids an effect on a wiring on a package substrate due to thermal expansion of a heat dissipating member. The semiconductor device includes a semiconductor element, a package substrate, and a heat dissipating member. A first main surface of the semiconductor element faces an element-mounting surface of the package substrate and is connected to the package substrate. A main surface part of the heat dissipating member contacts a second main surface which is a back surface of first main surface of semiconductor element. A bonding part around a periphery of the main surface part is bonded to a bonding area of the element-mounting surface of the package substrate. A wiring on the package substrate is arranged at a portion other than the element-mounting surface, in a region of the bonding area.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: December 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Keisuke Sato, Kouji Takemura