Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: An optical scanner package having a heating dam is provided. The optical scanner package having a heating dam includes: an optical scanner on which a mirror surface is formed; a ceramic package in which the optical scanner is installed at the bottom of a cavity thereof; a glass lid covering a sidewall of the ceramic package; a heating dam formed on the sidewall of the ceramic package; and solder on the heating dam sealing between the glass lid and the sidewall of the ceramic package. The heating dam locally heats the solder to form hermetic sealing.

Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.

Abstract: An assembly includes a substrate, a device coupled to the substrate; a ring formed on the substrate; and one or more bonding pads formed on the substrate, wherein the ring and bonding pads are formed of a same material.

Abstract: A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are connected to traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The input/output leads provide means for connecting the housing with the electronic device or system into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.

Abstract: An integrated circuit lid fixture and methods of using the same are provided. In one aspect, an integrated circuit lid fixture is provided that includes a base that has a plurality of pillars. Each of the plurality of pillars has a surface for supporting a substrate that may be removably seated thereon. The surfaces of the plurality of pillars have a first footprint at least as large as a footprint of the substrates to be placed thereon. A plate is provided for applying a compressive force to an integrated circuit lid positioned on any of the substrates removably seated on the pillars.

Abstract: A process for preparing an electronic package comprising: (a) providing a ceramic housing defining an internal cavity for receiving a micro device and having one or more interface portions; (b) treating the housing to form a tungsten layer on the interface portions; and (c) overlaying a palladium layer on the tungsten layer.

Abstract: Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.

Abstract: A packaging structure (10) is provided having a hermetic sealed cavity for microelectronic applications. The packaging structure (10) comprises first and second packaging layers (12, 28) forming a cavity. Two liquid crystal polymer (LCP) layers (16, 22) are formed between and hermetically seal the first and second packaging layers (12, 28). First and second conductive strips (18, 20) are formed between the LCP layers (16, 22) and extend into the cavity. An electronic device (24) is positioned within the cavity and is coupled to the first and second conductive strips (18, 20).

Abstract: A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by metal wires; and chip capacitors mounted on the semiconductor chip to reduce power source noise.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: A semiconductor package includes a wiring board, a semiconductor chip flip-chip bonded to the wiring board, an adhesive coated on the wiring board, a stiffener ring attached to the wiring board, and a heat spreader attached to the stiffener ring and the semiconductor chip. The stiffener ring includes a window through which the semiconductor chip is exposed and multiple through holes. A thermal interface material (TIM) coated on the back surface of the semiconductor chip. The stiffener ring is attached to the heat spreader by portions of the adhesive squeezed onto the upper surface of the stiffener ring via the through holes, and the semiconductor chip is attached to the heat spreader by the TIM. A method for manufacturing a semiconductor package includes: flip-chip bonding a semiconductor chip to a wiring board; coating an adhesive on the wiring board; and attaching a stiffener ring to the wiring board. The stiffener ring includes a window through which the semiconductor chip is exposed and through holes.

Abstract: An electronic circuit device comprises: a semiconductor element having a first surface and a second surface, with the first and second surfaces being on first and second sides of the semiconductor element, respectively, and facing in opposite directions; a first electrode on the first surface; a second electrode on the second surface; a first circuit board electrically connected to the first electrode via a metallic plate such that the metallic plate and the semiconductor element are on the first circuit board; a second circuit board on the second side of the semiconductor element, the second circuit board having a control circuit for the semiconductor element; and a metallic wire for directly electrically interconnecting the second electrode and the second circuit board.

Abstract: An electronic assembly includes a first substrate and a second substrate. The first substrate includes a first surface having a first plurality of conductive traces formed on an electrically non-conductive layer. The second substrate includes a first surface having a second plurality of conductive traces formed thereon and a second surface having a third plurality of conductive traces formed thereon. A first electronic component is electrically coupled to one or more of the plurality of conductive traces on the first surface of the second substrate. At least one of a plurality of conductive interconnects is incorporated within each solder joint that electrically couples one or more of the conductive traces formed on the second surface of the second substrate to one or more of the conductive traces formed on the first substrate.

Abstract: A MEMS package and a method for its forming are described. The MEMS package has at least one MEMS device located on a flexible substrate. A metal structure surrounds the at least one MEMS device wherein a bottom surface of the metal structure is attached to the flexible substrate and wherein a portion of the flexible substrate is folded over a top surface of the metal structure and attached to the top surface of the metal structure thereby forming the MEMS package.

Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

Abstract: A semiconductor device which includes: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip. A surface of the stiffener opposite from the solid device is generally flush with a surface of the semiconductor chip opposite from the solid device.

Abstract: A hermetic sealing cap member capable of suppressing deterioration of characteristics of an electronic component resulting from a sealant such as solder coming into contact with the electronic component in a package is obtained. This hermetic sealing cap, which is a hermetic sealing cap employed for an electronic component storing package for storing an electronic component (5, 34), comprises a hermetic sealing cap member (11, 41), a first plating layer (12, 42) formed at least on a region other than a region of the hermetic sealing cap member formed with a sealant (3, 32) and a second plating layer (13, 43), formed on the region of the hermetic sealing cap member on which the sealant is arranged, containing a material superior in wettability with the sealant to the first plating layer.

Abstract: An assembly includes a circuit board with a ball grid array device attached to a first side of the circuit board. A brace surrounding the ball grid array device has a series of mounting holes and a series of members extending between the mounting holes. The brace is removably secured to the first side of the circuit board at the mounting holes.

Abstract: A MEMS inertial sensor is secured within a premolded-type package formed, at least in part, from a low moisture permeable molding material. Consequently, such a motion detector should be capable of being produced more economically than those using ceramic packages. To those ends, the package has at least one wall (having a low moisture permeability) extending from a leadframe to form a cavity, and an isolator (with a top surface) within the cavity. The MEMS inertial sensor has a movable structure suspended above a substrate having a bottom surface. The substrate bottom surface is secured to the isolator top surface at a contact area. In illustrative embodiments, the contact area is less than the surface area of the bottom surface of the substrate. Accordingly, the isolator forms a space between at least a portion of the bottom substrate surface and the package. This space thus is free of the isolator.

Abstract: This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.

Abstract: The present invention provides a semiconductor device which includes a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.

Abstract: Ultrasonically formed seals, their use in semiconductor packages, and methods of fabricating semiconductor packages. A brittle center member (such as glass) has a molded edge member. That edge member is ultrasonically welded to a body. The molded edge member and body are comprised of ultrasonically weldable materials. A hermetically sealed semiconductor package includes a lid with a brittle center plate and a molded edge. The molded edge is ultrasonically welded to a body. Locating features that enable accurate positioning of the lid relative to the body, and energy directors can be included. Pins having a relieved portion and a protruding portion can also be hermetically sealed to the body. Such pins can have various lengths that enable stadium-type pin rows. The pins can be within channels, which can hold a sealant. The body can include a device that is electrically connected to the pins.

Abstract: A method (100) of attaching a shield (52 or 82) to a substrate (40) can include the steps of circumscribing a predetermined area on the substrate with a metallized trace pattern (26), applying (101) solder to the metallized trace pattern, and optionally placing (103) components (22 and 27) on portions of the metallized trace pattern. The method can further include the steps of reflowing (104) the solder to form a selective cladded trace pattern (32 or 62) on a portion of the metallized trace pattern reserved for the shield, placing (108) the shield on the cladded trace pattern, and reflowing (109) the substrate.

Abstract: A process and electronic assembly for conducting heat from a semiconductor circuit device mounted to a substrate. The substrate is supported by a housing member equipped with a heat-conductive member. A surface of the device opposite the substrate is bonded to the heat-conductive member with a solder joint formed of indium and optionally one or more alloying constituents that increase the melting temperature of the solder joint above that of indium. The housing member, substrate, and device are assembled so that an indium-containing solder material is present between the heat-conductive member and the surface of the device opposite the substrate. The solder material is then reflowed to form the solder joint. The alloying constituent(s) are preferably introduced into the solder joint during reflow.

Abstract: A semiconductor apparatus is provided in which input/output of an electric signal having a particularly high frequency is less disturbed by parasitic capacitance generated in a wiring in the semiconductor apparatus. A first through-hole wiring penetrating a first dielectric board, a second through-hole wiring penetrating a second dielectric board, and an internal wiring inserted between the first dielectric board and the second dielectric board are provided. The first through-hole wiring and the second through-hole wiring are arranged on the internal wiring while being away from each other.

Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates are prepared each having a chip thereon. Length and width of each substrate are equal to predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. A protruded portion is formed at each corner of each opening, wherein a distance between two diagonal protruded portions is slightly larger than that between two diagonal corners of the substrate. The substrates are fixed in the openings of the carrier by means of the protruded portions, and gaps between the substrates and the carrier are sealed. An encapsulant is formed over each opening to encapsulate the corresponding chip by a molding process. An area on the carrier covered by the encapsulant is larger in length and width than the opening. A plurality of the semiconductor packages are formed after performing mold-releasing and singulation processes.

Abstract: A semiconductor chip package has a substrate that includes circuit lines provided on first and/or second surfaces, a power plane provided on the second surface, bump lands provided on the second surface and coupled to the circuit lines, and ball lands provided on the first surface. The package further has a semiconductor chip attached to the second surface of the substrate and electrically coupled to the circuit lines, and a dielectric layer provided on the second surface of the substrate. The dielectric layer surrounds laterally the chip, covers the power plane, and exposes the bump lands. The package further has a ground plane provided on both the chip and the dielectric layer, vertical connection bumps provided within the dielectric layer and on the bump lands and electrically coupled to the ground plane, and solder balls provided on the ball lands.

Abstract: The present invention provides a heat spreader with a bypass capacitor to provide substantially instant power and/or to control simultaneous switching noise (SSN). The present invention also provides a semiconductor device package incorporating this heat spreader. In addition, fabrication methods for such heat spreaders and packages are provided. Generally, the heat spreaders and packages of the present invention include an embedded bypass capacitor that can provide decoupling capacitance in order to deliver near instant power to the die and/or minimize SSN. In a preferred embodiment, the embedded bypass capacitor is connected to terminals integrated with the heat spreader (e.g., lid; stiffener) and/or to a package plane (e.g., power plane or ground plane) in the package substrate for connection via the flip chip package's power delivery system to a power source and/or component.

Abstract: Integrated circuit components are imbedded within a laminate substrate disposed on a thermally conductive core, which provides a thermal sink. The circuit components are electrically connected to the integrated circuit via flexible electrical interconnects such as flexible wire bonds. An electrically insulating coating, is deposited upon the flexible electrical interconnects and upon the exposed surfaces of the integrated circuit assembly. The coating provides rigidity, an electrically insulating barrier and a first environmental barrier for preventing contamination of the exposed surfaces of the integrated circuit assembly. A thermally conductive encapsulating material, such as silicon gel, encases the circuit components and the flexible electrical interconnects within a rigid or semi-rigid matrix. The encapsulating material provides additional mechanical support, a second environmental and a thermal sink for dissipation of heat.

Abstract: A component includes a chip having a first chip face and a second chip face, where the first chip face includes component structures and connector metallizations associated with the component structures. The component also includes a frame structure on the first chip face and adjacent to the component structures, and a cover over the frame structure. The cover has a first cover face and a second cover face. The first cover face is closer to the chip than the second cover face. A back metallization is on the second chip face, on sides of the frame structure, and on sides of the cover. A contact is on the second cover face. There is a connection through the cover, which electrically connects the component structures and the contact. The connection is metallized and sealed.

Abstract: A method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method is disclosed. To fabricate the apparatus, a device chip including a substrate and at least one circuit element on the substrate is fabricated. Also, a cap is fabricated. The cap is attached to the device chip using single phase metal alloy to achieve sealed cavity over the circuit element. The single phase metal alloy allows the cap to be diffusion bonded to the device chip at a higher diffusivity thus allowing diffusion at a lower temperature, lower pressure, shorter period, or a combination of these.

Abstract: A semiconductor-producing/examining device that can maintain a preferable connection state for a predetermined period of time and that can easily remove a ceramic substrate from a supporting case. The semiconductor producing/examining device includes a ceramic substrate having a conductor layer formed on the surface thereof or inside thereof and a supporting case. An external terminal is connected to the conductor layer. A connection between the conductor layer and the external terminal is performed such that the external terminal is pressed on the conductor layer or the external terminal is pressed on another conductor layer connected to the conductor layer by using the elastic force and the like of an elastic body.

Abstract: An apparatus and method for providing three-dimensional carrier mounting of one or more electronic components. In accordance with one embodiment, the device mounting apparatus of the present invention includes an elastically resilient plastic substrate having component mounting surfaces in at least two dimensions. At least one press-fit component insertion cavity is disposed within the component mounting surfaces to provide compressive retention of the electronic component when press-fit into the cavity. Preferably, the cavity has a depth such that when the component is press-fit, it does not extend above the surface plane of the cavity. The insertion cavity is further characterized as including at least one conductive trace disposed on an inner surface of said insertion cavity and positioned on the insertion cavity surface such that the conductive trace contacts at least one lead of the electronic device retained within the insertion cavity.

Abstract: Microelectronic packages having chambers and sealing materials, and methods of making the packages, and sealing the chambers, are disclosed. An exemplary package may include a first surface, a second surface, a solid sealing material including an intermetallic compound, such as, for example, of gallium or another relatively low melting material, between the first surface and the second surface, and a chamber defined by the first surface, the second surface, and the sealing material. An exemplary method may include disposing a ring of a sealing material including a liquid metal between a first surface and a second surface to define a chamber between the first surface, the second surface, and the ring of the sealing material, and sealing the chamber by heating the sealing material to react the liquid metal with a metal that is capable of forming an intermetallic compound with the liquid metal.

Abstract: To enable to downsize a package for containing a solid-state imaging element relative to a solid-state imaging element having the same size and accordingly, downsize a solid-state imaging device for containing the solid-state imaging element thereto, further, downsize an apparatus such as a video camera or a still camera using the solid-state imaging device, there is provided a package for containing semiconductor element comprising a package having a recess portion for containing a semiconductor element, and a pair of positioning holes and a pair of attaching holes respectively provided at a pair of opposed side portions of the recess portion at surfaces of the package, wherein a line connecting the pair of positioning holes and a line connecting the pair of attaching holes are intersected with each other substantially at a center of the package.

Abstract: There is disclosed a combined absolute differential pressure transducer which consists of two sensors made from the same wafer silicon and selected to be adjacent to each other on the wafer. Since the same pressure is applied to the boss side of both sensors and a second pressure is applied to the opposite side of the differential sensor, deflection and the stress of the second sensor is determined by the pressure difference across the deflecting portion of the sensor. To obtain the same stresses in the thin section of each sensor, the overall active area of each sensor is different. For the same thickness read, the absolute value of P2?P1 where P2 is the pressure applied to the front side of the two sensors and P1 is the pressure applied to the differential sensor through the metal tube is less than P2 to obtain the same stress in each sensor a great active area in the differential sensor is required.

Abstract: A semiconductor device includes a hermetically sealed housing having a top member and a bottom member. The bottom member includes a recess. A semiconductor die is enclosed within the housing. Absorbing material is positioned in the recess under the semiconductor die. A porous film is positioned between the semiconductor die and the absorbing material.

Abstract: A heat spreader and stiffener device has a stiffener portion extending towards a center of the heat spreader and stiffener device and mountable to a die-side surface of a substrate.

Abstract: A thermally enhanced BGA semiconductor device 10 having a heat sink 12 formed from a single piece of material with an expanded base and a pedestal in contact with a semiconductor chip 11. The pedestal is aligned through a window opening in a substrate 13 and the top surface of the base is adhered to the substrate. The heat sink 12 with an expanded base provides a path for rapid and efficient heat spreading and dissipation, a stand-off and an aid to improved package planarity during reflow to a PCB, and a long path for ingress of contaminants into the package. The device is amenable to high volume, low cost production.

Abstract: An apparatus has first and second wafers, and a conductive rim between the first and second wafers. The conductive rim electrically and mechanically connects the first and second wafers. In addition, the conductive rim and second wafer at least in part seal an area on the surface of the first wafer.

Abstract: In a semiconductor laser device, a flange (33) of a cap (32) is provided with straight-line cut-off portions (34) that are the same in number as notches (36, 37) of a stem (35). With the cut-off portions (34) positioned so as not to overlap the notches (36, 37) of the stem (35) in position, welding between the cap (32) and the stem (35) is performed. The cut-off portions (34) of the cap (32) secure obtainment of a reference plane 38 with a large area in a place where the notches (36, 37) of the stem (35) are absent. As a result, sufficient precision in optical characteristics can be secured while suppressing an influence of unevenness of the stem (35) having a small diameter on a deviation angle ? of an optical axis from a normal line to a reference plane of an optical pickup.

Abstract: A method of fabricating an integrated circuit that includes a microelectromechanical (MEMS) device. The method includes forming a MEMS device on a substrate and forming an integrated circuit. The method further includes coupling the substrate to the integrated circuit to form a sealed cavity that includes the MEMS device. The substrate and the integrated circuit are coupled together in a controlled environment to establish a controlled environment within the cavity where the MEMS device is located.

Abstract: A method for producing a multi-layer device. The method initially providing a substrate which comprises a support region for supporting an electrical component, then forming an electrically conductive bond layer on a surface of the substrate. The bond is configured to surround the region for supporting the component. The next step in the method is to provide an encasing layer in contact with the bond layer, such that the component is encased between the substrate and the encasing layer. The final step involves bonding the encasing layer to the bond layer to form a sealed cavity which encloses the component. Further, a multi-layer device is provided. The device comprises a substrate, at least one electrical component which is located on the substrate, an electrically conductive bond layer and an encasing layer. The bond layer is formed on the substrate and surrounds the electrical components and the encasing layer is bonded to the bond layer to form a sealed cavity encasing the components therein.

Abstract: The present invention relates to a circuit assembly with at least two semiconductor components, each having terminals, whereby at least one terminal of the first semiconductor component is connected to a terminal of the other semiconductor component in an electrically conductive manner. The circuit assembly damps high-frequency oscillations that occur during switching operations. An eddy-current damping structure is provided above said assembly at a distance from the semiconductor components or said semiconductor components are directly connected to each other by means of a high-resistance wire connection in addition to the existent electroconductive connection.

Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Abstract: The stackable power semiconductor module comprises electrically conductive base plates, an electrically conductive cover plate and a plurality of semiconductor chips. The semiconductor chips are arranged in groups of several on separate base plates in preassembled submodules. The base plates are moveable towards the cover plate. The submodules are paralleled inside the module housing. The submodules are fully testable according to their current ratings. Altering the number of submodules paralleled inside the housing can vary the overall current rating of a module.

Abstract: A semiconductor package in which solder balls can be loaded on an encapsulated resin to reduce the package area and a method for producing the semiconductor package. An apparatus for carrying out the method includes a first insulating substrate 5 carrying a mounting portion 3 for mounting a semiconductor device 2 and a first electrically conductive pattern 4 electrically connected to the semiconductor device 2, a sidewall section 6 formed upright around the mounting portion of the first insulating substrate, a cavity 7 defined by the first insulating substrate 5 and the sidewall section and encapsulated by an encapsulating resin 12 as the semiconductor device 2 is mounted on the mounting portion 3 and a second insulating substrate 10 provided in the cavity 7 and on the sidewall section 6 and carrying a second electrically conductive pattern 31 electrically connected to the first electrically conductive pattern 4 via plated through-holes 26 formed in the sidewall section 6.