With Electrical Isolation Means Patents (Class 257/725)
  • Patent number: 8373259
    Abstract: A system includes an optical transceiver assembly, including a flip chip connection of a semiconductor die with a photonic transceiver that overhangs a substrate to which it is to be connected. The assembly further includes an alignment pin that is held to the semiconductor die at a micro-engineered structure in the semiconductor die. The alignment pin provides passive alignment of the photonic transceiver with an optical lens that interfaces the photonic transceiver to one or more optical channels.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Brian H. Kim, Simon S. Lee
  • Patent number: 8335077
    Abstract: A system contains a temperature sensitive device and a printed circuit board. The temperature sensitive device is coupled to the printed circuit board. An aperture is cut out of the printed circuit board between the temperature sensitive device and a heat generating device to act as an insulator for the temperature sensitive device.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: December 18, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Christopher N. Rijken, Mark D. Tupa, Michael R. Durham
  • Patent number: 8330252
    Abstract: An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Reimund Engl, Thomas Behrens, Wolfgang Kuebler, Rainald Sander
  • Patent number: 8330261
    Abstract: In general, the invention relates to manufacturing a wafer. The method includes manufacturing a wafer that includes a front side and a back side, thinning the wafer down to a thickness suitable for an intended operation of the wafer, polarizing the substrate wafer from the back side, and cutting the wafer. The wafer is polarized such that an attempt to thin the wafer from the backside results in at least one selected from a group consisting of destruction of the wafer and damage to the wafer.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: December 11, 2012
    Assignee: Gemalto SA
    Inventor: Michel Thill
  • Patent number: 8304873
    Abstract: A method for manufacturing a display device includes a first step of preparing a first substrate which has a first area to be etched and a second area located at a periphery of the first area and which has a display element on its surface, a second step of etching and removing the first area of the first substrate, a third step of forming a second substrate on a surface of the first substrate that is opposite to the surface on which the display element is located, and a fourth step of removing the second area of the first substrate.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: November 6, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Okabe, Yoshimasa Chikama
  • Patent number: 8304899
    Abstract: A recessed portion is provided in first and second insulating films, the first insulating film being stacked on a semiconductor wafer, the second insulating film being stacked on the first insulating film. The first and second insulating films are processed to form wiring in a formation region of the semiconductor wafer in which an acceleration sensor is to be formed. After a sacrificial film is stacked on the wiring and processed, a conductive film is stacked on the wiring and processed to form a plurality of thin film structures in the formation region. The recessed portion surrounds the formation region.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: November 6, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mika Okumura, Makio Horikawa, Kimitoshi Satou, Yasuo Yamaguchi
  • Patent number: 8268673
    Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: September 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
  • Patent number: 8269343
    Abstract: A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: September 18, 2012
    Assignee: Spansion LLC
    Inventor: Kouichi Meguro
  • Patent number: 8253241
    Abstract: An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 ?m.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: August 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Stefan Landau, Erwin Huber, Josef Hoeglauer, Joachim Mahler, Tino Karczeweski
  • Patent number: 8253235
    Abstract: A semiconductor packaging substrate with improved capability of electrostatic dissipation comprises a dielectric layer, a plurality of leads, a plurality of first electrostatic guiding traces, a plurality of second electrostatic guiding traces and a solder mask. The first electrostatic guiding traces and the second electrostatic guiding traces are formed in pairs in a plurality of electrostatic dissipation regions on the dielectric layer, where each pair of the first and second electrostatic guiding traces are disposed in equal line spacing and are electrically isolated from each other. The solder mask partially covers the leads but exposes the first electrostatic guiding traces and the second electrostatic guiding traces. The first electrostatic guiding traces are connected to some of the leads to enhance protection against electrostatic discharge.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: August 28, 2012
    Assignee: Chipmos Technologies Inc.
    Inventors: Tsung Lung Chen, Ming Hsun Li
  • Patent number: 8253226
    Abstract: An electronic part (100) that shields parts on a substrate (101) includes a plurality of chip parts (102) each having on a respective end portion a ground terminal (103A) and an electrode terminal (103B) that supplies a voltage source, and located at regular intervals on the substrate with the respective ground terminals aligned, the ground terminal and the electrode terminal being electrically connected to a ground terminal land (107A) and an electrode terminal land (107B) of the substrate respectively; and a shielding case (104) that shields the plurality of chip parts and includes an opening (105) through which a resin is to be provided for securing strength of the respective electrical connection points of the ground terminal land and the electrode terminal land of the substrate with the ground terminal and the electrode terminal of the chip parts; the opening being formed such that an edge (106) of the opening becomes parallel to the ground terminal of the respective chip parts, and such that upon being
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: August 28, 2012
    Assignee: NEC Corporation
    Inventor: Shinji Oguri
  • Patent number: 8253244
    Abstract: A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Uk-Song Kang
  • Patent number: 8231056
    Abstract: A contact detector having power switches for disconnecting power to portions of the contact sensor when an over current is detected is disclosed. The power switches thus protect the contact sensor from over-current as the result of latch-up or other current-generating conditions. These current-generating conditions are often the result of ESD events on a surface of the contact detector. A contact detector comprises an exposed surface for detecting the presence of an object, an insulating surface, and a protection element disposed under the insulating surface for controlling power to the contact detector. The protection element is configured to disconnect power to the contact detector when a current to the contact detector is detected above a threshold. Preferably, the contact detector is a finger swipe sensor, but it can be a finger placement sensor or any other type of device that functions on contact with a finger or other patterned object.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: July 31, 2012
    Assignee: Authentec, Inc.
    Inventors: Oleksiy Zabroda, Ericson W. Cheng, Hung Xuan Ngo
  • Patent number: 8193624
    Abstract: A semiconductor package assembly has a first semiconductor package. A plurality of first solder balls is attached to the first semiconductor package. A circuit board is provided having a plurality of mounting pads that is electrically connected to the plurality of first solder balls. A first underfill is disposed on each of the plurality of first solder balls. The first underfill is disposed on interfaces between each of the plurality of first solder balls and the first semiconductor package and each of the plurality of first solder balls and the circuit board. The first underfill is removed from an area between adjacent first solder balls.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: June 5, 2012
    Assignee: Amkor Technology, Inc.
    Inventor: Eun Sook Sohn
  • Patent number: 8183574
    Abstract: The present invention relates to an electronic device for providing improved heat transporting capability for protecting heat sensitive electronics and a method for producing the same. The present invention also relates to uses of the electronic device for various applications such as in LED lamps for signalizing, signage, automative and illumination applications or a display apparatus or any combinations thereof.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: May 22, 2012
    Assignee: NXP B.V.
    Inventor: Gilles Ferru
  • Patent number: 8179679
    Abstract: An electronic device includes a printed circuit board having a wall deposited directly on a board serving as a base for a printed circuit. As the board is constructed, the wall is deposited on the board for controlling airflow. The wall controls airflow across the board and around components mounted to the board. The wall may be utilized for controlling airflow in combination with a second printed circuit board positioned adjacent to the first printed circuit board. The wall may be utilized for controlling various types of airflow, including airflow from sources including fans and convection, and from geometries including horizontal and vertical mounting geometries. The silicon wall may be utilized for preventing heat airflow generated by heat radiated from one component from impinging upon another component.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: May 15, 2012
    Assignee: NetApp, Inc.
    Inventor: Richard A. Slagle
  • Patent number: 8154881
    Abstract: A radiation-shielded semiconductor assembly includes at least one radiation-shielding lamina within the package. In some embodiments, a semiconductor assembly includes a microelectronic component, and at least one radiation-shielding layer affixed to a surface of the component.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 10, 2012
    Assignee: Telecommunication Systems, Inc.
    Inventor: Roydn Jones
  • Patent number: 8148814
    Abstract: In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Futoshi Furuta, Kenichi Osada, Makoto Saen
  • Patent number: 8143720
    Abstract: The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: March 27, 2012
    Assignee: Rambus Inc.
    Inventor: Frank Lambrecht
  • Patent number: 8143719
    Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: March 27, 2012
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Chin Hock Toh, Hao Liu, Ravi Kanth Kolan
  • Patent number: 8134233
    Abstract: A method and apparatus for forming controlled stress fractures in metal produces electrically isolated, closely spaced circuit sub-entities for use on a metallized printed wiring board. A polymeric substrate has a layer of metal adhered to the surface, and the metal layer is formed into entities. Each entity has a fracture initiating feature formed into it, which serves to initiate and/or direct a stress crack that is induced in the metal. The entities are fractured in a controlled manner by subjecting the substrate and the entities to mechanical stress by a rapid thermal excursion, creating a stress fracture in the entity extending from the fracture initiating feature. The stress fracture divides each entity into two or more sub-entities that are electrically isolated from each other by the stress fracture. The resulting structure can be used to form circuitry requiring very fine spaces for high density printed circuit boards.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: March 13, 2012
    Assignee: Motorola Solutions, Inc.
    Inventors: Jerzy Wielgus, Daniel R. Gamota, Tomasz L. Klosowiak, John B. Szczech, Kin P. Tsui
  • Patent number: 8093983
    Abstract: Disclosed herein are various embodiments of narrowbody coil isolators containing multiple coil transducers, where integrated circuits are not stacked vertically over the coil transducers. The disclosed coil isolators provide high voltage isolation and high voltage breakdown performance characteristics in small packages that provide a high degree of functionality at a low price.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: January 10, 2012
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Julie Fouquet, Dominique Ho
  • Patent number: 8080865
    Abstract: An RF-coupled digital isolator includes a first leadframe portion and a second leadframe portion, electrically isolated from one another. The first leadframe portion includes a first main body and a first finger. The second leadframe portion includes a second main body and a second finger. The first main body is connected to a first ground, and the second main body is connected to a second ground that is electrically isolated from the first ground. The first finger and the second finger are electrically isolated from one another, e.g., by a plastic molding compound that forms a package for the digital isolator. The first finger acts as a primary of a transformer, and the second finger acts as a secondary of a transformer, when an RF signal drives to the first finger. The first finger and the second finger can be substantially parallel or anti-parallel to one another.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 20, 2011
    Assignee: Intersil Americas, Inc.
    Inventor: Barry Harvey
  • Patent number: 8049331
    Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: November 1, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Philip Neaves
  • Patent number: 8030764
    Abstract: The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second device.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: October 4, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Neill Thornton, Dennis Lang
  • Patent number: 8030134
    Abstract: Stacked semiconductor assemblies in which a first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: October 4, 2011
    Assignee: Chippac, Inc.
    Inventors: Hyeog Chan Kwon, Marcos Karnezos
  • Patent number: 8004089
    Abstract: On the lower surface of a semiconductor construct having an external connection electrode, there are formed an insulating film having a planar size greater than that of the semiconductor construct, and a metal layer and a mask metal layer having a connection pad portion in which a first opening corresponding to the external connection electrode is formed. A laser beam is applied using the mask metal layer as a mask, and a second opening is thereby formed in a part of the insulating film corresponding to the external connection electrode. Then, a connection conductor is formed to connect a wiring line to the external connection electrode via the second opening of the insulating film.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: August 23, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: 7999369
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: August 16, 2011
    Assignees: DENSO CORPORATION, University of Cambridge, The University of Sheffield
    Inventors: Rajesh Kumar Malhan, C. Mark Johnson, Cyril Buttay, Jeremy Rashid, Florin Udrea
  • Patent number: 7989269
    Abstract: A semiconductor device is made by mounting a first semiconductor die to a first substrate, forming a first encapsulant over the first semiconductor die, and forming a second encapsulant over the first encapsulant. The second encapsulant is penetrable, thermally conductive material. A second semiconductor die is mounted to the second substrate. A bond wire electrically connects the second semiconductor die to the second substrate. A passive circuit element is mounted to the second substrate. Leading with the second encapsulant, the first substrate is pressed onto the second substrate so that the second encapsulant completely covers the second semiconductor die, bond wire, and passive circuit element. The second encapsulant is then cured. A third encapsulant is formed over the first and second substrates. A shield can be disposed over the second semiconductor die with openings for the second encapsulant to flow through when pressed onto the second substrate.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: August 2, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Patent number: 7977232
    Abstract: A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators. The multi-level interconnections may extend in the device region. An electrode layer may be disposed over the stack of inter-layer insulators. The electrode layer may extend in the device region. The electrode layer may cover the multi-level interconnections. A cracking stopper groove may be disposed in the dicing region. The cracking stopper groove may be positioned outside the device region.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: July 12, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Toyonori Eto
  • Patent number: 7955875
    Abstract: Methods of forming a light emitting device include selectively forming a wavelength conversion structure on a light emitting element using stereolithography. Selectively forming the wavelength conversion structure may include covering the light emitting element with a photo-curable liquid polymer containing a luminescent material, and exposing the liquid polymer to light for a time sufficient to at least partially cure the liquid polymer. Multiple layers of polymer can be selectively built up to form a wavelength conversion structure having a custom shape on the light emitting element.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: June 7, 2011
    Assignee: Cree, Inc.
    Inventor: Craig Hardin
  • Patent number: 7952211
    Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: May 31, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Seng Guan Chow, Francis Heap Hoe Kuan
  • Patent number: 7952112
    Abstract: A submount for red, green, and blue LEDs is described where the submount has thermally isolated trenches and/or holes in the submount so that the high heat generated by the green/blue AlInGaN LEDs is not conducted to the red AlInGaP LEDs. The submount contains conductors to interconnect the LEDs in a variety of configurations. In one embodiment, the AlInGaP LEDs are recessed in the submount so all LEDs have the same light exit plane. The submount may be used for LEDs generating other colors, such as yellow, amber, orange, and cyan.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: May 31, 2011
    Assignee: Philips Lumileds Lighting Company LLC
    Inventor: Franklin J. Wall, Jr.
  • Patent number: 7939369
    Abstract: A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Subramanian S. Iyer
  • Patent number: 7935892
    Abstract: Circuit board having conductor wiring and connection terminal; anisotropic conductive resin layer provided on one surface of circuit board; and plurality of electronic components respectively provided with electrode terminals in positions facing the connection terminal are included. The anisotropic conductive resin layer includes at least one kind of conductive particles selected from coiled conductive particles, fiber fluff conductive particles and conductive particles provided with a plurality of conductive protrusions, and resin binder; electrically couples electrode terminals of plurality of electronic components to connection terminals to each other with conductive particles; mechanically fixes electronic components and circuit board to each other; and protects conductor wiring.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: May 3, 2011
    Assignee: Panasonic Corporation
    Inventors: Kazuhiro Nishikawa, Hidenori Miyakawa, Norihito Tsukahara, Shigeaki Sakatani
  • Patent number: 7928562
    Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Amilcar R. Arvelo, Evan G. Colgan, John H. Magerlein, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jeffrey A. Zitz
  • Patent number: 7906846
    Abstract: A plurality of LSI chips (1) are stacked on an interposer (2). Signal coils (1b) for signal transmission are formed on the circuit formation surfaces of LSI chips (1) that are formed using silicon substrates (1a). The signal coils (1b) connect to circuits formed in the LAI chips (1). Through-holes (1d) are formed in the centers of the signal coils (1b) of the silicon substrate (1a). Signal coils (2c) connected to solder balls (5) by way of through-conductors (2d) are formed on the interposer (2). Magnetic pins (3) that are composed of a magnetic material are inserted in the centers of the signal coils (1b and 2c).
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: March 15, 2011
    Assignee: NEC Corporation
    Inventors: Shigeki Hoshino, Michinobu Tanioka, Toru Taura
  • Patent number: 7906842
    Abstract: There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: March 15, 2011
    Assignee: NEPES Corporation
    Inventor: Yun Mook Park
  • Patent number: 7902665
    Abstract: A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: March 8, 2011
    Assignee: Linear Technology Corporation
    Inventor: David Alan Pruitt
  • Patent number: 7875971
    Abstract: The semiconductor device includes a substrate, a first semiconductor element, a second semiconductor element, a first heat sink and a second heat sink. The first and the second semiconductor elements are provided on the substrate. The maximum power consumption of the first semiconductor element is lower than that of the second semiconductor element. The first heat sink is fixed to the first semiconductor element. The second heat sink is fixed to the second semiconductor element. The first heat sink is spaced apart from the second heat sink.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Keisuke Sato
  • Patent number: 7847387
    Abstract: An electrical device and method is disclosed. One embodiment provides a substrate, a sensor chip disposed completely above a plane section of a surface of the substrate. A structurally homogeneous material layer is disposed above the substrate and the sensor chip. A cavity is formed between the substrate and the material layer. The sensor chip is disposed inside the cavity.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: December 7, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Horst Theuss
  • Patent number: 7834450
    Abstract: A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Uk-Song Kang
  • Patent number: 7812446
    Abstract: A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoichiro Kurita
  • Patent number: 7795729
    Abstract: A transceiver device includes a dielectric substrate, a ring member that is welded onto the dielectric substrate thereby forming a plurality of cavities, a cover that is welded onto the ring member, and at least one semiconductor device that is arranged in each of the cavities. The ring member has at least one passage that communicates between adjacent cavities. The passage is provided at a position shifted by substantially ?g/4 or substantially nĂ—?g/2+?g/4 from a center axis of the cavities. If there are two or more passages, the passages are arranged at a ?g/2 interval, and one of the passages closest to the center axis is at a position shifted by substantially ?g/4 from the center axis.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: September 14, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kousuke Yasooka
  • Patent number: 7786574
    Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: August 31, 2010
    Assignee: Aptina Imaging Corp.
    Inventors: James M. Derderian, Bret K. Street, Eric T. Mueller
  • Patent number: 7781887
    Abstract: A semiconductor device includes a first die, a substrate, and a first interconnect. The first die includes a first isolation region and a first contact at least partially overlapping the first isolation region. The substrate includes a second contact. The first interconnect couples the first contact to the second contact. The first interconnect is defined by a via through the first isolation region.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: August 24, 2010
    Assignee: Infineon Technologies AG
    Inventor: Alois Nitsch
  • Patent number: 7782624
    Abstract: An electronic apparatus includes a semiconductor chip 15, a first substrate 10A having an antenna 12 formed on a first face 10a thereof and having the semiconductor chip 15 loaded on a second face 10b thereof, a second substrate 20A on which the first substrate 10A is provided so as to face the semiconductor chip 15, and which is connected to the outside, copper core solder balls 18 electrically connecting the first substrate 10A and the second substrate 20A, and a resin material 30 disposed between the first substrate 10A and the second substrate 20A. The second substrate 20A is provided with a thermal via 27 which radiates the heat in the semiconductor chip 15.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: August 24, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Tomoharu Fujii
  • Patent number: 7778035
    Abstract: A portable electronic apparatus comprises a housing, a circuit board, a heat-conduction structure and a heat-dissipation structure. The circuit board is disposed in the housing and comprises a substrate and a first electronic device, wherein the first electronic device is disposed on the substrate. The heat-conduction structure is disposed on the circuit board, and dissipates heat from the first electronic device. The heat-dissipation structure is disposed on the housing and connected to the heat-conduction structure, wherein the heat passes the heat-conduction structure and the heat-dissipation structure, and is dissipated out of the housing.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: August 17, 2010
    Assignee: HTC Corporation
    Inventors: Yi-Chang Huang, Yao-Chung Lin
  • Patent number: 7777331
    Abstract: A semiconductor apparatus including built-in power supply circuits capable of supplying a large current with high voltage accuracy. The semiconductor apparatus includes a semiconductor chip including a circuit area and power supply circuits, coils and capacitors. The semiconductor chip, coils and capacitors are provided in a package. Each power supply circuit, a coil and a capacitor compose a switching regulator. The semiconductor chip and the package are connected such that a power supply voltage which will be produced by the switching regulator is supplied to the circuit area. The power supply circuit is supplied with a power supply voltage from the outside of the semiconductor apparatus.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: August 17, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Kozaburo Kurita
  • Patent number: RE43720
    Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: October 9, 2012
    Assignee: Rambus Inc.
    Inventors: Donald V. Perino, Sayeh Khalili