With Electrical Isolation Means Patents (Class 257/725)
  • Patent number: 7423340
    Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: September 9, 2008
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien Ping Huang, Yu-Po Wang, Chih-Ming Huang
  • Patent number: 7414299
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: August 19, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Tim J. Bales
  • Patent number: 7400038
    Abstract: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: July 15, 2008
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Takeo Sekino, Kenichi Shigenami, Shinichi Toi, Tatsuo Shimizu
  • Patent number: 7385283
    Abstract: A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the first and second devices comprises a metal-to-metal bond and a non-metal-to-non-metal bond.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: June 10, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weng-Jin Wu, Wen-Chih Chiou
  • Patent number: 7382056
    Abstract: The specification describes a multi-chip module (MCM) that contains an integrated passive device (IPD) as the carrier substrate (IPD MCM). Parasitic electrical interactions are controlled at one or both interfaces of the IPD either by eliminating metal from the interfaces, or by selective use of metal in parts of the MCM that are remote from the sensitive device components. The sensitive device components are primarily analog circuit components, especially RF inductor elements. In the IPD layout, the sensitive components are segregated from other components. This allows implementation of the selective metal approach. It also allows parasitic interactions on top of the IPD substrate to be reduced by selective placement of IC semiconductor chips and IC chip ground planes. In preferred embodiments of the IPD MCM of the invention, the IPD substrate is polysilicon, to further minimize RF interactions. The various methods of assembling the module may be adapted to keep the overall thickness within 1.0 mm.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: June 3, 2008
    Assignee: Sychip Inc.
    Inventors: Anthony M. Chiu, Yinon Degani, Charley Chunlei Gao, Kunquan Sun, Liquo Sun
  • Patent number: 7355264
    Abstract: The specification describes flip bonded dual substrate inductors wherein a portion of the inductor is constructed on a base IPD substrate, a mating portion of the inductor is constructed on a cover (second) substrate. The cover substrate is then flip bonded to the base substrate, thus mating the two portions of the inductor. Using this approach, a two level inductor can be constructed without using a multilevel substrate. Using two two-level substrates yields a four-level flip bonded dual substrate inductor.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: April 8, 2008
    Assignee: Sychip Inc.
    Inventors: Yinon Degani, Yinchao Chen, Yu Fan, Charley Chunlei Gao, Kunquan Sun, Liquo Sun
  • Patent number: 7345363
    Abstract: A semiconductor device includes a plastic package, at least one semiconductor chip and a rewiring level. The rewiring level includes an insulating layer and a rewiring layer. The rewiring layer includes either signal conductor paths and ground or supply conductor paths arranged parallel to one another and alternately, or only signal conductor paths arranged parallel to one another. In the latter case, an electrically conducting layer of metal which can be connected to ground or supply potential is additionally provided as a termination of the rewiring level or in the form of a covering layer.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: March 18, 2008
    Assignee: Infineon Technologies AG
    Inventors: Minka Gospodinova-Daltcheva, Harry Huebert, Rajesh Subraya, Jochen Thomas, Ingo Wennemuth
  • Patent number: 7335986
    Abstract: Disclosed is a wafer level chip scale package and a method for manufacturing the same. The wafer level chip scale package includes a semiconductor die having a first coating layer formed thereon; a redistribution layer formed on the first coating layer and connected to the bond pad; an electronic device placed on the first coating layer; a connection member for electrically connecting the electronic device and the redistribution layer; a conductive post formed on the redistribution layer with a predetermined thickness; a second coating layer for enclosing the first coating layer, the redistribution layer, the electronic device, the connection member, and the conductive post; and a solder ball thermally bonded to the conductive post while protruding to the exterior of the second coating layer. This construction makes it easy to manufacture stacked packages and chip scale packages in a wafer level.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: February 26, 2008
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Sung Su Park, Ho Cheol Jang, Jung Gi Jin
  • Patent number: 7330702
    Abstract: In one embodiment, the disclosure relates to a method and apparatus for inter-chip wireless communication system. The system includes a first microprocessor having a plurality of non-contact ports and a first RF communication circuit integrated with the first microprocessor; a second microprocessor also having a plurality of non-contact ports and a second RF communication circuit integrated therein. An RF communication protocol can be configured to receive data from each of the non-contact ports in parallel, multiplex and translate the data to a serial RF signal. Data communication can be accomplished using the wireless communication circuit on each chip. The RF communication between the first and the second integrated circuits using the communication protocol defines a non capacitive-coupling of the first and the second die.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: February 12, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker-Min Chen, Tsung-Yang Hung
  • Patent number: 7327022
    Abstract: A novel micro optical system as a platform technology for electrical and optical interconnections, thermal and mechanical assembly and integration of electronic, optoelectronic, passive and active components. This platform provides optical coupling and chip-to-chip interconnection by microwave electrical, optical guided and unguided waves, and power or bias electrical contacts or interfaces by a novel chip in flexible circuit, rigid or inflexible embodiments.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: February 5, 2008
    Assignee: General Electric Company
    Inventors: Glenn Scott Claydon, Matthew Christian Nielsen, Samhita Dasgupta, Robert John Filkins, Glenn Alan Forman
  • Patent number: 7327019
    Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: February 5, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
  • Patent number: 7321164
    Abstract: A stack structure with semiconductor chips embedded in carriers comprises two carriers stacking together as a whole, at least two semiconductor chips having active surfaces with electrode pads and inactive surfaces corresponding thereto placed in the cavities of the carriers, at least one dielectric layer formed on the active surface of the semiconductor chip and the surface of the carrier, at least a conductive structure formed in the opening of the dielectric layer, and at least a circuit layer formed on the surface of the dielectric layer wherein the circuit layer is electrically connected to the electrode pad by the conductive structure, so as to form a three-dimensional module to increase the storage capacity dramatically and integrate the semiconductor chips in the carriers for efficiently reducing the size of the module, so that the combinations can be changed flexibly to form the required storage capacity according to the demands.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: January 22, 2008
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Shih-Ping Hsu
  • Patent number: 7315455
    Abstract: More compact, thinner, shorter and lighter surface-mounted electronic component modules and their manufacturing methods at low costs, thus making them industrially highly valuable are available. Such the component includes a wiring substrate having wiring patterns formed on one side and external connection terminals formed on the other side, the wiring patterns and the external connection terminals being connected with each other by via holes or through holes; a plurality of electronic component devices mounted on the one side of the wiring substrate; and an exterior resin layer formed on the wiring substrate which covers the plurality of electronic component devices, wherein at least one of the plurality of electronic component devices is fastened face up to the one side of the wiring substrate, the connection terminal of the electronic component device fastened face up and the wiring pattern or the connection terminal of another electronic component device being connected with each other by wire.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: January 1, 2008
    Assignee: Fujitsu Media Devices Ltd.
    Inventors: Osamu Furukawa, Toshihiko Murata, Osamu Ikata
  • Patent number: 7304372
    Abstract: A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: December 4, 2007
    Assignee: International Rectifier Corporation
    Inventors: Kunzhong Hu, Chuan Cheah
  • Patent number: 7298045
    Abstract: A first semiconductor element and second semiconductor element are bonded via die-bonding material. A first electrode of the first semiconductor element and a third electrode are joined, by means of flip-chip bonding, to a semiconductor carrier that has the third electrode on the one face of the semiconductor carrier and a fourth electrode on the perimeter of the other face of the semiconductor carrier. The bonding pad of the second semiconductor element and the fourth electrode of the semiconductor carrier are connected via fine metal wire by means of wire bonding. The periphery of the first semiconductor element and the wiring portion of the fine metal wire are filled with insulating sealing resin between the semiconductor carrier and second semiconductor element and the sealing fill region for the sealing resin is formed substantially the same as the external dimensions of the second semiconductor element.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: November 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd
    Inventors: Hisaki Fujitani, Fumito Itou, Toshitaka Akahoshi, Toshiyuki Fukuda
  • Patent number: 7282789
    Abstract: A back-to-back semiconductor device assembly includes two vertically mountable semiconductor devices, the backs of which are secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the assembly. The semiconductor devices may include semiconductor dice, or they may be devices that have yet to be separated from other devices carried by the same substrates.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Larry D. Kinsman
  • Patent number: 7276790
    Abstract: An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined distance apart from the back side of the second semiconductor device. Discrete conductive elements are extended between the active surface of the first semiconductor device and the substrate prior to positioning of the second semiconductor device. Intermediate portions of the discrete conductive elements pass through an aperture formed between the active surface of the first semiconductor chip, the back side of the second semiconductor chip, and two of the spacers positioned therebetween. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Eric Tan Swee Seng
  • Patent number: 7268422
    Abstract: What is invented is a semiconductor device (10) comprising a pellet (12) having a ground electrode (18), an outside signal terminal (15) connected to the pellet (12), so as to receive signal which is likely to include noise. Therein, said outside signal terminal (15) is surrounded with a ground terminal (17) connected to said ground electrode (18) in at least a half periphery.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: September 11, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 7259450
    Abstract: A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are connected to traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The input/output leads provide means for connecting the housing with the electronic device or system into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: August 21, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Eugene H. Cloud, Larry D. Kinsman
  • Patent number: 7242078
    Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: July 10, 2007
    Assignee: General Semiconductor, Inc.
    Inventors: Paddy O'Shea, Eamonn Medley, Finbarr O'Donoghue, Gary Horsman
  • Patent number: 7242087
    Abstract: A flexible printed circuit board includes a substrate layer composed of insulating material, a protection circuit of a thin-film capacitor element, the protection circuit including a first wiring layer on the substrate layer, a dielectric layer, and a counter electrode layer. At least a portion of each of the first wiring layer and the counter electrode layer serves as a terminal. The front surface of each of the first wiring layer and the counter electrode layer, except the terminal portion, is covered with an insulating coating.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: July 10, 2007
    Assignee: Alps Electric Co., Ltd.
    Inventors: Akira Nakano, Yoshiomi Tsuji, Yoshinari Higa
  • Patent number: 7230329
    Abstract: A method is provided to realize a three-dimensional mounting structure of different types of packages. By bonding protruding electrodes onto lands, which are formed on a first carrier substrate, second and third carrier substrates are mounted on the first carrier substrate such that ends of the second and third carrier substrates are arranged above a semiconductor chip.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: June 12, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Toshihiro Sawamoto, Hirohisa Nakayama, Akiyoshi Aoyagi
  • Patent number: 7230320
    Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: June 12, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Doi, Noriyoshi Urushiwara, Akira Matsushita
  • Patent number: 7227249
    Abstract: A three-dimensional stacked semiconductor package includes first and second chips, first and second adhesives, first and second wire bonds, a lead and an encapsulant. The chips are disposed on opposite sides of the lead, and the wire bonds contact the same side of the lead.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: June 5, 2007
    Assignee: Bridge Semiconductor Corporation
    Inventor: Cheng-Lien Chiang
  • Patent number: 7227240
    Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: June 5, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: James Knapp, Francis Carney, Harold Anderson, Yenting Wen, Cang Ngo
  • Patent number: 7227251
    Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: June 5, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
  • Patent number: 7224053
    Abstract: A semiconductor device which integrates a plurality of semiconductor chips into a single package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a plurality of first bonding pads outputting first signals having a first level. The second semiconductor chip includes a plurality of second bonding pads and a plurality of third bonding pads. The plurality of second bonding pads is electrically coupled to a part of the plurality of first bonding pads to receive the first signals having the first level from the first semiconductor chip through the part of the plurality of first bonding pads. The plurality of third bonding pads converts the first signals received through the plurality of second bonding pad into second signals having a second level different from the first level and outputs the second signals through the plurality of third bonding pads.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: May 29, 2007
    Assignee: Ricoh Company, Ltd.
    Inventor: Hitoshi Yamamoto
  • Patent number: 7221244
    Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: May 22, 2007
    Assignee: Motorola, Inc.
    Inventors: John C. Estes, Rodolfo Lucero, Anthony M. Pavio
  • Patent number: 7221040
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 22, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Tim J. Bales
  • Patent number: 7199469
    Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 3, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Toru Ishida, Tetsuharu Urawa, Fujio Ito, Tomoo Matsuzawa, Kazunari Suzuki, Akihiko Kameoka, Hiromichi Suzuki, Takuji Ide
  • Patent number: 7176566
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: February 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Tim J. Bales
  • Patent number: 7176560
    Abstract: A semiconductor device having a chip-on-chip structure wherein; a first semiconductor chip with a memory macro control circuit where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; and a second semiconductor chip with memory macro having input/output terminals for the normal operation mode and for the test mode where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; are adhered to each other in a form so that the surfaces of the chips are opposed to each other and so that the inter-chip connection terminals of the first semiconductor chip and the inter-chip connection terminals of the second semiconductor chip are connected to each other; is provided wherein a multiplexer circuit and a demultiplexer circuit are provided with the first semiconductor chip and the second semiconductor chip so that a signal is inputted to, or is outputted from, the
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenji Motomochi
  • Patent number: 7173325
    Abstract: Structures and techniques for mounting semiconductor dies are disclosed. In one embodiment, the invention includes a stack of printed wiring board assemblies that are connected via interconnection components. At least one of the printed wiring board assemblies includes an interposer substrate having a constraining layer that includes carbon.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: February 6, 2007
    Assignee: C-Core Technologies, Inc.
    Inventors: Kalu K. Vasoya, Bharat M. Mangrolia
  • Patent number: 7173340
    Abstract: A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding pad (20G), a first bonding pad (20C) controllable to function as either an input or an output, and a second bonding pad (20E) controllable to function as either an output or an electrically floating pad in response to a corresponding input/output function control signal. The top die (30) is stacked on the bottom die (20) and the first bonding pad (20C) of the bottom die (20) is wire bonded to the first bonding pad (30C) of the top die (30). A first reference voltage (VDD) on the function control bonding pad of the bottom die configures its first bonding pad as an output and its second bonding pad as electrically floating, and a second reference voltage (VSS) on the function control bonding pad of the top die configures its first bonding pad as an input and its second bonding pad as an output, to thereby provide the daisy chain function.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: February 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Binling Zhou, James L. Todsen, Brian D. Johnson
  • Patent number: 7166915
    Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, David R. Hembree, James M. Wark
  • Patent number: 7166918
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Tim J. Bales
  • Patent number: 7157309
    Abstract: An elongated strip of a sheetlike substrate bearing microelectronic elements such as semiconductor chips is advanced in a downstream direction through one or more folding stations where successive portions of the substrate are folded so as to form a strip including a plurality of fold packages, each including confronting top and bottom runs and a fold region with one or more of the runs bearing one or more microelectronic elements. The strip incorporating the plural fold packages can be wound on a reel or otherwise handled, stored and shipped to a subsequent manufacturing operation, where individual fold packages can be severed from the strip.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: January 2, 2007
    Assignee: Tessera, Inc.
    Inventors: Nicholas J. Colella, Giles Humpston
  • Patent number: 7123107
    Abstract: To provide a piezoelectric oscillator which can be reduced in size by reducing the planar size. With regard to a layered lead frame comprising two lead frames and, connection leads for connection with a piezoelectric resonator are formed on the upper lead frame and the connection leads are erected upwards so as to form connection terminals, and mounting leads for mounting to a mounting board are formed on the lower lead frame and the mounting leads are erected downwards so as to form mounting terminals, and an IC forming an oscillating circuit is mounted on the layered lead frame, the piezoelectric resonator formed by sealing a piezoelectric resonator element within a package is mounted on the layered lead frame, and the layered lead frame and the piezoelectric resonator are sealed within a resin package such that the principal surface of the mounting terminals are exposed outwards, thereby forming a completed article.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: October 17, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Yugo Koyama, Katsuhiko Miyazaki, Kazuhiko Shimodaira, Yukari Nakajima
  • Patent number: 7122876
    Abstract: A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: October 17, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Kuo Wu, Edward Chiang, Shun-Liang Hsu
  • Patent number: 7095113
    Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: August 22, 2006
    Assignee: Diodes Incorporated
    Inventors: Tan Xiaochun, Shi Jingping
  • Patent number: 7088964
    Abstract: A true single-chip radio for bidirectional wireless communications includes a bulk substrate, at least one integrated antenna, at least one transceiver, baseband circuitry and at least one filter all integrally formed in or on the substrate. The radio preferably includes a low-loss dielectric propagating layer disposed beneath the substrate to improve antenna gain. The integrated antenna can be an adaptive array for beamforming.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: August 8, 2006
    Assignee: University of Florida Research Foundation, Inc.
    Inventor: Kenneth Kyongyop O
  • Patent number: 7053466
    Abstract: A contact-less high-speed signaling interface and method provide for the communication of high-speed signals across an interface, such as a die-substrate interface or die-die interface. The interface includes a transmission-line structure disposed on a dielectric medium to carry a high-speed forward incident signal, and another transmission-line structure disposed on another dielectric medium and substantially aligned with the other transmission-line structure to generate a coupled high-speed signal in a direction opposite to the incident signal.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 30, 2006
    Assignee: Intel Corporation
    Inventors: Victor Prokoflev, Henning Braunisch
  • Patent number: 7045884
    Abstract: A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: May 16, 2006
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 7042085
    Abstract: A method for packaging electronic assemblies and a multiple chip package, at least one power semiconductor chip being applied to a base plate using a first solder, at least one logic chip being applied to the base plate, the logic chip and the base plate being positioned electrically insulated from one another, at least one logic chip being connected to the at least one power semiconductor chip using signal transmission lines, and the electronic assembly including the at least one power semiconductor chip and the at least one logic chip being packaged using a molding compound in order to provide a multiple chip package.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: May 9, 2006
    Assignee: Robert Bosch GmbH
    Inventors: Kuno Wolf, Stephan Ernst, Robert Plikat, Wolfgang Feiler
  • Patent number: 7030455
    Abstract: To isolate at least one electric or electronic element (16, 58), for example an interconnection integrated onto a semiconductor substrate (12), this device comprises at least one isolation means chosen from an isolating layer (84, 86, 90) extending in the substrate and an assembly whose height exceeds that of the element and which comprises, on either side of the element, at least two superposed conductors (60 62 64, 66 68 70), which are integrated into the substrate and extend along the element.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: April 18, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Patrice Gamand, Alain De La Torre
  • Patent number: 7026664
    Abstract: A semiconductor chip package that includes a DC—DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC—DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: April 11, 2006
    Assignee: Power-One, Inc.
    Inventors: Mysore Purushotham Divakar, David Keating, Antoin Russell
  • Patent number: 7002256
    Abstract: A semiconductor device including a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area, circuit patterns formed on the substrate in the circuit area, a first dummy pattern which is formed of the same material as the circuit pattern, formed in the dummy area, the dummy pattern encompassing the circuit area, a first insulating layer formed on an entire surface of the semiconductor substrate, a second insulating layer formed only on the first insulating layer which is formed on the semiconductor substrate and on the circuit patterns; and a third insulating layer formed on the exposed first insulating layer and the second insulating layer.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: February 21, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroki Nakamura
  • Patent number: 6998721
    Abstract: In one embodiment, a device includes but is not limited to: a first integrated circuit affixed to a substrate; an electronic circuit component affixed to the substrate; a first encapsulation structure encasing the first integrated circuit; a second integrated circuit affixed to the first encapsulation structure; and a second encapsulation structure which at least partially encases the first encapsulation structure, the first integrated circuit, and the electronic component.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: February 14, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: Tiao Zhou
  • Patent number: 6995463
    Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: February 7, 2006
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 6992380
    Abstract: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric material layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: January 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Kenji Masumoto