Abstract: A hermetic package for electronic components which is made of metallic silicon is disclosed. The package includes a plurality of silicon elements which are bonded together. In the first embodiment, a cavity is hollowed out in the cover to house the Application Specific Integrated Circuit oscillator and the resonator. In a second embodiment, the cavity is formed in the base member with a plurality of pedestal shelves to hold the resonator above and out of contact with the electrical circuitry for the oscillator and thermal controls.

Abstract: An integrated circuit includes a substrate including an active area and a gas phase deposited packaging material encapsulating the active area.

Abstract: A light emitting device package and a method of manufacturing the light emitting device package are provided. A base is first provided and a hole is formed on the base. After a light emitting portion is formed on the base, a mold die is placed on the light emitting portion and a molding material is injected through the hole. The mold die is removed to complete the package.

Abstract: Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed.

Abstract: An integrated circuit having a semiconductor sensor device including a sensor housing partly filled with a rubber-elastic composition is disclosed. One embodiment has a sensor chip with sensor region arranged in the interior of the housing. The sensor housing has an opening to the surroundings which is arranged in such a way that the sensor region faces the opening. The sensor chip is embedded into a rubber-elastic composition on all sides in the interior of the housing. The sensor housing has a sandwich-like framework having three regions arranged one above another, including an intermediate region with the rubber-elastic composition.

Abstract: A low-temperature inorganic dielectric ALD film (e.g., Al2O3 and TiO2) is deposited on a packaged or unpackaged chip device so as to coat the device including any exposed electrical contacts. Such a low-temperature ALD film generally can be deposited without damaging the packaged chip device. The ALD film is typically deposited at a sufficient thickness to provide desired qualities (e.g., hermeticity for the entire packaged chip device, passivation for the electrical contacts, biocompatibility, etc.) but still allow for electrical connections to be made to the electrical contacts (e.g., by soldering or otherwise) directly through the ALD film without having to expose the electrical contacts.

Abstract: Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Abstract: A plastic housing includes plastic external faces and the underside of the plastic housing comprises external contact areas on which external contacts are arranged. The plastic external faces are covered by a closed metal layer apart from the underside, wherein the boundary layer between plastic external faces and the closed metal layer includes exposed electrically conductive inclusions of the plastic of the housing.

Abstract: To provide a semiconductor device which can increase reliability with respect to external force, especially pressing force, while the circuit size or the capacity of memory is maintained. A pair of structure bodies each having a stack of fibrous bodies of an organic compound or an inorganic compound, which includes a plurality of layers, especially three or more layers, is impregnated with an organic resin, and an element layer provided between the pair of structure bodies are included. The element layer and the structure body can be fixed to each other by heating and pressure bonding. Further, a layer for fixing the element layer and the structure body may be provided. Alternatively, the structure body fixed to an element layer can be formed in such a way that after a plurality of fibrous bodies is stacked over the element layer, the fibrous bodies are impregnated with an organic resin.

Abstract: An apparatus for housing a micromechanical system includes a substrate with a surface on which the micromechanical system is formed, a transparent cover and a dry film layer arrangement between the surface of the substrate and the transparent cover. The dry film layer arrangement has an opening, so that the micromechanical system adjoins the opening.

Abstract: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.

Abstract: A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.

Abstract: This invention is an adhesive film comprising (a) a top layer that is substantially UV curable and that has a glass transition temperature of 50° C. or less; and (b) a bottom layer that is substantially not UV-curable. Additional embodiments include a bundled wafer lamination film, a semiconductor wafer with a multilayer adhesive film attached, a process for attaching a semiconductor die to a substrate, and a method of preventing individually diced dies from sticking to one another.

Abstract: A modularly constructed electrical component having a module substrate, preferably, of Si, and having one or more preferably un-housed chips placed on the module substrate while being electrically connected thereto and each joined to the module substrate, e.g., by direct wafer bonding. A recess is provided in the module substrate so that a closed hollow space is formed when the chip is joined to the module substrate. The hollow space is not formed by a protective cap, which surrounds the chip and, with the module substrate, closes it on all sides. Rather it is formed by the joining of opposing contact areas of the chip underside and of the upper side of the module substrate. The component can be economically produced because it does not require a protective cap for creating the hollow space. The component has a higher yield than monolithic integration of the functional units.

Abstract: In a circuit module for a high frequency, a resistance film is formed on a side of a semiconductor circuit chip, mounted above a dielectric substrate through ground metal layers, opposite to the dielectric substrate. A distance from the ground metal layer to the resistance film is a ¼ wavelength at a predetermined frequency, and the resistance film has a sheet resistance equal to a characteristic impedance of air. A second dielectric substrate with the metal layer formed on a side opposite to the resistance film can be mounted. When being adhered to the second dielectric substrate, the resistance film has a characteristic impedance determined by a permittivity of a material of the semiconductor circuit chip. When being formed in space from the semiconductor circuit chip, the resistance film has a sheet resistance equal to a characteristic impedance of air. The thickness of the second dielectric substrate is a ¼ wavelength in a desired frequency.

Abstract: A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.

Abstract: A directional microphone assembly for a hearing aid, and methods of assembling a directional microphone, are provided. The hearing aid has one or more microphone cartridge(s), and first and second sound passages. Inlets to the sound passages, or the sound passages themselves, are spaced apart such that the shortest distance between them is less than or approximately equal to the length of the microphone cartridge(s). A sound duct and at least one surface of a microphone cartridge may form each sound passage, where the sound duct is mounted with the microphone cartridge. Alternatively, each sound duct may be formed as an integral part of a microphone cartridge.

Abstract: A semiconductor packaging structure is provided. The structure includes a base layer comprising alloy 42; die attached on a first side of the base layer; and an interconnect structure on the die, wherein the interconnect structure comprises vias and conductive lines connected to the die.

Abstract: Hermeticity of microcircuit packages is achieved in one embodiment by recognition that water can penetrate the ceramic structure and thus the ceramic structure is sealed and the edges of the ceramic package are metallically bonded to the electronic package. In one embodiment, a clear ceramic dielectric compound is sprayed on the ceramic and then the package is glazed.

Abstract: To hermetically seal a cavity in a microelectronic component, a cap located in a sealing device is positioned above the orifice opening into the cavity. The cap plastically deforms to seal the cavity. The sealing device includes a cavity permitting the cavity of the microelectronic component to be filled. The sealing device slides along the component so as to be positioned opposite either the filling cavity, or the cap.

Abstract: One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In this aspect, a die and leadframe are fully encapsulated in a first plastic casing. The first plastic casing is fully encapsulated in turn with a second plastic casing. The two casings have different compositions. The first plastic casing, for example, may be made of a thermoset plastic material and the second plastic casing may be made of a thermoplastic material. The first plastic casing may have recesses, indentations and/or slots suitable for securing it to the second plastic casing. In some embodiments, a corrosion resistant coating is added to the second plastic casing. Methods for forming semiconductor packages suitable for use in high stress environments are also described.

Abstract: Provided is a semiconductor package, and in particular a semiconductor package which is capable of electrically connecting to the outside without a lead.

Abstract: Eutectic Flow Containment in a Semiconductor Fabrication Process A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.

Abstract: A sensor element is capped by bonding or otherwise forming a cap on a sensor element. The sensor may be hermetically sealed by using a hermetic cap and hermetic bonding material or by applying a hermetic coating. The sensor may be filled with a gas at an elevated pressure. The sensor may alternatively or additionally be filled with a special gas, such as a gas having a density-to-viscosity ratio above approximately 0.2.

Abstract: A marking method is provided for putting markings on the surface of a packaged semiconductor device. The semiconductor device includes a semiconductor chip and a resin package for covering the semiconductor chip. The method includes the steps of forming a groove in the obverse surface of the resin package, and filling the groove with a resin that is visually distinguishable from the resin package.

Abstract: Embodiments of the present invention provide a system and method for manufacturing integrated circuit (IC) chip packages. In one embodiment, the integrated circuit (IC) chip package can include an IC chip and a substrate coupled to the IC chip. The substrate can include a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers. The IC chip can be coupled to copper circuitry bonded to one of the outermost amorphous glass layers.

Abstract: A multi-functional metal shield case and a method for making the same are provided. The multi-functional metal shield case includes a metal main body and an electrically non-conductive and heat conductive silicon layer. The metal main body includes a base and sidewalls integrally bent along edges of the base, and the electrically non-conductive and heat conductive silicon layer is formed on inner sides of the base and the sidewalls. Accordingly, heat can be rapidly transferred to the metal main body and emitted to an outside. Since the heat conductive silicon layer is non-conductive, an electric shock does not occur between the electronic component and the metal shield case. Further, since the heat conductive silicon layer is in contact with the electronic component, heat can be transferred more rapidly.

Abstract: Methods for coating a protective material on a semiconductor substrate to protect a back surface thereof from defects are provided, by depositing a diamond-like coating (DLC) material thereon at a low temperature, e.g. between about 150° C. to about 350° C.

Abstract: The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217).

Abstract: A semiconductor device includes: a semiconductor chip; a package for accommodating the chip, wherein the package has a box shape with an opening and a bottom; and a cover for sealing the opening of the package. The semiconductor chip is disposed on the bottom of the package. The cover has a plate shape. The cover includes a protrusion, which is disposed at a center of the plate shape. The protrusion protrudes toward an outside of the package.

Abstract: A semiconductor device includes a laminated substrate formed by laminating a plurality of semiconductor substrates, a concave part formed in the laminated substrate, and a semiconductor element mounted in the concave part. A method of manufacturing a semiconductor device includes a first step of forming a laminated substrate by laminating a plurality of semiconductor substrates, a second step of forming a concave part by etching the laminated substrate, and a third step of mounting a semiconductor element in the concave part.

Abstract: A plurality of parallel rib prototypes are provided on a flat base plate. A plurality of semiconductor elements are placed in each trench between adjacent ones of the rib prototypes, and a transparent member is bonded to each of the semiconductor elements. Electrode pads of the semiconductor elements are wire bonded to connection electrodes. The trenches are then filled with an encapsulating resin. Thereafter, middle portions, in the longitudinal direction, of the rib prototypes are cut with a dicing saw, and adjacent ones of the semiconductor elements are separated from each other, thereby obtaining semiconductor devices.

Abstract: A MEMS device including a getter film formed inside a hermetic chamber provides stable performance of the MEMS device by electrically stabilizing the getter film. The MEMS device includes a movable portion and a fixed portion formed inside the hermetic chamber. The hermetic chamber is formed by a base material of the MEMS device and glass substrates and having a cavity and cavities made therein. A part of any continuous getter film formed inside the hermetic chamber connects to only one of any one or a plurality of predetermined electrical potentials of the fixed portion and a ground potential of the fixed portion through the base material of the MEMS device.

Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.

Abstract: An optical device with a CAN package is disclosed, where the cap is resistance-welded to the stem without causing failures due to fragments by the welding flying within the package. The cap of the invention has a flange portion to be welded to the stem. The flange portion provides a ringed groove in addition to the ringed projection for the welding. The fragment due to the welding may be captured in the ringed groove and is prevented from flying within the package. The ringed groove and the ringed projection are simultaneously formed in the stamping to form the body portion of the cap.

Abstract: In an electronic parts packaging structure of the present invention, an electronic parts is mounted or formed on a silicon circuit substrate having a structure in which wiring layers on both sides thereof are connected to each other through a through electrode, and a protruded bonding portion which is ring-shaped and is made of glass, of a seal cap having a structure in which a cavity is constituted by the protruded bonding portion, is anodically bonded to a bonding portion of the silicon circuit substrate, thus, the electronic parts is hermetically sealed in the cavity of the sealing cap.

Abstract: Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.

Abstract: In some embodiments, an injection molded metal IC package stiffener and package-to-package interconnect frame is presented. In this regard, an apparatus is introduced comprising a microelectronic device package substrate, a microelectronic device coupled with a top surface of the package substrate, and an injection-molded, metal stiffener coupled with the package substrate, wherein the stiffener includes a central opening and at least partially surrounds the microelectronic device, and wherein the stiffener includes a plurality of vias that each couple a contact on a bottom surface of the stiffener with a respective contact on a top surface of the stiffener. Other embodiments are also disclosed and claimed.

Abstract: Disclosed is a semiconductor device package. The semiconductor device package includes at least one semiconductor device acting as a heating source, a package substrate having an upper surface on which the semiconductor device is mounted, the package substrate at least having a higher heat conductivity than that of the semiconductor device, and a fiber-reinforced polymer composite formed to surround a side surface of the package substrate, the polymer composite including fibers acting as a reinforcing material and a resin mass embedding the fibers therein.

Abstract: The likelihood of exfoliation of a sealing resin layer at a pad electrode part is reduced so that the reliability of a circuit apparatus is improved. A circuit apparatus includes a wiring layer, a gold plating layer, an insulating resin layer, a circuit element, a conductive member and sealing resin layer. The gold plating layer is formed in an wiring layer area for the pad electrode. The surface outside the area is roughened. The insulating resin layer is formed so as to cover the wiring layer and to have an opening in an area in which the pad electrode is formed. The circuit element is mounted on a predetermined area on the insulating resin layer. The sealing resin layer is formed on the insulating resin layer so as to entirely cover the circuit element and the opening for the pad electrode. The sealing resin layer, in the area for the pad electrode, is in contact with the gold plating layer and the wiring layer.

Abstract: In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus.

Abstract: A semiconductor package includes a package-substrate, a first cavity formed on a first main surface of the package substrate, a first semiconductor chip mounted on the bottom surface of the first cavity, a first resin layer filled into the first cavity, and a thermal stress canceller member mounted on the package substrate for cancelling the thermal stress caused by the difference in the thermal expansion rates between the package substrate and mounting section including a first semiconductor chip and a first resin layer. The thermal stress canceller member may include a second cavity, a second resin layer filled into the second cavity, and a semiconductor chip.

Abstract: A wireless communication device such as a cell phone is rendered temporarily inoperable by enclosing the device in a container such as a heat sealable bag (1) which has been metallized so that when the device (2) is sealed in the container (1) it is surrounded by a metal layer (9) which blocks signals to and from the device (3) to thereby render it inoperable. The device is sealed within the container (1) by a seal such as a heat seal which will reveal any attempt to remove the device from the container.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: An ink jet print head includes a silicon ink jet chip, a print head holder, configured to carry and support the silicon chip, and a glass plate, bonded between the silicon chip and the print head holder. The ink jet chip has a coefficient of thermal expansion ?s. The print head holder has a holder wall thickness, and a coefficient of thermal expansion ?h that is substantially different from ?s. The glass plate has a coefficient of thermal expansion ?g that is substantially similar to ?s, and a thickness at least as great as the holder wall thickness, whereby stress created by differential thermal expansion between the silicon chip and the holder is attenuated by the glass plate.

Abstract: A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the contact surface. The ceramic stiffener is disposed on the carrying surface and has a first opening. In addition, the chip is disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads.

Abstract: A semiconductor device including; a bottom plate having a laminated structure in which between a first and a second metal plates a third metal plate harder than these metal plates is clipped, a concave portion formed by removing a part of the first metal plate laminated on the surface of the bottom plate and the third metal plate laminated there under and expose the second metal plate, a semiconductor element arranged in the concave portion H, circuit board connected with the semiconductor element arranged on the surface of the bottom plate, circuit boards arranged on the surface of the bottom plate, a sidewall made of metal and fixed on the bottom plate surrounding the circuit boards and the semiconductor element, a metal lead provided so as to penetrate the side wall through an insulator, and a lid made of metal provided to block an opening formed by the sidewall.

Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: Vinyl addition polymer compositions, methods for forming such compositions, methods for using such compositions to form microelectronic and optoelectronic devices are provided. The vinyl addition polymer encompassed by such compositions has a polymer backbone having two or more distinct types of repeat units derived from norbornene-type monomers independently selected from monomers of Formula I: wherein each of X, m, R1, R2, R3, and R4 is as defined herein and wherein a first type of repeat unit is derived from a glycidyl ether substituted norbornene monomer and a second type of repeat unit is derived from an aralkyl substituted norbornene monomer.

Abstract: The waveform signals of ultrasonic waves reflected by a plurality of interfaces in a measurement object are received, the waveform signal of a reflected wave on a reference interface inside the measurement object is detected based on the amplitudes of the received waveform signals, and evaluation is made on the bonded condition of an interface to be measured based on the waveform signal of the reflected wave on the reference interface.