Combined With Electrical Contact Or Lead Patents (Class 257/734)
  • Patent number: 9594865
    Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: March 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
  • Patent number: 9589815
    Abstract: An IC packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a metal pad and an insulating layer and the insulating layer has an opening to expose the meal pad. The method also includes forming an under-the-ball meal electrode on the exposed metal pad. The under-the-ball metal electrode has an electrode body and an electrode tail, the electrode body is located at a bottom portion of the under-the-ball metal electrode and is in contact with the metal pad, and the electrode tail is located at a top portion of the under-the-ball meal electrode. Further, the method includes forming a solder ball on the under-the-ball metal electrode.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: March 7, 2017
    Assignee: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
    Inventors: Chang-Ming Lin, Lei Shi, Xiao-Chun Wu
  • Patent number: 9583465
    Abstract: Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang-Wei Cheng, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 9576926
    Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen
  • Patent number: 9576880
    Abstract: A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The method further includes forming a liner material on the material over or within the via of the dual damascene structure. The method further includes filling any remaining portions of the via and a trench of the dual damascene structure with additional material.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Baozhen Li, Chih-Chao Yang
  • Patent number: 9570413
    Abstract: An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Wei-Yu Chen, Ming-Da Cheng, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 9568541
    Abstract: A semiconductor package includes a semiconductor die, an antenna embedded in insulating material contacting a first main side of the semiconductor die and electrically connected to a first pad of the semiconductor die and a coupling structure embedded in the insulating material, electrically connected to a second pad of the semiconductor die and spaced from the antenna. The coupling structure is configured to sense energy radiated from the antenna or a feedline connected to the antenna. The semiconductor die includes a transmitter circuit operable to drive a signal onto the antenna through the feedline. The semiconductor die also includes a transmit path verification circuit operable to indicate if the antenna is electrically connected to the first pad of the semiconductor die based on a signal from the coupling structure that corresponds to the energy sensed by the coupling structure.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventor: Saverio Trotta
  • Patent number: 9570414
    Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tsukiyama, Masatoshi Fukuda, Yukifumi Oyama, Shinya Fukayama
  • Patent number: 9559002
    Abstract: A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: January 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Taek Lee, Eun-Ji Kim, Sin-Woo Kang, Yeong-Lyeol Park, Sung-Dong Cho
  • Patent number: 9558936
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes an accommodation module configured to accommodate a substrate. The apparatus further includes a first flow channel including first openings configured to emit a first gas into the accommodation module. The apparatus further includes a second flow channel including second openings configured to emit the first gas into the accommodation module, a number or a size of the second openings being different from a number or a size of the first openings. The apparatus further includes a controller configured to control supplying of the first gas to the first and second flow channels such that the first gas is emitted from the first openings at a first flow velocity and the first gas is emitted from the second openings at a second flow velocity different from the first flow velocity.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hajime Nagano
  • Patent number: 9559077
    Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 31, 2017
    Assignee: NXP USA, Inc.
    Inventors: Akhilesh K. Singh, Rama I. Hegde, Nishant Lakhera
  • Patent number: 9543161
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a flowable-material (FM) layer over a substrate. The substrate has a first region and a second region. A top surface of the FM layer in the first region is higher than a top surface of the FM layer in the second region. The method also includes forming a plurality of trenches in the FM layer in the first region and performing annealing process to reflow the FM layer, wherein the plurality of trenches are filled with the FM layer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Hao Su, Yu-Lun Liu, Chi-Kang Chang, Shih-Chi Fu, Kuei-Shun Chen, Chloe Hsu
  • Patent number: 9536750
    Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 3, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Cheng Chi, Fee Li Lie, Chi-Chun Liu, Ruilong Xie
  • Patent number: 9530703
    Abstract: Provided is a method for manufacturing a silicon carbide semiconductor device capable of preventing an increase in a cost of manufacturing one chip while favorably maintaining forward characteristics of the semiconductor device including (a) inspecting the characteristics of the forward conduction of body diodes as element structures; (b) classifying the body diode and the body diode as either a first group suitable for forward conduction or a second group unsuitable for forward conduction on the basis of an inspection result; and (c) manufacturing a silicon carbide semiconductor MOSFET that requires forward conduction using the body diode classified into the first group or manufacturing a silicon carbide semiconductor MOSFET that does not need forward conduction using the body diode classified into the second group.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 27, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Sugimoto, Takuyo Nakamura
  • Patent number: 9524946
    Abstract: An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 20, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsumi Ishii, Masashi Yamaura
  • Patent number: 9502583
    Abstract: A method for forming a semiconductor device includes providing a substrate structure, which includes a nanowire structure supported by two isolation regions on a substrate. The nanowire structure includes a first nanowire and a second nanowire having different high mobility semiconductor materials and conductivity types. A multi-layer film structure is formed surrounding the nanowire structure and includes a conductive material layer sandwiched between two dielectric layers. A plurality of first electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the first nanowire, and a plurality of second electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the second nanowire. A third electrode is formed to contact one end of the nanowire structure, and a fourth electrode is formed to contact the other end of the nanowire structure. A fifth electrode is formed and coupled to a center portion of the nanowire structure.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: November 22, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Deyuan Xiao
  • Patent number: 9496050
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the dies stores a flag for indicating whether a threshold number of cells of the dies have failed during test operations.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: November 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Boon Hor Lam, Dennis Montierth
  • Patent number: 9484205
    Abstract: A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn
  • Patent number: 9472426
    Abstract: A method for manufacturing a packaging substrate includes: patterning a first photo-resisting layer having first openings on a copper foil layer to expose portions of the copper foil layer; patterning a removable second photo-resisting layer having second openings on the first photo-resisting layer to expose the first openings; filling copper into the first and second openings to form base portions and a first wiring layer; orderly forming a first dielectric layer and a second wiring layer on the first wiring layer; patterning a removable third photo-resisting layer comprising covering portions opposite to the base portions on the copper foil layer; and etching the copper foil layer to form protruding portions connected to and corresponding to the base portions to define a copper pillar bump, a size of the copper pillar bump gradually increasing from the protruding portions to the base portions.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: October 18, 2016
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventor: Wei-Shuo Su
  • Patent number: 9466760
    Abstract: A method of manufacturing a horizontal power LED device includes constructing a light-emitting structure on a substrate, etching the light-emitting structure, fabricating an electrode, forming an insulating film, forming a metal substrate, removing the substrate from the light-emitting structure, and forming an n-pad. A high-power and high-efficiency horizontal LED device is manufactured by the method of manufacturing the same.
    Type: Grant
    Filed: April 23, 2016
    Date of Patent: October 11, 2016
    Assignees: CLPHOTONICS CO., LTD.
    Inventors: Jeong Woon Bae, Seong Wook Ryu, Jong Young Shim
  • Patent number: 9463976
    Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements (101B, 110D) formed in different layers of a multi-layer semiconductor structure (100) and one or more cap devices (200, 300) bonded to the multi-layer semiconductor structure (100) to protect any exposed inertial transducer element from ambient environmental conditions.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 11, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Paul M. Winebarger
  • Patent number: 9431323
    Abstract: To form a semiconductor device, a through electrode is formed in a semiconductor die, and a dielectric layer is then formed to cover the through electrode. The dielectric layer has an opening by being partially etched to allow the through electrode to protrude to the outside, or has a thickness thinner overall so as to allow the through electrode to protrude to the outside. Subsequently, a conductive pad is formed on the through electrode protruding to the outside through the dielectric layer by using an electroless plating method.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: August 30, 2016
    Inventors: Won Chul Do, Yong Jae Ko
  • Patent number: 9412696
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 9, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Patent number: 9412697
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 9, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Patent number: 9406611
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Patent number: 9406613
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Patent number: 9406610
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Patent number: 9406612
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 2, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Kenichi Watanabe
  • Patent number: 9398689
    Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and having a plurality of openings for correspondingly exposing the conductive pads; and a plurality of ring bodies formed in the openings and corresponding in position to edges of the conductive pads. As such, a plurality of conductive elements can be subsequently formed inside the ring bodies so as to be prevented by the ring bodies from expanding outward during a reflow process, thereby protecting the insulating layer from being compressed by the conductive elements and preventing cracking of the insulating layer.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: July 19, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-An Chang, Sung-Huan Sun, Wen-Kai Liao, Chien-Hung Wu, Yi-Cheih Chen
  • Patent number: 9391012
    Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
  • Patent number: 9384981
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate, forming a first electrode on the silicon carbide substrate, establishing ohmic contact between the silicon carbide substrate and the first electrode by irradiating the first electrode with laser beams, and forming a second electrode on the first electrode. In the step of establishing ohmic contact, a surface of the first electrode is irradiated with laser beams such that arithmetic mean roughness of a surface of the second electrode is not greater than 0.2 ?m.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 5, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideto Tamaso, Hiroyuki Kitabayashi, Keiji Wada
  • Patent number: 9379084
    Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: June 28, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9379075
    Abstract: A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 9379097
    Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: June 28, 2016
    Assignee: Apple Inc.
    Inventor: Chih-Ming Chung
  • Patent number: 9345148
    Abstract: A semiconductor device has a semiconductor die having a plurality of bumps formed over a surface of the semiconductor die. The bumps can include a fusible portion and non-fusible portion. Conductive traces are formed over the substrate with interconnect sites having an exposed sidewall and sized according to a design rule defined by SRO+2*SRR?2X, where SRO is an opening over the interconnect site, SRR is a registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The bumps are misaligned with the interconnect sites by a maximum distance of X which ranges from 5 to 20 microns. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: May 17, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9343452
    Abstract: A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hwan Yun, Jin-Taek Park
  • Patent number: 9337203
    Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 10, 2016
    Assignee: SK Hynix Inc.
    Inventors: Chang-Youn Hwang, Sang-Kil Kang, Ill-Hee Joe, Dae-Sik Park, Hae-Jung Park, Se-Han Kwon
  • Patent number: 9330823
    Abstract: An integrated circuit structure can include an interposer having a plurality of conductive layers and a die coupled to the interposer through an internal interconnect structure. The integrated circuit structure can include an inductor implemented within at least one of the conductive layers of the interposer. The inductor can include a first terminal and a second terminal. The first terminal and the second terminal can be coupled to the internal interconnect structure.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: May 3, 2016
    Assignee: XILINX, INC.
    Inventors: Arifur Rahman, Zhaoyin D. Wu, Namhoon Kim
  • Patent number: 9320151
    Abstract: A sleeve structure includes an electrically insulating protective sleeve having clips that retain and capture component pins and regulate a mounting distance of the electrical component from a wiring structure. A method of component wiring assembly is also included.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: April 19, 2016
    Assignee: General Electric Company
    Inventor: Khanh Q. Nguyen
  • Patent number: 9299648
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: March 29, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 9293432
    Abstract: A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: March 22, 2016
    Assignee: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
    Inventors: Chang-Ming Lin, Lei Shi, Haijun Shen
  • Patent number: 9283641
    Abstract: Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing a flux material on one or more pads of a package substrate, the flux material including a rosin material and a thixotropic agent and depositing one or more solder balls on the flux material disposed on the one or more pads, wherein depositing the one or more solder balls on the flux material is performed at a temperature greater than 80° C., and wherein the rosin material and the thixotropic agent are configured to resist softening at the temperature greater than 80° C. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: March 15, 2016
    Assignee: INTEL CORPORATION
    Inventors: Rajen S. Sidhu, Martha A. Dudek, Wei Tan
  • Patent number: 9269872
    Abstract: A method and system are provided for a molded electronic package geometry that enables control of warpage and die stress. A mold tool can be closed to define a space or cavity about a semiconductor die disposed on a substrate. Once the mold tool is closed, a mold material can be applied to the space to produce a mold cap. The mold cap geometry can have a first surface that is in contact with the surface of the substrate and a second surface that is opposite the first surface. The second surface can define a tapered portion of the mold cap in which the larger thickness of the tapered portion of the mold cap is in proximity to the semiconductor die and the smaller thickness of the tapered portion of the mold cap is away from the semiconductor die. The thickness of the tapered portion can vary linearly or non-linearly.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 23, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Bora Baloglu, Jeffrey R. Watson
  • Patent number: 9263322
    Abstract: Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Tian-Lin Chang, Jianfang Liang, Aaron Chen, Yew Tuck Clament Chow, Fan Zhang, Juan Boon Tan
  • Patent number: 9257398
    Abstract: A semiconductor device includes a first pad region including a plurality of first storage nodes, a second pad region neighboring the first pad region and including a plurality of second storage nodes, a coupling portion disposed between the first pad region and the second pad region, and a plate electrode disposed over the plurality of first storage nodes of the first pad region and the plurality of second storage nodes of the second pad region, and disposed in the coupling portion to interconnect the first pad region and the second pad region.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: February 9, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jung Sam Kim
  • Patent number: 9257329
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes densifying an upper-surface portion of an ILD layer of dielectric material that overlies a metallization layer above a semiconductor substrate to form a densified surface layer of dielectric material. The densified surface layer and the ILD layer are etched through to expose a metal line of the metallization layer.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: February 9, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Oliver Mieth, Carsten Peters, Torsten Huisinga
  • Patent number: 9245842
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first functional region of an integrated circuit over a workpiece, and forming a second functional region of the integrated circuit over the workpiece. The method includes forming a guard ring around the first functional region of the integrated circuit. The guard ring is formed in a material layer disposed over the first functional region and the second functional region.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Nien-Fang Wu, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • Patent number: 9240392
    Abstract: A method of fabricating embedded die packages including the following steps: obtaining a honeycomb array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket; placing the honeycomb array on a transparent tape so that an underside of the honey comb array contacts the transparent tape; positioning a chip terminal the down (flip chip) in each chip socket so that undersides of the dies contact the transparent tape; using optical imaging through the tape to align the chips with the via posts; applying a packing material over and around the chips in the honeycomb array, and curing the filler to embed the chips on five sides; thinning and planarizing the packing material to expose upper ends of the vias on upper side of the array; removing the transparent tape; applying a feature layer of conductors on the underside of the honeycomb array and the undersides of the chips, to couple at least
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: January 19, 2016
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co., Ltd.
    Inventors: Dror Hurwitz, Alex Huang
  • Patent number: 9224751
    Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: December 29, 2015
    Assignee: SK Hynix Inc.
    Inventors: Chan Sun Hyun, Myung Kyu Ahn, Woo June Kwon
  • Patent number: 9214428
    Abstract: A semiconductor device includes a copper-containing post overlying and electrically connected to a bond pad region. The semiconductor device further includes a protection layer on a surface of the copper-containing post, where the protection layer includes manganese.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Shi Liu, Chen-Hua Yu