Combined With Electrical Contact Or Lead Patents (Class 257/734)
  • Patent number: 9202841
    Abstract: A method of fabricating a semiconductor structure is disclosed, in which a pad above a connecting section and metal structures above a functional section are formed from the same metal layer. This design enables the simultaneous formation of the pad and the metal structures by forming a single metal layer and performing thereon a selective etching process, thereby leading to the advantages of process simplification, throughput improvement and cost reduction.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: December 1, 2015
    Assignee: OMNIVISION TECHNOLOGIES (SHANGHAI) CO., LTD.
    Inventors: Jiaming Xing, Jing Ye, Xifeng Gao, Zhetian Shi
  • Patent number: 9190295
    Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: November 17, 2015
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Patent number: 9190389
    Abstract: A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: November 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Joachim Mahler, Khalil Hosseini
  • Patent number: 9177885
    Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, said buffer layers having a Young's Modulus of 2.5GPa or less.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: November 3, 2015
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Simon Jonathan Stacey
  • Patent number: 9171791
    Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: October 27, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Baba, Toshihiro Iwasaki, Masaki Watanabe
  • Patent number: 9111923
    Abstract: A wiring substrate may include: a base having a predetermined thickness; a plurality of electrode portions formed to protrude on one surface in a thickness direction of the base; a wiring provided in the base and electrically connected to the electrode portions; and a resin layer formed on the base to fill between the plurality of electrode portions. An upper surface of the resin layer may be formed in a concave shape lower than a maximum height of the electrode portion, and an upper surface of the electrode portion and the upper surface of the resin layer form a continuous curved surface.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 18, 2015
    Assignee: OLYMPUS CORPORATION
    Inventors: Chihiro Migita, Hiroshi Kikuchi, Yoshiaki Takemoto, Yoshitaka Tadaki
  • Patent number: 9111870
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes encapsulating a device stack within a molded panel having a frontside and a backside. The device stack contains an upper semiconductor die and an interconnect buffer layer, which is formed over the upper semiconductor die and which is covered by the frontside of the molded panel. Material is removed from the frontside the molded panel to expose the interconnect buffer layer therethrough. One or more frontside redistribution layers are produced over the frontside of the molded panel and electrically coupled to the upper semiconductor die through the interconnect buffer layer. The molded panel is then singulated to yield a microelectronic package including a molded package body containing the device stack.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 18, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventor: Michael B. Vincent
  • Patent number: 9111064
    Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lai, Ming-Che Ho, Tzong-Hann Yang, Chien Rhone Wang, Chia-Tung Chang, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 9099302
    Abstract: Semiconductor devices are provided that include spacers on sidewalls of conductive lines, as well as methods for manufacturing the same. A method for manufacturing a semiconductor device includes forming bit lines on a semiconductor substrate. Triple-layered bit line spacers are formed on respective sidewalls of the bit lines. An interlayer insulation layer is formed on the bit lines and the triple-layered bit line spacers. Storage node contact plugs that penetrate the interlayer insulation layer are formed between the bit lines. Portions of the triple-layered bit line spacers are etched to form recessed regions. An insulation layer is formed on the substrate including the recessed regions. Storage node electrodes electrically connected to the storage node contact plugs are formed.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: August 4, 2015
    Assignee: SK hynix Inc.
    Inventor: Jong Pil Lee
  • Patent number: 9064805
    Abstract: Systems and methods are described for combining two or more thin-film electronic devices use a hot-press method. Two or more thin-film batteries, electrochromic devices, and/or a fuel cells may be combined. A thin-film conductive substrate is positioned between the thin-film electronic device. Sufficient heat is applied to the thin film conductive substrate and/or the connecting surface of the one or more devices to cause a material, such as lithium, to flow and bind the thin-film electronic devices together.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 23, 2015
    Assignee: ITN Energy Systems, Inc.
    Inventor: Jonathan Mack Frey
  • Patent number: 9064933
    Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 23, 2015
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Michael Newman, Charles G. Woychik, Terrence Caskey
  • Patent number: 9059162
    Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: June 16, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Kyu Ha, Kwan-Jai Lee, Jae-Min Jung, Kyong-Soon Cho, Na-Rae Shin, Kyoung-Suk Yang, Pa-Lan Lee, So-Young Lim
  • Patent number: 9047937
    Abstract: A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: June 2, 2015
    Assignee: Peking University
    Inventors: Jinfeng Kang, Bin Gao, Yuansha Chen, Bing Sun, Lifeng Liu, Xiaoyan Liu
  • Patent number: 9048149
    Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: June 2, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chia Lai, Hsien-Ming Tu, Tung-Liang Shao, Hsien-Wei Chen, Chang-Pin Huang, Ching-Jung Yang
  • Patent number: 9041181
    Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-chul Lee, Myung-kee Chung, Kun-dae Yeom
  • Publication number: 20150137348
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Publication number: 20150137347
    Abstract: An adhesive composition comprising silver particles containing silver atoms and zinc particles containing metallic zinc, wherein the silver atom content is 90 mass % or greater and the zinc atom content is from 0.01 mass % to 0.6 mass %, with respect to the total transition metal atoms in the solid portion of the adhesive composition.
    Type: Application
    Filed: June 14, 2013
    Publication date: May 21, 2015
    Inventors: Hideo Nakako, Toshiaki Tanaka, Michiko Natori, Dai Ishikawa, Hiroshi Matsumoto
  • Patent number: 9035454
    Abstract: Prepared in advance is a substrate formed of metallic material where slits are formed between mounting regions. Oxide films are generated all over the substrate including end faces of the substrate. Exposed are only lateral faces corresponding to the cross sections cut when tie bars are cut. This structure and the fabrication method minimize the area of cutting faces in the metallic material.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: May 19, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Nagamatsu, Mayumi Nakasato, Masurao Yoshii, Yasuhiro Kohara, Kotaro Deguchi
  • Publication number: 20150130075
    Abstract: Provided is a semiconductor device. A semiconductor chip is disposed on a substrate. A first magnetic substance, a second magnetic substance and a third magnetic substance which are spaced apart from one another are formed on the semiconductor chip. The first magnetic substance and the second magnetic substance can be adjacent an edge of the semiconductor chip. The third magnetic substance can be adjacent a center of the semiconductor chip. The third magnetic substance is between the first magnetic substance and the second magnetic substance.
    Type: Application
    Filed: July 14, 2014
    Publication date: May 14, 2015
    Inventors: Sang-Wook Ji, Hyoung-Yol Mun, Yeong-Lyeol Park, In-Kyum Lee
  • Publication number: 20150130082
    Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Shin-Puu Jeng, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang, Chun Hua Chang
  • Patent number: 9030007
    Abstract: A semiconductor device includes a first circuit base member including a surface having multiple first electrodes formed thereon, a second circuit base member being provided above the first circuit base member and having first through holes and second through holes formed respectively above the first electrodes, a semiconductor package provided above the second circuit base member, and multiple first bumps provided inside the first through holes and the second through holes to connect the first electrodes to the semiconductor package.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventor: Daisuke Mizutani
  • Patent number: 9030019
    Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Ludwig Heitzer
  • Patent number: 9030017
    Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 12, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 9029196
    Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: May 12, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Publication number: 20150123263
    Abstract: The invention relates to a method for joining a semiconductor (20) to a substrate (10), comprising the following steps: •applying a first paste layer (1) of a sintering paste to the substrate; •heating and compressing the first paste layer to form a first sintered layer; •applying a second paste layer (2) of a sintering paste to the first sintered layer and arranging a semiconductor (20) on the second paste layer; •heating and compressing the second paste layer (2) to form a second sintered layer. The invention further relates to a semiconductor component produced by means of the method.
    Type: Application
    Filed: April 2, 2013
    Publication date: May 7, 2015
    Inventors: Christiane Frueh, Michael Guenther, Thomas Herboth
  • Publication number: 20150123287
    Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a first substrate; disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; and performing a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole, thereby preventing a popcorn effect from occurring when the first substrate is heated and hence preventing delamination of the semiconductor package. Further, the cleaning hole facilitates to disperse thermal stresses so as to prevent warping of the first and second substrates during a chip-bonding or encapsulating process, thereby overcoming the conventional drawbacks of cracking of the supporting elements and a short circuit therebetween.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 7, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Chu-Chi Hsu, Lung-Yuan Wang, Cheng-Chia Chiang, Chia-Kai Shih
  • Patent number: 9024427
    Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: May 5, 2015
    Assignee: Freescale Semiconductor. Inc
    Inventors: Huan Wang, Aipeng Shu, Shu An Yao
  • Patent number: 9018744
    Abstract: A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Khalil Hosseini
  • Patent number: 9018758
    Abstract: A bump has a non-metal sidewall spacer on a lower sidewall portion of Cu pillar, and a metal top cap on a top surface and an upper sidewall portion of the Cu pillar. The metal top cap is formed by an electroless or immersion plating technique after the non-metal sidewall spacer formation.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Hui-Jung Tsai, Yi-Wen Wu, Chung-Shi Liu
  • Publication number: 20150108633
    Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side. The semiconductor device structure also includes devices formed on the front side of the substrate and interconnect structures formed on the devices. The semiconductor device structure further includes a protection layer formed on the back side of the substrate, and the protection layer has a thickness over about 10 A.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shyang TSAI, Wen-Han TAN, Wen-Lung HO
  • Patent number: 9013043
    Abstract: A semiconductor element includes: a transparent substrate; a stack structure formed on the transparent substrate and having a metal oxide layer partially exposed through sidewalls of the stack structure; a plurality of leads spacingly formed on the stack structure and extending to the sidewalls of the stack structure; an insulating film covering the exposed portions of the metal oxide layer; a metal film formed on the leads; and a solder mask layer disposed on the metal film, the stack structure and the insulating film. As such, the insulating film prevents short circuits from occurring between adjacent leads so as to improve the product yield.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: April 21, 2015
    Assignee: Xintec Inc.
    Inventor: Hung-Chang Chen
  • Patent number: 9013038
    Abstract: A semiconductor device, including a protective layer overlying a contact pad and a dummy pad on a semiconductor substrate, an interconnect structure overlying the protective layer and contacting part of the dummy pad through a contact via passing through the protective layer, a bump overlying the interconnect structure positioned over the dummy pad.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 9006890
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Shawna M Liff, Gregory S Clemons
  • Patent number: 9006884
    Abstract: A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 9006889
    Abstract: Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 14, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventor: Jaydutt J. Joshi
  • Patent number: 9006885
    Abstract: The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 14, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kunihiro Komiya
  • Publication number: 20150097282
    Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
  • Patent number: 9000587
    Abstract: A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded silicon chip is a thin chip (e.g., <50 ?m). In implementations, the wafer-level package device that employs the techniques of the present disclosure includes an active device wafer, a thin integrated circuit chip, an encapsulation structure covering at least a portion of the active device wafer and the thin integrated circuit chip, a redistribution layer structure, and at least one solder bump for providing electrical interconnectivity. Once the wafer is singulated into semiconductor devices, each semiconductor device including the embedded thin integrated circuit chip may be mounted to a printed circuit board.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 7, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Amit S. Kelkar, Vivek S. Sridharan
  • Patent number: 8994190
    Abstract: A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 31, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Trent S. Uehling
  • Patent number: 8994193
    Abstract: A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akihiko Tateiwa, Masato Tanaka, Akio Rokugawa
  • Patent number: 8994158
    Abstract: Semiconductor packages having lead frames include a lead frame, which supports a semiconductor chip and is electrically connected to the semiconductor chip by bonding wires, and a molding layer encapsulating the semiconductor chip. The lead frame includes first lead frames extending in a first direction and second lead frames extending in a second direction. The first lead frames may run across the semiconductor chip and support the semiconductor chip and the second lead frames may run across the bottom surface of the semiconductor chip.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyun Kim, Won-young Kim
  • Publication number: 20150084184
    Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.
    Type: Application
    Filed: November 28, 2014
    Publication date: March 26, 2015
    Inventors: Michio INOUE, Yorio TAKADA
  • Publication number: 20150084195
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Applicant: SECURE SILICON LAYER, INC.
    Inventor: William Eli Thacker, III
  • Publication number: 20150084183
    Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Joachim Patzer, Hans-Peter Moll
  • Publication number: 20150076506
    Abstract: This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer.
    Type: Application
    Filed: March 17, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida
  • Patent number: 8980696
    Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dominic Koey Poh Meng, Zhiwei Gong, Kesvakumar V. C. Muniandy, Weng Foong Yap
  • Patent number: 8981385
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate. The silicon carbide substrate is composed of an element region provided with a semiconductor element portion and a termination region surrounding the element region as viewed in a plan view. The semiconductor element portion includes a drift region having a first conductivity type. The termination region includes a first electric field relaxing region contacting the element region and having a second conductivity type different from the first conductivity type, and a second electric field relaxing region arranged outside the first electric field relaxing region as viewed in the plan view, having the second conductivity type, and spaced from the first electric field relaxing region. A ratio calculated by dividing a width of the first electric field relaxing region by a thickness of the drift region is not less than 0.5 and not more than 1.83.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8981550
    Abstract: A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 17, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Joon Young Park, Jin Suk Jeong, Kyeong Sool Seong, Seo Won Lee
  • Patent number: 8981557
    Abstract: A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 8981542
    Abstract: A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Toshio Hanada