Abstract: A chemical leadframe roughening process includes cleaning and chemically micro-etching a raw copper leadframe to remove organic material and oxide material from the surface. The surface of the leadframe is then roughened using an organic and peroxide solution, resulting in a finely pitted surface morphology. The roughened leadframe is cleaned to remove organic material, and then is plated with a lead-free plating material (such as a layered plating of nickel-palladium-gold (NiPdAu)) having a reflow temperature higher than the reflow temperature of lead-based solder. The plated leadframe exhibits the desired finely pitted morphology that is believed to provide for greater bonding with the mold compound used to make a finished integrated circuit package, thereby improving the moisture sensitivity level (MSL) performance of the package.

Abstract: An intermediate semiconductor structure and method for low-pressure wire bonding that reduces the propensity of dielectric material to mechanical failure due to any wire bonding stresses. Roughened surfaces such as metal pillars or metal dendrites are provided on a bonding pad, bonding wire or both. These roughened surfaces increase reactivity between the bond wire and the bond pad to form strong bonds. This increased activity as a result of the roughened bonding pad and/or wire surfaces reduce the amount of pressure, temperature and energy required for wire bonding, which in turn, avoids damage to the bonding pad as well as the semiconductor substrate.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: An integrated circuit is electrically connected with a plurality of pads. A passivation film covers a part of each of the pads and exposes the other part of each of the pads. Bumps are formed on the pads, respectively. Each of the bumps is a single layer disposed on a part of each of the pads exposed from the passivation film, and on the passivation film.

Abstract: There is disclosed a TAB style BGA type semiconductor device. This semiconductor device comprises a semiconductor chip on which an integrated circuit is formed, and a polyimide tape which has a conductive pattern and which is allowed to adhere to the semiconductor chip. The conductive pattern includes a bonding portion connected to the pad of the semiconductor chip, a pad portion connected to the outside electrode, and an electrically floating island-like portion in addition to a wiring portion for connecting the bonding portion and the pad portion.

Abstract: A bare chip carrier for holding a bare chip includes a bare chip carrier base member, a bump electrode which is located above a principal surface of the bare chip carrier base member and which is to be connected to a pad electrode of the bare chip, a bare chip carrier electrode which is formed on a back surface of the bare chip carrier base member and which has a recessed portion, and a wiring that connects the bump electrode to the bare chip carrier electrode.

Abstract: Method of manufacturing a circuit board and semiconductor device wherein the circuit board has a plurality of wiring patterns and protrusions located on the wiring patterns, the method including simultaneously and unitarily forming the wiring patterns and protrusions, and alternatively coupling electrically the protrusions with electrodes on a semiconductor chip component when present.

Abstract: Methods and apparatuses for packaging a microelectronic device. One embodiment can include a packaged microelectronic device comprising a microelectronic die, an interposer substrate, and a casing encapsulating at least a portion of the die. The microelectronic die can have a first side attached to the substrate, a plurality of contacts on the first side, and an integrated circuit coupled to the contacts. The die can also include a second side with a plurality of first interconnecting elements on the second side of the die, such as first non-planar features. The casing can include an interior surface and a plurality of second interconnecting elements on the interior surface, such as second non-planar features. The first non-planar features on the second side of the die mate with second non-planar features on the interior surface of the casing. Accordingly, delamination along the interface between the microelectronic die and the casing is inhibited.

Abstract: The invention includes a semiconductor device, and a method for making the same, wherein bumps of a semiconductor chip and inner leads of a film tape carrier can be securely bonded to each other by thermal welding using a heating unit. A semiconductor wafer 50 is etched using a potassium iodide or ammonium iodide solution. By the etching, a barrier metal layer 48 is removed while the upper face of a bump 10 is simultaneously roughened and many prominences 12 are formed. The formation of the prominences 12 increases the surface area of the upper face of the bump 10 and improves the bonding between the bump 10 of the semiconductor chip and the lead of the film tape carrier.

Abstract: Digital circuitry, such as interconnective pads which are patterned as waffles according to the embossing methods for flexible substrates which are disclosed, so as to be especially suited for the interconnection of stacks of circuitry blocks forming digital memory known as Permanent Inexpensive, Rugged Memory (PIRM) cross point arrays.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bump formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film formed in at least a peripheral portion of the bump to cover an interface of the bump and the intermediate layer which is exposed to a side surface of the bump.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, the method may form a surface in which an upper surface of the fill layer is substantially level with at least one of the peaks associated with the surface roughness of the metal layer. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In other cases, the method may include forming a surface in which the fill layer is arranged above the metal layer-fill layer interface. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained.

Abstract: A non-leaded semiconductor package and method of fabricating the same is proposed, which can be used for the fabrication of a non-leaded type of semiconductor package, such as a CQFN (Carrierless Quad Flat No-lead) package. The proposed semiconductor packaging technology is characterized by the use of a metal plate as provisional chip carrier during fabrication and by the use of RDL (Redistribution Layer) technology to provide internal electrical interconnections between the I/O pads of the packaged chip and the non-leaded external electrical contacts. These features allow the fabrication of the CQFN package to be implemented without the use of bonding wires for internal electrical connections and without the use of substrate as a permanent chip carrier.

Abstract: An integrated vacuum package having an added volume on a perimeter within the perimeter of a bonding seal between two wafers. The added volume of space may be an etching of material from the inside surface of the top wafer. This wafer may have vent holes that may be sealed to maintain a vacuum within the volume between the two wafers after the pump out of gas and air. The inside surface of the top wafer may have an anti-reflective pattern. Also, an anti-reflective pattern may be on the outside surface of the top wafer. The seal between the two wafers may be ring-like and have a spacer material. Also, it may have a malleable material such as solder to compensate for any flatness variation between the two facing surfaces of the wafers.

Abstract: A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.

Abstract: An integrated circuit having multiple power/ground connections to a single external terminal and method for manufacturing an integrated circuit provides an integrated circuit having a reduced number of external power/ground terminals. The multiple connections may be made by conductive circuit paths on one side of the substrate and a terminal pad on the same side of the substrate, with the conductive circuit paths leading from die terminals terminating at the terminal pad, or a via may be formed either directly above the terminal pad or contacting its circumference to provide a connection through from the opposite side of the substrate. Multiple vias may be formed above the terminal pad and within its circumference to provide connection of multiple die terminals to the terminal pad.

Abstract: A semiconductor device comprising: a substrate (30) including a plurality of holes (36) and a surface over which an interconnecting pattern (32) is formed, part of the interconnecting pattern (32) being superposed over the holes (36); a semiconductor chip (10) including a plurality of electrodes (12) which are disposed over another surface of the substrate (30) to correspond to the holes (36); and conductive members provided within the holes (36) for electrically connecting the electrodes (12) to the interconnecting pattern (32)

Abstract: The invention relates to an electronic device and a semiconductor wafer and also to a method for producing the device and wafer. The electronic device comprises at least one semiconductor chip obtained from corresponding chip positions of a semiconductor wafer constructed according the invention. In this case, the semiconductor chip has two topmost metallization layers that have area-covering voltage supply structures, insulation layers arranged in between, and passage contacts to module regions of an integrated circuit. The voltage supply structure has a grid of supply interconnects arranged parallel to one another. This grid is rotated with respect to a grid of a subsequent metallization layer.

Abstract: In order to improve adhesion between a plated film which functions as an external connection terminal of a semiconductor device and a surface of a resin protuberance and to improve reliability, a carrier substrate includes a metal substrate which is shaped into a sheet form, to which a semiconductor chip is fixed, and which is removed before the semiconductor device is completed, a recess formed at a position of the metal substrate corresponding to the resin protuberance and having a rugged bottom surface and/or a rugged side surface, and a plated film formed on the inner surface of the recess.

Abstract: Methods for attaching an integrated circuit die to a substrate. Specifically, substrates which are used for BOC/COB or F/C surface mounting comprise protrusions on the surface of the substrate. The protrusions are configured to form barriers to hold an adhesive paste within the barriers. An integrated circuit die is disposed on the top of the barriers and coupled to the substrate by the adhesive paste.

Abstract: A probe unit has a plurality of metal leads regularly juxtaposed on the surface of a substrate. Each metal lead has a resilient contact piece in a front portion of the lead, the resilient contact piece being spaced apart from the substrate surface or extending over an edge of the substrate. The cross sectional shape of the resilient contact piece is an arc shape and/or has a projection near at the distal end of the resilient contact piece.

Abstract: The invention includes a semiconductor device, and a method for making the same, wherein bumps of a semiconductor chip and inner leads of a film tape carrier can be securely bonded to each other by thermal welding using a heating unit. A semiconductor wafer 50 is etched using a potassium iodide or ammonium iodide solution. By the etching, a barrier metal layer 48 is removed while the upper face of a bump 10 is simultaneously roughened and many prominences 12 are formed. The formation of the prominences 12 increases the surface area of the upper face of the bump 10 and improves the bonding between the bump 10 of the semiconductor chip and the lead of the film tape carrier.

Abstract: A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.

Abstract: Parts of pad electrodes formed on an interconnection board so as to correspond to bump electrodes of a semiconductor pellet that neighbor parts superposed with the bump electrodes are caused to extend in substantially the same direction, and ultrasonic vibration is applied in this extension direction so as to make a connection between the pad electrodes and the bump electrodes.

Abstract: A TFT array panel and a method for fabricating the same is disclosed, wherein an adhesion force between an elongated wire and a TFT array panel pad is improved by increasing the contact area of a bonding pad. The TFT array panel pad includes a first conductive layer formed in a pad region on an insulating substrate. The first conductive layer includes a plurality of conductive islands and holes. A second conductive layer is formed over and covers the first conductive layer.

Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Abstract: While a transfer surface 10a of a transfer plate 10 having a predetermined surface roughness is brought into contact with a plurality of bumps 44B on a contact sheet 44 formed on a substrate 44M having the coefficient of linear expansion larger than that of the transfer plate 10 at a predetermined pressure, the substrate 44M and the transfer plate 10 are heated to a predetermined temperature to recover the surface roughness of the bump 44B to a predetermined value.

Abstract: The present invention is a semiconductor device with improved adhesion properties of a resin with a wiring pattern, comprising a film fragment 14 having a patterned wiring pattern 16 including a projection 17, a semiconductor chip 12 having electrodes 13 bonded to the projection 17, and a resin 19 provided to the wiring pattern 16 in the region other than that of the projection 17; and the wiring pattern 16 has its surface of contact with the resin 19 roughened.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract: An electronic component includes a projection electrode to be bonded to a circuit board. The projection electrode is prevented from being contaminated or oxidized during a period from manufacturing of the electronic component until mounting of the component to the circuit board. Methods of manufacturing the electronic component and an electronic circuit device are also provided. The electronic component includes the projection electrode formed on a connection terminal on a substrate having a circuit element and a protective film for covering the circuit element and the projection electrode. The projection electrode is prevented from being contaminated or oxidized since the manufacturing of the electronic component until mounting thereof to the circuit board, and reliable bonding of the projection electrode to a connection terminal of the circuit board can be realized.

Abstract: A stacked structure of a BGA (Ball Grid Array) integrated circuit package arranged on a printed circuit board includes a lower IC package body, an upper IC package body and glue. The lower IC package body has a first surface and a second surface opposite to the first surface. The first surface is formed with a plurality of first contacts for electrically connecting to the printed circuit board. The second surface is formed with a plurality of second contacts for electrically connecting to the upper IC package body. The upper IC package body is stacked above the lower IC package body and electrically connected to the second contacts on the second surface of the lower IC package body. The glue is provided between the lower IC package body and the upper IC package body for covering and protecting the plurality of second contacts.

Abstract: A semiconductor structure includes a semiconductor substrate and a compliant interconnect element disposed on a first surface of the substrate. The compliant interconnect element defines a chamber between the first surface of the substrate and a surface of the compliant interconnect element. The compliant interconnect element can be a compliant layer. The compliant layer can be formed of a polymer, such as silicone. A conductive layer can be disposed on the compliant layer, in contact with a contact pad on the semiconductor substrate. A method for forming a semiconductor structure includes providing a semiconductor substrate and providing a compliant interconnect element on a first surface of the substrate, so that the compliant interconnect element defines a chamber between the compliant interconnect element and the first surface of the substrate.

Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.

Abstract: Methods are disclosed for manufacturing semiconductor device dies and for removing material from the bottom side of the wafer dies, wherein a contoured surface is provided on the die bottom, such as through an etching process. In addition, methods are disclosed for securing a semiconductor device to a surface. Semiconductor wafers and die are also disclosed having contoured bottom surfaces.

Abstract: A method and apparatus for attaching an integrated circuit die to a substrate. Specifically, substrates which are used for BOC/COB or F/C surface, mounting comprise protrusions on the surface of the substrate. The protrusions are configured to form barriers to hold an adhesive paste within the barriers. An integrated circuit die is disposed on the top of the barriers and coupled to the substrate by the adhesive paste.

Abstract: The dimension measurement and management of a mask or a wafer are facilitated by using a dummy pattern having a configuration and arrangement capable of achieving a plurality of objects. In the entire region or a major region of an optional wiring layer on a semiconductor chip and in the space between the adjacent patterns in an actual pattern portion, dummy patterns for controlling the coverage and density of a pattern in the wiring layer are regularly arranged. All or some of the dummy patterns are dummy patterns for the dimension measurement including the main size (width and distance) required for the dimension management of the wiring layer.

Abstract: A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

Abstract: An interconnect for testing semiconductor components having both bumped contacts, and planar contacts, is provided. The interconnect includes: a substrate, first contacts on the substrate for electrically engaging the bumped contacts, and second contacts on the substrate for electrically engaging the planar contacts. In illustrative embodiments the first contacts include recesses in the substrate covered with a conductive layer, or recesses formed in a compliant layer on the substrate, or conductive polymer donuts sized and shaped to retain the bumped contacts. In illustrative embodiments the second contacts include etched pillars having penetrating projections, or conductive polymer bumps having penetrating particles, or flat topped projections having a compliant layer thereon. The interconnect can be used to construct a die level test carrier for testing components in singulated form, or to construct a wafer level test carrier for testing components in wafer or panel form.

Abstract: There is provided a semiconductor device including a semiconductor pellet having a plurality of bump electrodes on a surface thereof, a wiring board having a plurality of pad electrodes on a surface thereof, each one of the pad electrodes being engaged to an associated one of the bump electrodes when the wiring board is coupled to the semiconductor pellet, and a resin layer sandwiched between the semiconductor pellet and the wiring board for connecting them with each other therethrough, each of the bump electrodes being formed with one of a projection and a recess into which the projection is able to be fit, and each of the pad electrodes being formed with the other. For instance, the bump electrodes are formed by compressing a molten ball formed at a tip end of a gold wire onto the semiconductor pellet, and the projection is formed on the bump electrodes by cutting the gold wire so that a tip end portion of the gold wire leaves on the bump electrodes.

Abstract: A semiconductor apparatus includes a mount pad formed on a substrate and a bump formed on a semiconductor device. A plurality of needle-like or branch-like protrusions is formed on at least one of the mount pad and the bump. The plurality of protrusions of one of the mount pad and the bump engages with the other. The plurality of protrusions protrudes in directions crossing each other, or protrudes to random directions.

Abstract: Surface mount device packages with increased mounting strength and a method therefor. In one embodiment, an, electronic device is made up of a device package and one or more electrically conductive terminals. For surface mounting, the device terminals are each provided with a mounting surface which is bonded using a conductive adhesive to a corresponding contact pad on a circuit board. The terminals are further provided with at least one groove across the mounting surface. When conductive adhesive is used to mount the device on a circuit board, this groove serves to form the conductive adhesive into a ridge or “dam” over the contact pad. This provides increased mounting strength which may eliminate the need for additional adhesive material to provide side reinforcement of the device, and thereby allow an increase in the packing density of devices on the circuit board.

Abstract: An electronic component with an electronic circuit and electrical contacts, disposed at least on a first surface of the electronic component, for the electrical bonding of the electronic circuit includes at least one flexible elevation of an insulating material disposed on the first surface, at least one electrical contact disposed on the flexible elevation, and a conduction path disposed on the surface or in the interior of the flexible elevation between the electrical contact and the electronic circuit. A method for producing the electronic component is also provided.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: An electro-optical, ridge-waveguide device and method for its fabrication utilizes a polyimide ridge-protection layer, which provides good ridge protection/planarization while minimizing parasitic capacitance. A silicon oxide interlayer is used between a metal contact layer and the polyimide. This interlayer facilitates the adhesion between the metal contact layer and the underlying device since good adhesion can be obtained between the silicon oxide layer and the polyimide layer and between the metal layer and silicon oxide layer. Preferably, the polyimide is roughened to increase the surface area contact between the polyimide layer and silicon oxide layer to further increase adhesion and thus the pull-off force required to separate the metal contact layer from the device. While such roughening can be achieved through plasma etching, in a preferred embodiment, the polyimide layer is roughened by patterned etching.

Abstract: A tape carrier package (TCP) with improved connecting terminals is disclosed. The TCP includes a base film of non-conductive material which carries a plurality of conductive leads on one surface thereof. A plurality of connecting terminals are deposited on the surface such as to be electrically interconnected to the ends of the conductive leads. Each of the connecting terminals has an acute-angled top portion and includes an inner member of a first material and an outer member of a second material plated on the inner member. The acute-angled top portion of the second material is easily deformable when the connecting terminal is pressed against a corresponding terminal provided on a board to be interconnected to the TCP. Thus, an adequate interconnection area is obtained between the TCP and the circuit provided on the board.

Abstract: A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134).

Abstract: Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.

Abstract: A carrier element for a semiconductor chip which can be incorporated in smart cards and soldered onto circuit boards using SMD technology. For this purpose, a copper lamination of a plastic sheet is structured by etching in such a way that contact areas are formed in one piece with conductor tracks which end at the edge of the carrier element and enable reliable soldering.