Abstract: A device including a first substrate in which a functional element and an electrode are formed; a second substrate in which a through electrode is formed; a joining material that joins the first substrate and the second substrate while reserving a predetermined space between the functional element and the second substrate; and a conductive material that electrically connects the electrode to the through electrode. Here, the joining material is harder than the conductive material, and the joining material is electrically less conductive than the conductive material.

Abstract: By forming a metal layer 14 on at least one of a connecting electrode 12 of a first substrate 10 and a connecting electrode 17 of a second substrate 15, placing the first substrate 10 and the second substrate 15 together in order that the connecting electrode 12 and the connecting electrode 17 face opposite to each other via the metal layer 14, increasing temperature up to anodic bonding temperature, and applying DC voltage between the first substrate 10 and the second substrate 15 while maintaining that temperature, the first substrate 10 and the second substrate 15 are anodically bonded, and at the same time by melting the metal layer 14, the connecting electrode 12 and the connecting electrode 17 are electrically connected. The method achieves anodic bonding of substrates with high yield and at the same time establishes wiring connection, effective for packaging.

Abstract: An organic light-emitting display device comprises a substrate, an anode electrode formed on the substrate, an organic layer formed on the anode electrode, a cathode electrode formed on the organic layer, and an organic capping layer formed on the cathode electrode and containing a capping organic material and a rare-earth material which has higher oxidizing power than the material which forms the cathode electrode.

Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.

Abstract: A semiconductor device includes a substrate, a surface electrode of aluminum-containing material formed on the substrate, a metal film of solderable material formed on the surface electrode, and an end-securing film securing an end of the metal film and having a portion on the surface electrode and also having an overlapping portion which is formed integrally with the portion on the surface electrode and which overlaps the end of the metal film.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a precursor. A decomposable polymer layer (DPL) is deposited between the conductive features of the precursor. The DPL is annealed to form an ordered periodic pattern of different types of polymer nanostructures. One type of polymer nanostructure is decomposed by a first selectively to form a trench. The trench is filled by a dielectric layer to form a dielectric block. The remaining types of polymer nanostructures are decomposed by a second selectively etching to form nano-air-gaps.

Abstract: A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening.

Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.

Abstract: A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. In one embodiment a first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract: A semiconductor package is provided, including a carrier having electrical connecting pads, a semiconductor element disposed on the carrier and having electrode pads, conductive elements electrically connected to the electrode pads and the electrical connecting pads, fluorine ions formed between the conductive elements and the electrode pads or between the conductive elements and the electrical connecting pads, and an encapsulant formed on the carrier and the conductive elements, wherein the electrode pads or the electrical connecting pads are formed by aluminum materials to form fluorine aluminum by way of packaging the fluorine ions after the completion of the packaging process. Accordingly, the corrosion resistance of the semiconductor package is increased.

Abstract: A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract: A laminated graphene device is demonstrated as a cathode. In one example the devices include organic photovoltaic devices. The measured properties demonstrate work-function matching via contact doping. Devices and method shown also provide increased power conversion efficiency due to transparency. These findings indicate that flexible, light-weight all carbon devices, such as solar cells, can be constructed using graphene as the cathode material.

Abstract: An anisotropic conductive film composition for bonding an electronic device may include a hydrogenated bisphenol A epoxy monomer represented by Formula 1 or a hydrogenated bisphenol A epoxy oligomer represented by Formula 2: where n may be an integer from 1 to about 50.

Abstract: A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film.

Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.

Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.

Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width.

Abstract: One illustrative device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in the layer of insulating material and a bi-layer cap layer comprised of a first layer of material positioned on the copper-based conductive structure and a second layer of material positioned on the first layer of material. One method disclosed herein includes forming a copper-based conductive structure in a first layer of insulating material, forming a first layer of a bi-layer cap layer on the copper-based conductive structure, the first layer being comprised of silicon carbon nitride, forming a second layer of the bi-layer cap layer on the first layer, the second layer being comprised of silicon nitride, and forming a second layer of insulating material above the second layer.

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract: A MEMS device comprises a substrate for manufacturing a moving MEMS component is divided into two electrically isolated conducting regions to allow the moving MEMS component and a circuit disposed on its surface to connect electrically with another substrate below respectively through their corresponding conducting regions, thereby the electrical conducting paths and manufacturing process can be simplified.

Abstract: A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer.

Abstract: Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch of a set of traces defines a center to center distance between two neighboring traces, or bonding pads on a substrate. The first die is coupled to the substrate by a thermal compression bonding process. In some implementations, the first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. In some implementations, the second die is coupled to the second set of traces of the substrate.

Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Abstract: A semiconductor component having wettable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.

Abstract: Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material.

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Abstract: A high-frequency transmission module includes a first chip, a second chip, and a conductive wire. The first chip includes a first top surface and a number of pads arranged along a periphery of the first top surface. The pads include a first bonding pad. The second chip includes a second top surface and a second bonding pad on the second top surface. The second chip is positioned on the first top surface such that the pads are uncovered by the second chip and the second bonding pad is mostly closed to the first bonding pad. The conductive wire bonds to the first bonding pad and the second bonding pad to electrically connect the second chip to the first chip and is configured to transmit high-frequency signals between the first chip and the second chip.

Abstract: A method of increasing a work function of an electrode is provided. The method comprises obtaining an electronegative species from a precursor using electromagnetic radiation and reacting a surface of the electrode with the electronegative species. An electrode comprising a functionalized substrate is also provided.

Abstract: One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.

Abstract: In a semiconductor diamond device, there is provided an ohmic electrode that is chemically and thermally stable and has an excellent low contact resistance and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni and Cr such as Ni6Cr2 or Ni72Cr18Si10, which is chemically and thermally stable, is formed on a semiconductor diamond by a sputtering process and so forth, to thereby obtain the semiconductor diamond device provided with an excellent ohmic electrode. If heat treatment is applied after forming the nickel-chromium alloy or compound, it is improved in characteristics.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.

Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.

Abstract: A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Abstract: According to an exemplary embodiment of the invention, systems and methods are provided for producing low work function electrodes. According to an exemplary embodiment, a method is provided for reducing a work function of an electrode. The method includes applying, to at least a portion of the electrode, a solution comprising a Lewis basic oligomer or polymer; and based at least in part on applying the solution, forming an ultra-thin layer on a surface of the electrode, wherein the ultra-thin layer reduces the work function associated with the electrode by greater than 0.5 eV. According to another exemplary embodiment of the invention, a device is provided. The device includes a semiconductor; at least one electrode disposed adjacent to the semiconductor and configured to transport electrons in or out of the semiconductor.

Abstract: A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners of the substrate, the at least one stress relief structure being adjacent to at least one die of the one or more dies.

Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract: A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer.

Abstract: The present invention discloses an integrated circuit (IC) comprising a bond pad (160); a substrate stack carrying a first layer (130) comprising conductive regions (135); and an interconnect layer (140) over the first layer (130) comprising a dielectric material portion (400) between the bond pad (160) and the substrate stack, said portion comprising a plurality of air-filled trenches (345) defining at least one pillar (340) of the dielectric material (400), at least said air-filled trenches (345) being capped by a porous capping layer (440). The interconnect layer (140), which typically is one of the uppermost interconnect layers of the IC, has an improved resilience to pressure exerted on the bond pad (160). The present invention further teaches a method for manufacturing such an IC.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 ? or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.

Abstract: An integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.

Abstract: There is a highly reliable semiconductor module having a satisfactory bonding strength in the electrical bonded portion. In the semiconductor module 10, a semiconductor chip 11 is mounted on a circuit board 20. In the circuit board 20, on an insulating ceramic substrate 21 is formed a metal circuit plate 22 on which the semiconductor chip 11 is implemented. The semiconductor chip 11 and metal circuit plate 22 are connected with each other by an aluminum bonding wire 23. In the connected portion between the metal circuit plate 22 and bonding wire 23, a coating layer 24 for excellent conjunction therebetween is mounted. The coating layer 24, as shown in an enlarged diagram, is made up of a nickel (Ni) layer 241, a P-distributed palladium (Pd) layer 242, and an Au layer 243 in increasing order. To the P-distributed Pd layer 242 is added P (phosphorous) and, the P concentration on the Ni layer 241 is higher than that on the Au layer side 243.